Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
Summary:
This clang-tidy check is looking for unsigned integer variables whose initializer
starts with an implicit cast from llvm::Register and changes the type of the
variable to llvm::Register (dropping the llvm:: where possible).
Partial reverts in:
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
X86FixupLEAs.cpp - Some functions return unsigned and arguably should be MCRegister
X86FrameLowering.cpp - Some functions return unsigned and arguably should be MCRegister
HexagonBitSimplify.cpp - Function takes BitTracker::RegisterRef which appears to be unsigned&
MachineVerifier.cpp - Ambiguous operator==() given MCRegister and const Register
PPCFastISel.cpp - No Register::operator-=()
PeepholeOptimizer.cpp - TargetInstrInfo::optimizeLoadInstr() takes an unsigned&
MachineTraceMetrics.cpp - MachineTraceMetrics lacks a suitable constructor
Manual fixups in:
ARMFastISel.cpp - ARMEmitLoad() now takes a Register& instead of unsigned&
HexagonSplitDouble.cpp - Ternary operator was ambiguous between unsigned/Register
HexagonConstExtenders.cpp - Has a local class named Register, used llvm::Register instead of Register.
PPCFastISel.cpp - PPCEmitLoad() now takes a Register& instead of unsigned&
Depends on D65919
Reviewers: arsenm, bogner, craig.topper, RKSimon
Reviewed By: arsenm
Subscribers: RKSimon, craig.topper, lenary, aemerson, wuzish, jholewinski, MatzeB, qcolombet, dschuff, jyknight, dylanmckay, sdardis, nemanjai, jvesely, wdng, nhaehnle, sbc100, jgravelle-google, kristof.beyls, hiraditya, aheejin, kbarton, fedor.sergeev, javed.absar, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, tpr, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, Jim, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65962
llvm-svn: 369041
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index fbf81c2..44d0233 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -455,7 +455,7 @@
if (MO.isUndef())
return;
- unsigned PhysReg = MO.getReg();
+ Register PhysReg = MO.getReg();
assert(Register::isPhysicalRegister(PhysReg) && "Bad usePhysReg operand");
markRegUsedInInstr(PhysReg);
@@ -645,7 +645,7 @@
unsigned C = 0;
for (const MachineInstr &MI : MRI->def_instructions(VirtReg)) {
if (isCoalescable(MI)) {
- unsigned Reg = MI.getOperand(1).getReg();
+ Register Reg = MI.getOperand(1).getReg();
Reg = traceCopyChain(Reg);
if (Reg != 0)
return Reg;
@@ -750,7 +750,7 @@
void RegAllocFast::allocVirtRegUndef(MachineOperand &MO) {
assert(MO.isUndef() && "expected undef use");
- unsigned VirtReg = MO.getReg();
+ Register VirtReg = MO.getReg();
assert(Register::isVirtualRegister(VirtReg) && "Expected virtreg");
LiveRegMap::const_iterator LRI = findLiveVirtReg(VirtReg);
@@ -889,7 +889,7 @@
SmallSet<unsigned, 8> ThroughRegs;
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) ||
@@ -904,7 +904,7 @@
LLVM_DEBUG(dbgs() << "\nChecking for physdef collisions.\n");
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || !MO.isDef()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg || !Register::isPhysicalRegister(Reg))
continue;
markRegUsedInInstr(Reg);
@@ -919,7 +919,7 @@
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
MachineOperand &MO = MI.getOperand(I);
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
if (MO.isUse()) {
@@ -945,7 +945,7 @@
for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
const MachineOperand &MO = MI.getOperand(I);
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
if (!MO.isEarlyClobber())
@@ -960,7 +960,7 @@
UsedInInstr.clear();
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg || !Register::isPhysicalRegister(Reg))
continue;
LLVM_DEBUG(dbgs() << "\tSetting " << printReg(Reg, TRI)
@@ -1043,7 +1043,7 @@
continue;
}
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg) continue;
if (Register::isVirtualRegister(Reg)) {
VirtOpEnd = i+1;
@@ -1094,7 +1094,7 @@
for (unsigned I = 0; I != VirtOpEnd; ++I) {
MachineOperand &MO = MI.getOperand(I);
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
if (MO.isUse()) {
@@ -1123,7 +1123,7 @@
for (MachineOperand &MO : MI.uses()) {
if (!MO.isReg() || !MO.isUse())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
continue;
@@ -1138,7 +1138,7 @@
if (hasEarlyClobbers) {
for (const MachineOperand &MO : MI.operands()) {
if (!MO.isReg()) continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg || !Register::isPhysicalRegister(Reg))
continue;
// Look for physreg defs and tied uses.
@@ -1166,7 +1166,7 @@
const MachineOperand &MO = MI.getOperand(I);
if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Reg || !Register::isPhysicalRegister(Reg) || !MRI->isAllocatable(Reg))
continue;
@@ -1179,7 +1179,7 @@
const MachineOperand &MO = MI.getOperand(I);
if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
continue;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
// We have already dealt with phys regs in the previous scan.
if (Register::isPhysicalRegister(Reg))
@@ -1214,7 +1214,7 @@
// mostly constants and frame indices.
if (!MO.isReg())
return;
- unsigned Reg = MO.getReg();
+ Register Reg = MO.getReg();
if (!Register::isVirtualRegister(Reg))
return;