Revert r351778: IR: Add fp operations to atomicrmw
This broke the RISCV build, and even with that fixed, one of the RISCV
tests behaves surprisingly differently with asserts than without,
leaving there no clear test pattern to use. Generally it seems bad for
hte IR to differ substantially due to asserts (as in, an alloca is used
with asserts that isn't needed without!) and nothing I did simply would
fix it so I'm reverting back to green.
This also required reverting the RISCV build fix in r351782.
llvm-svn: 351796
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index d9e9d73..9168648 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -8667,18 +8667,15 @@
- min
- umax
- umin
-- fadd
-- fsub
For most of these operations, the type of '<value>' must be an integer
type whose bit width is a power of two greater than or equal to eight
and less than or equal to a target-specific size limit. For xchg, this
may also be a floating point type with the same size constraints as
-integers. For fadd/fsub, this must be a floating point type. The
-type of the '``<pointer>``' operand must be a pointer to that type. If
-the ``atomicrmw`` is marked as ``volatile``, then the optimizer is not
-allowed to modify the number or order of execution of this
-``atomicrmw`` with other :ref:`volatile operations <volatile>`.
+integers. The type of the '``<pointer>``' operand must be a pointer to
+that type. If the ``atomicrmw`` is marked as ``volatile``, then the
+optimizer is not allowed to modify the number or order of execution of
+this ``atomicrmw`` with other :ref:`volatile operations <volatile>`.
A ``atomicrmw`` instruction can also take an optional
":ref:`syncscope <syncscope>`" argument.
@@ -8704,8 +8701,6 @@
comparison)
- umin: ``*ptr = *ptr < val ? *ptr : val`` (using an unsigned
comparison)
-- fadd: ``*ptr = *ptr + val`` (using floating point arithmetic)
-- fsub: ``*ptr = *ptr - val`` (using floating point arithmetic)
Example:
""""""""
diff --git a/llvm/include/llvm/Bitcode/LLVMBitCodes.h b/llvm/include/llvm/Bitcode/LLVMBitCodes.h
index ce853cd..e694331 100644
--- a/llvm/include/llvm/Bitcode/LLVMBitCodes.h
+++ b/llvm/include/llvm/Bitcode/LLVMBitCodes.h
@@ -406,9 +406,7 @@
RMW_MAX = 7,
RMW_MIN = 8,
RMW_UMAX = 9,
- RMW_UMIN = 10,
- RMW_FADD = 11,
- RMW_FSUB = 12
+ RMW_UMIN = 10
};
/// OverflowingBinaryOperatorOptionalFlags - Flags for serializing
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 850b9e2..3886ac5 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -1715,9 +1715,8 @@
/// Returns how the IR-level AtomicExpand pass should expand the given
/// AtomicRMW, if at all. Default is to never expand.
- virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *RMW) const {
- return RMW->isFloatingPointOperation() ?
- AtomicExpansionKind::CmpXChg : AtomicExpansionKind::None;
+ virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
+ return AtomicExpansionKind::None;
}
/// On some platforms, an AtomicRMW that never actually modifies the value
diff --git a/llvm/include/llvm/IR/Instructions.h b/llvm/include/llvm/IR/Instructions.h
index beadf73..c720dd8 100644
--- a/llvm/include/llvm/IR/Instructions.h
+++ b/llvm/include/llvm/IR/Instructions.h
@@ -724,14 +724,8 @@
/// *p = old <unsigned v ? old : v
UMin,
- /// *p = old + v
- FAdd,
-
- /// *p = old - v
- FSub,
-
FIRST_BINOP = Xchg,
- LAST_BINOP = FSub,
+ LAST_BINOP = UMin,
BAD_BINOP
};
@@ -753,16 +747,6 @@
static StringRef getOperationName(BinOp Op);
- static bool isFPOperation(BinOp Op) {
- switch (Op) {
- case AtomicRMWInst::FAdd:
- case AtomicRMWInst::FSub:
- return true;
- default:
- return false;
- }
- }
-
void setOperation(BinOp Operation) {
unsigned short SubclassData = getSubclassDataFromInstruction();
setInstructionSubclassData((SubclassData & 31) |
@@ -820,10 +804,6 @@
return getPointerOperand()->getType()->getPointerAddressSpace();
}
- bool isFloatingPointOperation() const {
- return isFPOperation(getOperation());
- }
-
// Methods for support type inquiry through isa, cast, and dyn_cast:
static bool classof(const Instruction *I) {
return I->getOpcode() == Instruction::AtomicRMW;
diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp
index 855c5d2..20d9606 100644
--- a/llvm/lib/AsmParser/LLParser.cpp
+++ b/llvm/lib/AsmParser/LLParser.cpp
@@ -6815,7 +6815,6 @@
AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
SyncScope::ID SSID = SyncScope::System;
bool isVolatile = false;
- bool IsFP = false;
AtomicRMWInst::BinOp Operation;
if (EatIfPresent(lltok::kw_volatile))
@@ -6834,14 +6833,6 @@
case lltok::kw_min: Operation = AtomicRMWInst::Min; break;
case lltok::kw_umax: Operation = AtomicRMWInst::UMax; break;
case lltok::kw_umin: Operation = AtomicRMWInst::UMin; break;
- case lltok::kw_fadd:
- Operation = AtomicRMWInst::FAdd;
- IsFP = true;
- break;
- case lltok::kw_fsub:
- Operation = AtomicRMWInst::FSub;
- IsFP = true;
- break;
}
Lex.Lex(); // Eat the operation.
@@ -6858,25 +6849,18 @@
if (cast<PointerType>(Ptr->getType())->getElementType() != Val->getType())
return Error(ValLoc, "atomicrmw value and pointer type do not match");
- if (Operation == AtomicRMWInst::Xchg) {
- if (!Val->getType()->isIntegerTy() &&
- !Val->getType()->isFloatingPointTy()) {
- return Error(ValLoc, "atomicrmw " +
- AtomicRMWInst::getOperationName(Operation) +
- " operand must be an integer or floating point type");
- }
- } else if (IsFP) {
- if (!Val->getType()->isFloatingPointTy()) {
- return Error(ValLoc, "atomicrmw " +
- AtomicRMWInst::getOperationName(Operation) +
- " operand must be a floating point type");
- }
- } else {
- if (!Val->getType()->isIntegerTy()) {
- return Error(ValLoc, "atomicrmw " +
- AtomicRMWInst::getOperationName(Operation) +
- " operand must be an integer");
- }
+ if (Operation != AtomicRMWInst::Xchg && !Val->getType()->isIntegerTy()) {
+ return Error(ValLoc, "atomicrmw " +
+ AtomicRMWInst::getOperationName(Operation) +
+ " operand must be an integer");
+ }
+
+ if (Operation == AtomicRMWInst::Xchg &&
+ !Val->getType()->isIntegerTy() &&
+ !Val->getType()->isFloatingPointTy()) {
+ return Error(ValLoc, "atomicrmw " +
+ AtomicRMWInst::getOperationName(Operation) +
+ " operand must be an integer or floating point type");
}
unsigned Size = Val->getType()->getPrimitiveSizeInBits();
diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
index 0b93a61..87bd8f6 100644
--- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
+++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp
@@ -1034,8 +1034,6 @@
case bitc::RMW_MIN: return AtomicRMWInst::Min;
case bitc::RMW_UMAX: return AtomicRMWInst::UMax;
case bitc::RMW_UMIN: return AtomicRMWInst::UMin;
- case bitc::RMW_FADD: return AtomicRMWInst::FAdd;
- case bitc::RMW_FSUB: return AtomicRMWInst::FSub;
}
}
diff --git a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
index f4a539e..d345ae0 100644
--- a/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
+++ b/llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
@@ -559,8 +559,6 @@
case AtomicRMWInst::Min: return bitc::RMW_MIN;
case AtomicRMWInst::UMax: return bitc::RMW_UMAX;
case AtomicRMWInst::UMin: return bitc::RMW_UMIN;
- case AtomicRMWInst::FAdd: return bitc::RMW_FADD;
- case AtomicRMWInst::FSub: return bitc::RMW_FSUB;
}
}
diff --git a/llvm/lib/CodeGen/AtomicExpandPass.cpp b/llvm/lib/CodeGen/AtomicExpandPass.cpp
index 2d91594..bef9682 100644
--- a/llvm/lib/CodeGen/AtomicExpandPass.cpp
+++ b/llvm/lib/CodeGen/AtomicExpandPass.cpp
@@ -549,10 +549,6 @@
case AtomicRMWInst::UMin:
NewVal = Builder.CreateICmpULE(Loaded, Inc);
return Builder.CreateSelect(NewVal, Loaded, Inc, "new");
- case AtomicRMWInst::FAdd:
- return Builder.CreateFAdd(Loaded, Inc, "new");
- case AtomicRMWInst::FSub:
- return Builder.CreateFSub(Loaded, Inc, "new");
default:
llvm_unreachable("Unknown atomic op");
}
@@ -1551,8 +1547,6 @@
case AtomicRMWInst::Min:
case AtomicRMWInst::UMax:
case AtomicRMWInst::UMin:
- case AtomicRMWInst::FAdd:
- case AtomicRMWInst::FSub:
// No atomic libcalls are available for max/min/umax/umin.
return {};
}
diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp
index f48a970..8b67446 100644
--- a/llvm/lib/IR/Instructions.cpp
+++ b/llvm/lib/IR/Instructions.cpp
@@ -1407,10 +1407,6 @@
return "umax";
case AtomicRMWInst::UMin:
return "umin";
- case AtomicRMWInst::FAdd:
- return "fadd";
- case AtomicRMWInst::FSub:
- return "fsub";
case AtomicRMWInst::BAD_BINOP:
return "<invalid operation>";
}
diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp
index 1000e21..fb2388c 100644
--- a/llvm/lib/IR/Verifier.cpp
+++ b/llvm/lib/IR/Verifier.cpp
@@ -3435,11 +3435,6 @@
AtomicRMWInst::getOperationName(Op) +
" operand must have integer or floating point type!",
&RMWI, ElTy);
- } else if (AtomicRMWInst::isFPOperation(Op)) {
- Assert(ElTy->isFloatingPointTy(), "atomicrmw " +
- AtomicRMWInst::getOperationName(Op) +
- " operand must have floating point type!",
- &RMWI, ElTy);
} else {
Assert(ElTy->isIntegerTy(), "atomicrmw " +
AtomicRMWInst::getOperationName(Op) +
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index df77e8e..2530b0a 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -11600,9 +11600,6 @@
// For the real atomic operations, we have ldxr/stxr up to 128 bits,
TargetLowering::AtomicExpansionKind
AArch64TargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
- if (AI->isFloatingPointOperation())
- return AtomicExpansionKind::CmpXChg;
-
unsigned Size = AI->getType()->getPrimitiveSizeInBits();
if (Size > 128) return AtomicExpansionKind::None;
// Nand not supported in LSE.
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 469ceb9..5cf9a2f 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -14645,9 +14645,6 @@
// and up to 64 bits on the non-M profiles
TargetLowering::AtomicExpansionKind
ARMTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
- if (AI->isFloatingPointOperation())
- return AtomicExpansionKind::CmpXChg;
-
unsigned Size = AI->getType()->getPrimitiveSizeInBits();
bool hasAtomicRMW = !Subtarget->isThumb() || Subtarget->hasV8MBaselineOps();
return (Size <= (Subtarget->isMClass() ? 32U : 64U) && hasAtomicRMW)
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index b3781fe..329d7ae 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -3110,21 +3110,13 @@
AtomicOrdering Ord) const {
BasicBlock *BB = Builder.GetInsertBlock();
Module *M = BB->getParent()->getParent();
- auto PT = cast<PointerType>(Addr->getType());
- Type *Ty = PT->getElementType();
+ Type *Ty = cast<PointerType>(Addr->getType())->getElementType();
unsigned SZ = Ty->getPrimitiveSizeInBits();
assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic loads supported");
Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_L2_loadw_locked
: Intrinsic::hexagon_L4_loadd_locked;
-
- PointerType *NewPtrTy
- = Builder.getIntNTy(SZ)->getPointerTo(PT->getAddressSpace());
- Addr = Builder.CreateBitCast(Addr, NewPtrTy);
-
Value *Fn = Intrinsic::getDeclaration(M, IntID);
- Value *Call = Builder.CreateCall(Fn, Addr, "larx");
-
- return Builder.CreateBitCast(Call, Ty);
+ return Builder.CreateCall(Fn, Addr, "larx");
}
/// Perform a store-conditional operation to Addr. Return the status of the
@@ -3135,17 +3127,10 @@
Module *M = BB->getParent()->getParent();
Type *Ty = Val->getType();
unsigned SZ = Ty->getPrimitiveSizeInBits();
-
- Type *CastTy = Builder.getIntNTy(SZ);
assert((SZ == 32 || SZ == 64) && "Only 32/64-bit atomic stores supported");
Intrinsic::ID IntID = (SZ == 32) ? Intrinsic::hexagon_S2_storew_locked
: Intrinsic::hexagon_S4_stored_locked;
Value *Fn = Intrinsic::getDeclaration(M, IntID);
-
- unsigned AS = Addr->getType()->getPointerAddressSpace();
- Addr = Builder.CreateBitCast(Addr, CastTy->getPointerTo(AS));
- Val = Builder.CreateBitCast(Val, CastTy);
-
Value *Call = Builder.CreateCall(Fn, {Addr, Val}, "stcx");
Value *Cmp = Builder.CreateICmpEQ(Call, Builder.getInt32(0), "");
Value *Ext = Builder.CreateZExt(Cmp, Type::getInt32Ty(M->getContext()));
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b9e23df..8a32d95 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1720,12 +1720,6 @@
TargetLowering::AtomicExpansionKind
RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
- // atomicrmw {fadd,fsub} must be expanded to use compare-exchange, as
- // floating point operations can't be used in an lr/sc sequence without
- // brekaing the forward-progress guarantee.
- if (AI->isFloatingPointOperation())
- return AtomicExpansionKind::CmpXChg;
-
unsigned Size = AI->getType()->getPrimitiveSizeInBits();
if (Size == 8 || Size == 16)
return AtomicExpansionKind::MaskedIntrinsic;
diff --git a/llvm/test/Assembler/atomic.ll b/llvm/test/Assembler/atomic.ll
index 04ff262..a8b527f 100644
--- a/llvm/test/Assembler/atomic.ll
+++ b/llvm/test/Assembler/atomic.ll
@@ -39,13 +39,3 @@
fence syncscope("device") seq_cst
ret void
}
-
-define void @fp_atomics(float* %x) {
- ; CHECK: atomicrmw fadd float* %x, float 1.000000e+00 seq_cst
- atomicrmw fadd float* %x, float 1.0 seq_cst
-
- ; CHECK: atomicrmw volatile fadd float* %x, float 1.000000e+00 seq_cst
- atomicrmw volatile fadd float* %x, float 1.0 seq_cst
-
- ret void
-}
diff --git a/llvm/test/Assembler/invalid-atomicrmw-fadd-must-be-fp-type.ll b/llvm/test/Assembler/invalid-atomicrmw-fadd-must-be-fp-type.ll
deleted file mode 100644
index 3185d95..0000000
--- a/llvm/test/Assembler/invalid-atomicrmw-fadd-must-be-fp-type.ll
+++ /dev/null
@@ -1,7 +0,0 @@
-; RUN: not llvm-as -disable-output %s 2>&1 | FileCheck %s
-
-; CHECK: error: atomicrmw fadd operand must be a floating point type
-define void @f(i32* %ptr) {
- atomicrmw fadd i32* %ptr, i32 2 seq_cst
- ret void
-}
diff --git a/llvm/test/Assembler/invalid-atomicrmw-fsub-must-be-fp-type.ll b/llvm/test/Assembler/invalid-atomicrmw-fsub-must-be-fp-type.ll
deleted file mode 100644
index cd5bd4b..0000000
--- a/llvm/test/Assembler/invalid-atomicrmw-fsub-must-be-fp-type.ll
+++ /dev/null
@@ -1,7 +0,0 @@
-; RUN: not llvm-as -disable-output %s 2>&1 | FileCheck %s
-
-; CHECK: error: atomicrmw fsub operand must be a floating point type
-define void @f(i32* %ptr) {
- atomicrmw fsub i32* %ptr, i32 2 seq_cst
- ret void
-}
diff --git a/llvm/test/Bitcode/compatibility.ll b/llvm/test/Bitcode/compatibility.ll
index 3c5e86e..320ed83 100644
--- a/llvm/test/Bitcode/compatibility.ll
+++ b/llvm/test/Bitcode/compatibility.ll
@@ -764,13 +764,6 @@
define void @fp_atomics(float* %word) {
; CHECK: %atomicrmw.xchg = atomicrmw xchg float* %word, float 1.000000e+00 monotonic
%atomicrmw.xchg = atomicrmw xchg float* %word, float 1.0 monotonic
-
-; CHECK: %atomicrmw.fadd = atomicrmw fadd float* %word, float 1.000000e+00 monotonic
- %atomicrmw.fadd = atomicrmw fadd float* %word, float 1.0 monotonic
-
-; CHECK: %atomicrmw.fsub = atomicrmw fsub float* %word, float 1.000000e+00 monotonic
- %atomicrmw.fsub = atomicrmw fsub float* %word, float 1.0 monotonic
-
ret void
}
diff --git a/llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll
deleted file mode 100644
index d63f911..0000000
--- a/llvm/test/Transforms/AtomicExpand/AArch64/atomicrmw-fp.ll
+++ /dev/null
@@ -1,47 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -mtriple=aarch64-linux-gnu -atomic-expand %s | FileCheck %s
-
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fadd_f32(
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
-; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
-; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
-; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
-; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: ret float [[TMP6]]
-;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
- ret float %res
-}
-
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fsub_f32(
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
-; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
-; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
-; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
-; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: ret float [[TMP6]]
-;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
- ret float %res
-}
-
diff --git a/llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll
deleted file mode 100644
index 6f8ffc1..0000000
--- a/llvm/test/Transforms/AtomicExpand/ARM/atomicrmw-fp.ll
+++ /dev/null
@@ -1,51 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -mtriple=armv7-apple-ios7.0 -atomic-expand %s | FileCheck %s
-
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fadd_f32(
-; CHECK-NEXT: call void @llvm.arm.dmb(i32 11)
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
-; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
-; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
-; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
-; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: call void @llvm.arm.dmb(i32 11)
-; CHECK-NEXT: ret float [[TMP6]]
-;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
- ret float %res
-}
-
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fsub_f32(
-; CHECK-NEXT: call void @llvm.arm.dmb(i32 11)
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
-; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
-; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
-; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
-; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: call void @llvm.arm.dmb(i32 11)
-; CHECK-NEXT: ret float [[TMP6]]
-;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
- ret float %res
-}
-
diff --git a/llvm/test/Transforms/AtomicExpand/Hexagon/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/Hexagon/atomicrmw-fp.ll
deleted file mode 100644
index 3402690..0000000
--- a/llvm/test/Transforms/AtomicExpand/Hexagon/atomicrmw-fp.ll
+++ /dev/null
@@ -1,47 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -mtriple=hexagon-- -atomic-expand %s | FileCheck %s
-
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fadd_f32(
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[PTR:%.*]] to i32*
-; CHECK-NEXT: [[LARX:%.*]] = call i32 @llvm.hexagon.L2.loadw.locked(i32* [[TMP1]])
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[LARX]] to float
-; CHECK-NEXT: [[NEW:%.*]] = fadd float [[TMP2]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[STCX:%.*]] = call i32 @llvm.hexagon.S2.storew.locked(i32* [[TMP3]], i32 [[TMP4]])
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[STCX]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i32
-; CHECK-NEXT: [[TRYAGAIN:%.*]] = icmp ne i32 [[TMP6]], 0
-; CHECK-NEXT: br i1 [[TRYAGAIN]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: ret float [[TMP2]]
-;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
- ret float %res
-}
-
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fsub_f32(
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[TMP1:%.*]] = bitcast float* [[PTR:%.*]] to i32*
-; CHECK-NEXT: [[LARX:%.*]] = call i32 @llvm.hexagon.L2.loadw.locked(i32* [[TMP1]])
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[LARX]] to float
-; CHECK-NEXT: [[NEW:%.*]] = fsub float [[TMP2]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[STCX:%.*]] = call i32 @llvm.hexagon.S2.storew.locked(i32* [[TMP3]], i32 [[TMP4]])
-; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[STCX]], 0
-; CHECK-NEXT: [[TMP6:%.*]] = zext i1 [[TMP5]] to i32
-; CHECK-NEXT: [[TRYAGAIN:%.*]] = icmp ne i32 [[TMP6]], 0
-; CHECK-NEXT: br i1 [[TRYAGAIN]], label [[ATOMICRMW_START]], label [[ATOMICRMW_END:%.*]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: ret float [[TMP2]]
-;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
- ret float %res
-}
-
diff --git a/llvm/test/Transforms/AtomicExpand/Hexagon/lit.local.cfg b/llvm/test/Transforms/AtomicExpand/Hexagon/lit.local.cfg
deleted file mode 100644
index cc6a7ed..0000000
--- a/llvm/test/Transforms/AtomicExpand/Hexagon/lit.local.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-if not 'Hexagon' in config.root.targets:
- config.unsupported = True
diff --git a/llvm/test/Transforms/AtomicExpand/Mips/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/Mips/atomicrmw-fp.ll
deleted file mode 100644
index 7931b2b..0000000
--- a/llvm/test/Transforms/AtomicExpand/Mips/atomicrmw-fp.ll
+++ /dev/null
@@ -1,51 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -mtriple=mips64-mti-linux-gnu -atomic-expand %s | FileCheck %s
-
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fadd_f32(
-; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
-; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
-; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
-; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
-; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: ret float [[TMP6]]
-;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
- ret float %res
-}
-
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fsub_f32(
-; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] monotonic monotonic
-; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
-; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
-; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
-; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: fence seq_cst
-; CHECK-NEXT: ret float [[TMP6]]
-;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
- ret float %res
-}
-
diff --git a/llvm/test/Transforms/AtomicExpand/Mips/lit.local.cfg b/llvm/test/Transforms/AtomicExpand/Mips/lit.local.cfg
deleted file mode 100644
index 7d12f7a..0000000
--- a/llvm/test/Transforms/AtomicExpand/Mips/lit.local.cfg
+++ /dev/null
@@ -1,2 +0,0 @@
-if not 'Mips' in config.root.targets:
- config.unsupported = True
diff --git a/llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-fp.ll b/llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-fp.ll
deleted file mode 100644
index 0d2d8ca..0000000
--- a/llvm/test/Transforms/AtomicExpand/RISCV/atomicrmw-fp.ll
+++ /dev/null
@@ -1,47 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -mtriple=riscv32-- -atomic-expand %s | FileCheck %s
-
-define float @test_atomicrmw_fadd_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fadd_f32(
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
-; CHECK-NEXT: br label [[ATOMICRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[NEW:%.*]] = fadd float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
-; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
-; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
-; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
-; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: ret float [[TMP6]]
-;
- %res = atomicrmw fadd float* %ptr, float %value seq_cst
- ret float %res
-}
-
-define float @test_atomicrmw_fsub_f32(float* %ptr, float %value) {
-; CHECK-LABEL: @test_atomicrmw_fsub_f32(
-; CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[PTR:%.*]], align 4
-; CHECK-NEXT: br label [[ATOMIxbCRMW_START:%.*]]
-; CHECK: atomicrmw.start:
-; CHECK-NEXT: [[LOADED:%.*]] = phi float [ [[TMP1]], [[TMP0:%.*]] ], [ [[TMP6:%.*]], [[ATOMICRMW_START]] ]
-; CHECK-NEXT: [[NEW:%.*]] = fsub float [[LOADED]], [[VALUE:%.*]]
-; CHECK-NEXT: [[TMP2:%.*]] = bitcast float* [[PTR]] to i32*
-; CHECK-NEXT: [[TMP3:%.*]] = bitcast float [[NEW]] to i32
-; CHECK-NEXT: [[TMP4:%.*]] = bitcast float [[LOADED]] to i32
-; CHECK-NEXT: [[TMP5:%.*]] = cmpxchg i32* [[TMP2]], i32 [[TMP4]], i32 [[TMP3]] seq_cst seq_cst
-; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
-; CHECK-NEXT: [[NEWLOADED:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
-; CHECK-NEXT: [[TMP6]] = bitcast i32 [[NEWLOADED]] to float
-; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]]
-; CHECK: atomicrmw.end:
-; CHECK-NEXT: ret float [[TMP6]]
-;
- %res = atomicrmw fsub float* %ptr, float %value seq_cst
- ret float %res
-}
-
diff --git a/llvm/test/Transforms/AtomicExpand/RISCV/lit.local.cfg b/llvm/test/Transforms/AtomicExpand/RISCV/lit.local.cfg
deleted file mode 100644
index 7aaeda5..0000000
--- a/llvm/test/Transforms/AtomicExpand/RISCV/lit.local.cfg
+++ /dev/null
@@ -1,5 +0,0 @@
-config.suffixes = ['.ll']
-
-targets = set(config.root.targets_to_build.split())
-if not 'RISCV' in targets:
- config.unsupported = True