AMDGPU: Workaround for instruction size with literals
Instructions with a 32-bit base encoding with an optional
32-bit literal encoded after them report their size as 4
for the disassembler. Consider these when computing the
MachineInstr size. This fixes problems caused by size estimate
consistency in BranchRelaxation.
llvm-svn: 285743
diff --git a/llvm/lib/Target/AMDGPU/SIInstrFormats.td b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
index 8976333..9dfe06f 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrFormats.td
+++ b/llvm/lib/Target/AMDGPU/SIInstrFormats.td
@@ -65,6 +65,10 @@
// SMEM instructions like the cache flush ones.
field bits<1> ScalarStore = 0;
+ // Whether the operands can be ignored when computing the
+ // instruction size.
+ field bits<1> FixedSize = 0;
+
// These need to be kept in sync with the enum in SIInstrFlags.
let TSFlags{0} = VM_CNT;
let TSFlags{1} = EXP_CNT;
@@ -100,6 +104,7 @@
let TSFlags{27} = DisableWQM;
let TSFlags{28} = SOPKZext;
let TSFlags{29} = ScalarStore;
+ let TSFlags{30} = FixedSize;
let SchedRW = [Write32Bit];