[mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions
Differential Revision: https://reviews.llvm.org/D19906

llvm-svn: 276397
diff --git a/llvm/test/CodeGen/Mips/setge.ll b/llvm/test/CodeGen/Mips/setge.ll
index af69d7b..0809b6f 100644
--- a/llvm/test/CodeGen/Mips/setge.ll
+++ b/llvm/test/CodeGen/Mips/setge.ll
@@ -1,4 +1,5 @@
 ; RUN: llc  -march=mipsel -mattr=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
+; RUN: llc  -march=mips -mcpu=mips32r6 -mattr=micromips -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=MMR6
 
 @j = global i32 -5, align 4
 @k = global i32 10, align 4
@@ -16,9 +17,10 @@
   %cmp = icmp sge i32 %0, %1
   %conv = zext i1 %cmp to i32
   store i32 %conv, i32* @r1, align 4
-; 16:	slt	${{[0-9]+}}, ${{[0-9]+}}
-; 16:	move	$[[REGISTER:[0-9]+]], $24
-; 16:	xor	$[[REGISTER]], ${{[0-9]+}}
+; 16:   slt   ${{[0-9]+}}, ${{[0-9]+}}
+; MMR6: slt   ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
+; 16:   move  $[[REGISTER:[0-9]+]], $24
+; 16:   xor   $[[REGISTER]], ${{[0-9]+}}
   %2 = load i32, i32* @m, align 4
   %cmp1 = icmp sge i32 %0, %2
   %conv2 = zext i1 %cmp1 to i32