|  | //===-- Nios2Schedule.td - Nios2 Scheduling Definitions ----*- tablegen -*-===// | 
|  | // | 
|  | //                     The LLVM Compiler Infrastructure | 
|  | // | 
|  | // This file is distributed under the University of Illinois Open Source | 
|  | // License. See LICENSE.TXT for details. | 
|  | // | 
|  | //===----------------------------------------------------------------------===// | 
|  |  | 
|  | //===----------------------------------------------------------------------===// | 
|  | // Functional units across Nios2 chips sets. Based on GCC/Nios2 backend files. | 
|  | //===----------------------------------------------------------------------===// | 
|  | def ALU     : FuncUnit; | 
|  | def IMULDIV : FuncUnit; | 
|  |  | 
|  | //===----------------------------------------------------------------------===// | 
|  | // Instruction Itinerary classes used for Nios2 | 
|  | //===----------------------------------------------------------------------===// | 
|  | def IIAlu              : InstrItinClass; | 
|  | def IILoad             : InstrItinClass; | 
|  | def IIStore            : InstrItinClass; | 
|  | def IIFlush            : InstrItinClass; | 
|  | def IIIdiv             : InstrItinClass; | 
|  | def IIBranch           : InstrItinClass; | 
|  |  | 
|  | def IIPseudo           : InstrItinClass; | 
|  |  | 
|  | //===----------------------------------------------------------------------===// | 
|  | // Nios2 Generic instruction itineraries. | 
|  | //===----------------------------------------------------------------------===// | 
|  | //@ http://llvm.org/docs/doxygen/html/structllvm_1_1InstrStage.html | 
|  | def Nios2GenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ | 
|  | InstrItinData<IIAlu              , [InstrStage<1,  [ALU]>]>, | 
|  | InstrItinData<IILoad             , [InstrStage<3,  [ALU]>]>, | 
|  | InstrItinData<IIStore            , [InstrStage<1,  [ALU]>]>, | 
|  | InstrItinData<IIFlush            , [InstrStage<1,  [ALU]>]>, | 
|  | InstrItinData<IIIdiv             , [InstrStage<38, [IMULDIV]>]>, | 
|  | InstrItinData<IIBranch           , [InstrStage<1,  [ALU]>]> | 
|  | ]>; |