[X86] Add WriteFMOVMSK/WriteVecMOVMSK/WriteMMXMOVMSK scheduler classes
Currently MOVMSK instructions use the WriteVecLogic class, which is a very poor choice given that MOVMSK involves a SSE->GPR transfer.
Differential Revision: https://reviews.llvm.org/D44924
llvm-svn: 328664
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 71eb873..db7ae8a 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -227,6 +227,11 @@
let ResourceCycles = [4,3,1,1];
}
+// MOVMSK Instructions.
+def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; }
+def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; }
+def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; }
+
// AES instructions.
def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
let Latency = 7;
@@ -297,7 +302,6 @@
}
def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
"MMX_MOVD64grr",
- "MMX_PMOVMSKBrr",
"MMX_PSLLDri",
"MMX_PSLLDrr",
"MMX_PSLLQri",
@@ -839,15 +843,6 @@
"STOSQ",
"STOSW")>;
-def BWWriteResGroup26 : SchedWriteRes<[BWPort0]> {
- let Latency = 3;
- let NumMicroOps = 1;
- let ResourceCycles = [1];
-}
-def: InstRW<[BWWriteResGroup26], (instregex "(V?)MOVMSKPD(Y?)rr",
- "(V?)MOVMSKPS(Y?)rr",
- "(V?)PMOVMSKB(Y?)rr")>;
-
def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
let Latency = 3;
let NumMicroOps = 1;