Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / d4507266c8c8f1bd99f7d3fcb86989cda2e16066 / . / llvm / lib / Target / X86 / X86SchedBroadwell.td
blob: 71eb873c5acade0b38d2c3abe591b26bf966100c [file] [log] [blame]
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Broadwell to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14def BroadwellModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
16 // instructions per cycle.
17 let IssueWidth = 4;
18 let MicroOpBufferSize = 192; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 16;
21
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]24
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]25 // This flag is set to allow the scheduler to assign a default model to
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]26 // unrecognized opcodes.
27 let CompleteModel = 0;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]28}
29
30let SchedModel = BroadwellModel in {
31
32// Broadwell can issue micro-ops to 8 different ports in one cycle.
33
34// Ports 0, 1, 5, and 6 handle all computation.
35// Port 4 gets the data half of stores. Store data can be available later than
36// the store address, but since we don't model the latency of stores, we can
37// ignore that.
38// Ports 2 and 3 are identical. They handle loads and the address half of
39// stores. Port 7 can handle address calculations.
40def BWPort0 : ProcResource<1>;
41def BWPort1 : ProcResource<1>;
42def BWPort2 : ProcResource<1>;
43def BWPort3 : ProcResource<1>;
44def BWPort4 : ProcResource<1>;
45def BWPort5 : ProcResource<1>;
46def BWPort6 : ProcResource<1>;
47def BWPort7 : ProcResource<1>;
48
49// Many micro-ops are capable of issuing on multiple ports.
50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>;
51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>;
52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>;
54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>;
55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>;
56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>;
57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>;
58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>;
59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
62
63// 60 Entry Unified Scheduler
64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
65 BWPort5, BWPort6, BWPort7]> {
66 let BufferSize=60;
67}
68
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]69// Integer division issued on port 0.
70def BWDivider : ProcResource<1>; // Integer division issued on port 0.
71
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]72// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
73// cycles after the memory operand.
74def : ReadAdvance<ReadAfterLd, 5>;
75
76// Many SchedWrites are defined in pairs with and without a folded load.
77// Instructions with folded loads are usually micro-fused, so they only appear
78// as two micro-ops when queued in the reservation station.
79// This multiclass defines the resource usage for variants with and without
80// folded loads.
81multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]82 list<ProcResourceKind> ExePorts,
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]83 int Lat, list<int> Res = [1], int UOps = 1,
84 int LoadLat = 5> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]85 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]86 def : WriteRes<SchedRW, ExePorts> {
87 let Latency = Lat;
88 let ResourceCycles = Res;
89 let NumMicroOps = UOps;
90 }
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]91
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]92 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
93 // the latency (default = 5).
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]94 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]95 let Latency = !add(Lat, LoadLat);
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]96 let ResourceCycles = !listconcat([1], Res);
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame]97 let NumMicroOps = !add(UOps, 1);
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]98 }
99}
100
101// A folded store needs a cycle on port 4 for the store data, but it does not
102// need an extra port 2/3 cycle to recompute the address.
103def : WriteRes<WriteRMW, [BWPort4]>;
104
105// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]106defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
107defm : BWWriteResPair<WriteIMul, [BWPort1], 3>; // Integer multiplication.
108defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
Simon Pilgrim28e7bcb2018-03-26 21:06:14 +0000[diff] [blame]109defm : BWWriteResPair<WriteCRC32, [BWPort1], 3>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]110def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]111
112def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
113
Simon Pilgrimf33d9052018-03-26 18:19:28 +0000[diff] [blame]114// Bit counts.
115defm : BWWriteResPair<WriteBitScan, [BWPort1], 3>;
116defm : BWWriteResPair<WriteLZCNT, [BWPort1], 3>;
117defm : BWWriteResPair<WriteTZCNT, [BWPort1], 3>;
118defm : BWWriteResPair<WritePOPCNT, [BWPort1], 3>;
119
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]120// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]121defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]122
123// Loads, stores, and moves, not folded with other operations.
124def : WriteRes<WriteLoad, [BWPort23]> { let Latency = 5; }
125def : WriteRes<WriteStore, [BWPort237, BWPort4]>;
126def : WriteRes<WriteMove, [BWPort0156]>;
127
128// Idioms that clear a register, like xorps %xmm0, %xmm0.
129// These can often bypass execution ports completely.
130def : WriteRes<WriteZero, []>;
131
Sanjoy Das1074eb22017-12-12 19:11:31 +0000[diff] [blame]132// Treat misc copies as a move.
133def : InstRW<[WriteMove], (instrs COPY)>;
134
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]135// Branches don't produce values, so they have no latency, but they still
136// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]137defm : BWWriteResPair<WriteJump, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]138
139// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]140def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
141def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
142def : WriteRes<WriteFMove, [BWPort5]>;
143
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]144defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub/compare.
145defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.
146defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division.
147defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root.
148defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
149defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
150defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
151defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
152defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
153defm : BWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2]>; // Fp vector variable blends.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]154
155// FMA Scheduling helper class.
156// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
157
158// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]159def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; }
160def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
161def : WriteRes<WriteVecMove, [BWPort015]>;
162
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]163defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
164defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
165defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
166defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles.
167defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends.
168defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends.
169defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]170
171// Vector bitwise operations.
172// These are often used on both floating point and integer vectors.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]173defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]174
175// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]176defm : BWWriteResPair<WriteCvtF2I, [BWPort1], 3>; // Float -> Integer.
177defm : BWWriteResPair<WriteCvtI2F, [BWPort1], 4>; // Integer -> Float.
178defm : BWWriteResPair<WriteCvtF2F, [BWPort1], 3>; // Float -> Float size conversion.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]179
180// Strings instructions.
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]181
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]182// Packed Compare Implicit Length Strings, Return Mask
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]183def : WriteRes<WritePCmpIStrM, [BWPort0]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]184 let Latency = 11;
185 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]186 let ResourceCycles = [3];
187}
188def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]189 let Latency = 16;
190 let NumMicroOps = 4;
191 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]192}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]193
194// Packed Compare Explicit Length Strings, Return Mask
195def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
196 let Latency = 19;
197 let NumMicroOps = 9;
198 let ResourceCycles = [4,3,1,1];
199}
200def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
201 let Latency = 24;
202 let NumMicroOps = 10;
203 let ResourceCycles = [4,3,1,1,1];
204}
205
206// Packed Compare Implicit Length Strings, Return Index
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]207def : WriteRes<WritePCmpIStrI, [BWPort0]> {
208 let Latency = 11;
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]209 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]210 let ResourceCycles = [3];
211}
212def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]213 let Latency = 16;
214 let NumMicroOps = 4;
215 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]216}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]217
218// Packed Compare Explicit Length Strings, Return Index
219def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
220 let Latency = 18;
221 let NumMicroOps = 8;
222 let ResourceCycles = [4,3,1];
223}
224def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
225 let Latency = 23;
226 let NumMicroOps = 9;
227 let ResourceCycles = [4,3,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]228}
229
230// AES instructions.
231def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
232 let Latency = 7;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]233 let NumMicroOps = 1;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]234 let ResourceCycles = [1];
235}
236def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]237 let Latency = 12;
238 let NumMicroOps = 2;
239 let ResourceCycles = [1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]240}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]241
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]242def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
243 let Latency = 14;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]244 let NumMicroOps = 2;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]245 let ResourceCycles = [2];
246}
247def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]248 let Latency = 19;
249 let NumMicroOps = 3;
250 let ResourceCycles = [2,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]251}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]252
253def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
254 let Latency = 29;
255 let NumMicroOps = 11;
256 let ResourceCycles = [2,7,2];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]257}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]258def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
259 let Latency = 33;
260 let NumMicroOps = 11;
261 let ResourceCycles = [2,7,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]262}
263
264// Carry-less multiplication instructions.
Simon Pilgrim3b2ff1f2018-03-22 13:37:30 +0000[diff] [blame]265defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]266
267// Catch-all for expensive system instructions.
268def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
269
270// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]271defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles.
272defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles.
273defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]274
275// Old microcoded instructions that nobody use.
276def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
277
278// Fence instructions.
279def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
280
281// Nop, not very useful expect it provides a model for nops!
282def : WriteRes<WriteNop, []>;
283
284////////////////////////////////////////////////////////////////////////////////
285// Horizontal add/sub instructions.
286////////////////////////////////////////////////////////////////////////////////
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]287
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]288defm : BWWriteResPair<WriteFHAdd, [BWPort1], 3>;
289defm : BWWriteResPair<WritePHAdd, [BWPort15], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]290
291// Remaining instrs.
292
293def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
294 let Latency = 1;
295 let NumMicroOps = 1;
296 let ResourceCycles = [1];
297}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]298def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
299 "MMX_MOVD64grr",
300 "MMX_PMOVMSKBrr",
301 "MMX_PSLLDri",
302 "MMX_PSLLDrr",
303 "MMX_PSLLQri",
304 "MMX_PSLLQrr",
305 "MMX_PSLLWri",
306 "MMX_PSLLWrr",
307 "MMX_PSRADri",
308 "MMX_PSRADrr",
309 "MMX_PSRAWri",
310 "MMX_PSRAWrr",
311 "MMX_PSRLDri",
312 "MMX_PSRLDrr",
313 "MMX_PSRLQri",
314 "MMX_PSRLQrr",
315 "MMX_PSRLWri",
316 "MMX_PSRLWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]317 "(V?)MOVPDI2DIrr",
318 "(V?)MOVPQIto64rr",
319 "(V?)PSLLD(Y?)ri",
320 "(V?)PSLLQ(Y?)ri",
321 "VPSLLVQ(Y?)rr",
322 "(V?)PSLLW(Y?)ri",
323 "(V?)PSRAD(Y?)ri",
324 "(V?)PSRAW(Y?)ri",
325 "(V?)PSRLD(Y?)ri",
326 "(V?)PSRLQ(Y?)ri",
327 "VPSRLVQ(Y?)rr",
328 "(V?)PSRLW(Y?)ri",
329 "VTESTPD(Y?)rr",
330 "VTESTPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]331
332def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
333 let Latency = 1;
334 let NumMicroOps = 1;
335 let ResourceCycles = [1];
336}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]337def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r",
338 "COM_FST0r",
339 "UCOM_FPr",
340 "UCOM_Fr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]341
342def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
343 let Latency = 1;
344 let NumMicroOps = 1;
345 let ResourceCycles = [1];
346}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]347def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]348 "MMX_MOVD64to64rr",
349 "MMX_MOVQ2DQrr",
350 "MMX_PALIGNRrri",
351 "MMX_PSHUFBrr",
352 "MMX_PSHUFWri",
353 "MMX_PUNPCKHBWirr",
354 "MMX_PUNPCKHDQirr",
355 "MMX_PUNPCKHWDirr",
356 "MMX_PUNPCKLBWirr",
357 "MMX_PUNPCKLDQirr",
358 "MMX_PUNPCKLWDirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]359 "(V?)ANDNPD(Y?)rr",
360 "(V?)ANDNPS(Y?)rr",
361 "(V?)ANDPD(Y?)rr",
362 "(V?)ANDPS(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]363 "VBROADCASTSSrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]364 "(V?)INSERTPSrr",
365 "(V?)MOV64toPQIrr",
366 "(V?)MOVAPD(Y?)rr",
367 "(V?)MOVAPS(Y?)rr",
368 "(V?)MOVDDUP(Y?)rr",
369 "(V?)MOVDI2PDIrr",
370 "(V?)MOVHLPSrr",
371 "(V?)MOVLHPSrr",
372 "(V?)MOVSDrr",
373 "(V?)MOVSHDUP(Y?)rr",
374 "(V?)MOVSLDUP(Y?)rr",
375 "(V?)MOVSSrr",
376 "(V?)MOVUPD(Y?)rr",
377 "(V?)MOVUPS(Y?)rr",
378 "(V?)ORPD(Y?)rr",
379 "(V?)ORPS(Y?)rr",
380 "(V?)PACKSSDW(Y?)rr",
381 "(V?)PACKSSWB(Y?)rr",
382 "(V?)PACKUSDW(Y?)rr",
383 "(V?)PACKUSWB(Y?)rr",
384 "(V?)PALIGNR(Y?)rri",
385 "(V?)PBLENDW(Y?)rri",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]386 "VPBROADCASTDrr",
387 "VPBROADCASTQrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]388 "VPERMILPD(Y?)ri",
389 "VPERMILPD(Y?)rr",
390 "VPERMILPS(Y?)ri",
391 "VPERMILPS(Y?)rr",
392 "(V?)PMOVSXBDrr",
393 "(V?)PMOVSXBQrr",
394 "(V?)PMOVSXBWrr",
395 "(V?)PMOVSXDQrr",
396 "(V?)PMOVSXWDrr",
397 "(V?)PMOVSXWQrr",
398 "(V?)PMOVZXBDrr",
399 "(V?)PMOVZXBQrr",
400 "(V?)PMOVZXBWrr",
401 "(V?)PMOVZXDQrr",
402 "(V?)PMOVZXWDrr",
403 "(V?)PMOVZXWQrr",
404 "(V?)PSHUFB(Y?)rr",
405 "(V?)PSHUFD(Y?)ri",
406 "(V?)PSHUFHW(Y?)ri",
407 "(V?)PSHUFLW(Y?)ri",
408 "(V?)PSLLDQ(Y?)ri",
409 "(V?)PSRLDQ(Y?)ri",
410 "(V?)PUNPCKHBW(Y?)rr",
411 "(V?)PUNPCKHDQ(Y?)rr",
412 "(V?)PUNPCKHQDQ(Y?)rr",
413 "(V?)PUNPCKHWD(Y?)rr",
414 "(V?)PUNPCKLBW(Y?)rr",
415 "(V?)PUNPCKLDQ(Y?)rr",
416 "(V?)PUNPCKLQDQ(Y?)rr",
417 "(V?)PUNPCKLWD(Y?)rr",
418 "(V?)SHUFPD(Y?)rri",
419 "(V?)SHUFPS(Y?)rri",
420 "(V?)UNPCKHPD(Y?)rr",
421 "(V?)UNPCKHPS(Y?)rr",
422 "(V?)UNPCKLPD(Y?)rr",
423 "(V?)UNPCKLPS(Y?)rr",
424 "(V?)XORPD(Y?)rr",
425 "(V?)XORPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]426
427def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
428 let Latency = 1;
429 let NumMicroOps = 1;
430 let ResourceCycles = [1];
431}
432def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
433
434def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
435 let Latency = 1;
436 let NumMicroOps = 1;
437 let ResourceCycles = [1];
438}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]439def: InstRW<[BWWriteResGroup5], (instregex "FINCSTP",
440 "FNOP")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]441
442def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
443 let Latency = 1;
444 let NumMicroOps = 1;
445 let ResourceCycles = [1];
446}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]447def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
448 "ADC(16|32|64)i",
449 "ADC(8|16|32|64)rr",
450 "ADCX(32|64)rr",
451 "ADOX(32|64)rr",
452 "BT(16|32|64)ri8",
453 "BT(16|32|64)rr",
454 "BTC(16|32|64)ri8",
455 "BTC(16|32|64)rr",
456 "BTR(16|32|64)ri8",
457 "BTR(16|32|64)rr",
458 "BTS(16|32|64)ri8",
459 "BTS(16|32|64)rr",
460 "CDQ",
461 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
462 "CQO",
463 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
464 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
465 "JMP_1",
466 "JMP_4",
467 "RORX(32|64)ri",
468 "SAR(8|16|32|64)r1",
469 "SAR(8|16|32|64)ri",
470 "SARX(32|64)rr",
471 "SBB(16|32|64)ri",
472 "SBB(16|32|64)i",
473 "SBB(8|16|32|64)rr",
474 "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
475 "SHL(8|16|32|64)r1",
476 "SHL(8|16|32|64)ri",
477 "SHLX(32|64)rr",
478 "SHR(8|16|32|64)r1",
479 "SHR(8|16|32|64)ri",
480 "SHRX(32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]481
482def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
483 let Latency = 1;
484 let NumMicroOps = 1;
485 let ResourceCycles = [1];
486}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]487def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
488 "BLSI(32|64)rr",
489 "BLSMSK(32|64)rr",
490 "BLSR(32|64)rr",
491 "BZHI(32|64)rr",
492 "LEA(16|32|64)(_32)?r",
493 "MMX_PABSBrr",
494 "MMX_PABSDrr",
495 "MMX_PABSWrr",
496 "MMX_PADDBirr",
497 "MMX_PADDDirr",
498 "MMX_PADDQirr",
499 "MMX_PADDSBirr",
500 "MMX_PADDSWirr",
501 "MMX_PADDUSBirr",
502 "MMX_PADDUSWirr",
503 "MMX_PADDWirr",
504 "MMX_PAVGBirr",
505 "MMX_PAVGWirr",
506 "MMX_PCMPEQBirr",
507 "MMX_PCMPEQDirr",
508 "MMX_PCMPEQWirr",
509 "MMX_PCMPGTBirr",
510 "MMX_PCMPGTDirr",
511 "MMX_PCMPGTWirr",
512 "MMX_PMAXSWirr",
513 "MMX_PMAXUBirr",
514 "MMX_PMINSWirr",
515 "MMX_PMINUBirr",
516 "MMX_PSIGNBrr",
517 "MMX_PSIGNDrr",
518 "MMX_PSIGNWrr",
519 "MMX_PSUBBirr",
520 "MMX_PSUBDirr",
521 "MMX_PSUBQirr",
522 "MMX_PSUBSBirr",
523 "MMX_PSUBSWirr",
524 "MMX_PSUBUSBirr",
525 "MMX_PSUBUSWirr",
526 "MMX_PSUBWirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]527 "(V?)PABSB(Y?)rr",
528 "(V?)PABSD(Y?)rr",
529 "(V?)PABSW(Y?)rr",
530 "(V?)PADDB(Y?)rr",
531 "(V?)PADDD(Y?)rr",
532 "(V?)PADDQ(Y?)rr",
533 "(V?)PADDSB(Y?)rr",
534 "(V?)PADDSW(Y?)rr",
535 "(V?)PADDUSB(Y?)rr",
536 "(V?)PADDUSW(Y?)rr",
537 "(V?)PADDW(Y?)rr",
538 "(V?)PAVGB(Y?)rr",
539 "(V?)PAVGW(Y?)rr",
540 "(V?)PCMPEQB(Y?)rr",
541 "(V?)PCMPEQD(Y?)rr",
542 "(V?)PCMPEQQ(Y?)rr",
543 "(V?)PCMPEQW(Y?)rr",
544 "(V?)PCMPGTB(Y?)rr",
545 "(V?)PCMPGTD(Y?)rr",
546 "(V?)PCMPGTW(Y?)rr",
547 "(V?)PMAXSB(Y?)rr",
548 "(V?)PMAXSD(Y?)rr",
549 "(V?)PMAXSW(Y?)rr",
550 "(V?)PMAXUB(Y?)rr",
551 "(V?)PMAXUD(Y?)rr",
552 "(V?)PMAXUW(Y?)rr",
553 "(V?)PMINSB(Y?)rr",
554 "(V?)PMINSD(Y?)rr",
555 "(V?)PMINSW(Y?)rr",
556 "(V?)PMINUB(Y?)rr",
557 "(V?)PMINUD(Y?)rr",
558 "(V?)PMINUW(Y?)rr",
559 "(V?)PSIGNB(Y?)rr",
560 "(V?)PSIGND(Y?)rr",
561 "(V?)PSIGNW(Y?)rr",
562 "(V?)PSUBB(Y?)rr",
563 "(V?)PSUBD(Y?)rr",
564 "(V?)PSUBQ(Y?)rr",
565 "(V?)PSUBSB(Y?)rr",
566 "(V?)PSUBSW(Y?)rr",
567 "(V?)PSUBUSB(Y?)rr",
568 "(V?)PSUBUSW(Y?)rr",
569 "(V?)PSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]570
571def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
572 let Latency = 1;
573 let NumMicroOps = 1;
574 let ResourceCycles = [1];
575}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]576def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]577 "MMX_PANDNirr",
578 "MMX_PANDirr",
579 "MMX_PORirr",
580 "MMX_PXORirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]581 "(V?)BLENDPD(Y?)rri",
582 "(V?)BLENDPS(Y?)rri",
583 "(V?)MOVDQA(Y?)rr",
584 "(V?)MOVDQU(Y?)rr",
585 "(V?)MOVPQI2QIrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]586 "VMOVZPQILo2PQIrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]587 "(V?)PANDN(Y?)rr",
588 "(V?)PAND(Y?)rr",
589 "VPBLENDD(Y?)rri",
590 "(V?)POR(Y?)rr",
591 "(V?)PXOR(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]592
593def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
594 let Latency = 1;
595 let NumMicroOps = 1;
596 let ResourceCycles = [1];
597}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]598def: InstRW<[BWWriteResGroup9], (instrs CWDE)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]599def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
600 "ADD(8|16|32|64)rr",
601 "ADD(8|16|32|64)i",
602 "AND(8|16|32|64)ri",
603 "AND(8|16|32|64)rr",
604 "AND(8|16|32|64)i",
605 "CBW",
606 "CLC",
607 "CMC",
608 "CMP(8|16|32|64)ri",
609 "CMP(8|16|32|64)rr",
610 "CMP(8|16|32|64)i",
611 "DEC(8|16|32|64)r",
612 "INC(8|16|32|64)r",
613 "LAHF",
614 "MOV(8|16|32|64)rr",
615 "MOV(8|16|32|64)ri",
616 "MOVSX(16|32|64)rr16",
617 "MOVSX(16|32|64)rr32",
618 "MOVSX(16|32|64)rr8",
619 "MOVZX(16|32|64)rr16",
620 "MOVZX(16|32|64)rr8",
621 "NEG(8|16|32|64)r",
622 "NOOP",
623 "NOT(8|16|32|64)r",
624 "OR(8|16|32|64)ri",
625 "OR(8|16|32|64)rr",
626 "OR(8|16|32|64)i",
627 "SAHF",
628 "SGDT64m",
629 "SIDT64m",
630 "SLDT64m",
631 "SMSW16m",
632 "STC",
633 "STRm",
634 "SUB(8|16|32|64)ri",
635 "SUB(8|16|32|64)rr",
636 "SUB(8|16|32|64)i",
637 "SYSCALL",
638 "TEST(8|16|32|64)rr",
639 "TEST(8|16|32|64)i",
640 "TEST(8|16|32|64)ri",
641 "XCHG(16|32|64)rr",
642 "XOR(8|16|32|64)ri",
643 "XOR(8|16|32|64)rr",
644 "XOR(8|16|32|64)i")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]645
646def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
647 let Latency = 1;
648 let NumMicroOps = 2;
649 let ResourceCycles = [1,1];
650}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]651def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
652 "MMX_MOVD64from64rm",
653 "MMX_MOVD64mr",
654 "MMX_MOVNTQmr",
655 "MMX_MOVQ64mr",
656 "MOV(16|32|64)mr",
657 "MOV8mi",
658 "MOV8mr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]659 "MOVNTI_64mr",
660 "MOVNTImr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]661 "ST_FP32m",
662 "ST_FP64m",
663 "ST_FP80m",
664 "VEXTRACTF128mr",
665 "VEXTRACTI128mr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]666 "(V?)MOVAPD(Y?)mr",
667 "(V?)MOVAPS(Y?)mr",
668 "(V?)MOVDQA(Y?)mr",
669 "(V?)MOVDQU(Y?)mr",
670 "(V?)MOVHPDmr",
671 "(V?)MOVHPSmr",
672 "(V?)MOVLPDmr",
673 "(V?)MOVLPSmr",
674 "(V?)MOVNTDQ(V?)mr",
675 "(V?)MOVNTPD(V?)mr",
676 "(V?)MOVNTPS(V?)mr",
677 "(V?)MOVPDI2DImr",
678 "(V?)MOVPQI2QImr",
679 "(V?)MOVPQIto64mr",
680 "(V?)MOVSDmr",
681 "(V?)MOVSSmr",
682 "(V?)MOVUPD(Y?)mr",
683 "(V?)MOVUPS(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]684
685def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> {
686 let Latency = 2;
687 let NumMicroOps = 2;
688 let ResourceCycles = [2];
689}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]690def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0",
691 "BLENDVPSrr0",
692 "MMX_PINSRWrr",
693 "PBLENDVBrr0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]694 "VBLENDVPD(Y?)rr",
695 "VBLENDVPS(Y?)rr",
696 "VPBLENDVB(Y?)rr",
697 "(V?)PINSRBrr",
698 "(V?)PINSRDrr",
699 "(V?)PINSRQrr",
700 "(V?)PINSRWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]701
702def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
703 let Latency = 2;
704 let NumMicroOps = 2;
705 let ResourceCycles = [2];
706}
707def: InstRW<[BWWriteResGroup12], (instregex "FDECSTP")>;
708
709def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
710 let Latency = 2;
711 let NumMicroOps = 2;
712 let ResourceCycles = [2];
713}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]714def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
715 "ROL(8|16|32|64)ri",
716 "ROR(8|16|32|64)r1",
717 "ROR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]718
719def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
720 let Latency = 2;
721 let NumMicroOps = 2;
722 let ResourceCycles = [2];
723}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]724def: InstRW<[BWWriteResGroup14], (instregex "LFENCE",
725 "MFENCE",
726 "WAIT",
727 "XGETBV")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]728
729def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
730 let Latency = 2;
731 let NumMicroOps = 2;
732 let ResourceCycles = [1,1];
733}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]734def: InstRW<[BWWriteResGroup15], (instregex "MMX_PEXTRWrr",
735 "VCVTPH2PS(Y?)rr",
736 "(V?)CVTPS2PDrr",
737 "(V?)CVTSS2SDrr",
738 "(V?)EXTRACTPSrr",
739 "(V?)PEXTRBrr",
740 "(V?)PEXTRDrr",
741 "(V?)PEXTRQrr",
742 "(V?)PEXTRWrr",
743 "(V?)PSLLDrr",
744 "(V?)PSLLQrr",
745 "(V?)PSLLWrr",
746 "(V?)PSRADrr",
747 "(V?)PSRAWrr",
748 "(V?)PSRLDrr",
749 "(V?)PSRLQrr",
750 "(V?)PSRLWrr",
751 "(V?)PTESTrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]752
753def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
754 let Latency = 2;
755 let NumMicroOps = 2;
756 let ResourceCycles = [1,1];
757}
758def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
759
760def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
761 let Latency = 2;
762 let NumMicroOps = 2;
763 let ResourceCycles = [1,1];
764}
765def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;
766
767def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
768 let Latency = 2;
769 let NumMicroOps = 2;
770 let ResourceCycles = [1,1];
771}
772def: InstRW<[BWWriteResGroup18], (instregex "SFENCE")>;
773
774def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {
775 let Latency = 2;
776 let NumMicroOps = 2;
777 let ResourceCycles = [1,1];
778}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]779def: InstRW<[BWWriteResGroup19], (instregex "BEXTR(32|64)rr",
780 "BSWAP(16|32|64)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]781
782def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
783 let Latency = 2;
784 let NumMicroOps = 2;
785 let ResourceCycles = [1,1];
786}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]787def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000[diff] [blame]788def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]789def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8",
790 "ADC8ri",
791 "CMOV(A|BE)(16|32|64)rr",
792 "SBB8i8",
793 "SBB8ri",
794 "SET(A|BE)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]795
796def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> {
797 let Latency = 2;
798 let NumMicroOps = 3;
799 let ResourceCycles = [1,1,1];
800}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]801def: InstRW<[BWWriteResGroup21], (instregex "(V?)EXTRACTPSmr",
802 "(V?)PEXTRBmr",
803 "(V?)PEXTRDmr",
804 "(V?)PEXTRQmr",
805 "(V?)PEXTRWmr",
806 "(V?)STMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]807
808def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
809 let Latency = 2;
810 let NumMicroOps = 3;
811 let ResourceCycles = [1,1,1];
812}
813def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;
814
815def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {
816 let Latency = 2;
817 let NumMicroOps = 3;
818 let ResourceCycles = [1,1,1];
819}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]820def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]821
822def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
823 let Latency = 2;
824 let NumMicroOps = 3;
825 let ResourceCycles = [1,1,1];
826}
827def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
828
829def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
830 let Latency = 2;
831 let NumMicroOps = 3;
832 let ResourceCycles = [1,1,1];
833}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]834def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]835def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
836 "PUSH64i8",
837 "STOSB",
838 "STOSL",
839 "STOSQ",
840 "STOSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]841
842def BWWriteResGroup26 : SchedWriteRes<[BWPort0]> {
843 let Latency = 3;
844 let NumMicroOps = 1;
845 let ResourceCycles = [1];
846}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]847def: InstRW<[BWWriteResGroup26], (instregex "(V?)MOVMSKPD(Y?)rr",
848 "(V?)MOVMSKPS(Y?)rr",
849 "(V?)PMOVMSKB(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]850
851def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
852 let Latency = 3;
853 let NumMicroOps = 1;
854 let ResourceCycles = [1];
855}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]856def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]857def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]858def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]859 "ADD_FST0r",
860 "ADD_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]861 "MMX_CVTPI2PSirr",
862 "PDEP(32|64)rr",
863 "PEXT(32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]864 "SHLD(16|32|64)rri8",
865 "SHRD(16|32|64)rri8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]866 "SUBR_FPrST0",
867 "SUBR_FST0r",
868 "SUBR_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]869 "SUB_FPrST0",
870 "SUB_FST0r",
871 "SUB_FrST0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]872 "(V?)ADDPD(Y?)rr",
873 "(V?)ADDPS(Y?)rr",
874 "(V?)ADDSDrr",
875 "(V?)ADDSSrr",
876 "(V?)ADDSUBPD(Y?)rr",
877 "(V?)ADDSUBPS(Y?)rr",
878 "(V?)CMPPD(Y?)rri",
879 "(V?)CMPPS(Y?)rri",
880 "(V?)CMPSDrr",
881 "(V?)CMPSSrr",
882 "(V?)COMISDrr",
883 "(V?)COMISSrr",
884 "(V?)CVTDQ2PS(Y?)rr",
885 "(V?)CVTPS2DQ(Y?)rr",
886 "(V?)CVTTPS2DQ(Y?)rr",
887 "(V?)MAX(C?)PD(Y?)rr",
888 "(V?)MAX(C?)PS(Y?)rr",
889 "(V?)MAX(C?)SDrr",
890 "(V?)MAX(C?)SSrr",
891 "(V?)MIN(C?)PD(Y?)rr",
892 "(V?)MIN(C?)PS(Y?)rr",
893 "(V?)MIN(C?)SDrr",
894 "(V?)MIN(C?)SSrr",
895 "(V?)SUBPD(Y?)rr",
896 "(V?)SUBPS(Y?)rr",
897 "(V?)SUBSDrr",
898 "(V?)SUBSSrr",
899 "(V?)UCOMISDrr",
900 "(V?)UCOMISSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]901
902def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
903 let Latency = 3;
904 let NumMicroOps = 2;
905 let ResourceCycles = [1,1];
906}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]907def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]908
909def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
910 let Latency = 3;
911 let NumMicroOps = 1;
912 let ResourceCycles = [1];
913}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]914def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr",
915 "VBROADCASTSSYrr",
916 "VEXTRACTF128rr",
917 "VEXTRACTI128rr",
918 "VINSERTF128rr",
919 "VINSERTI128rr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]920 "VPBROADCASTB(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]921 "VPBROADCASTDYrr",
922 "VPBROADCASTQYrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]923 "VPBROADCASTW(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]924 "VPERM2F128rr",
925 "VPERM2I128rr",
926 "VPERMDYrr",
927 "VPERMPDYri",
928 "VPERMPSYrr",
929 "VPERMQYri",
930 "VPMOVSXBDYrr",
931 "VPMOVSXBQYrr",
932 "VPMOVSXBWYrr",
933 "VPMOVSXDQYrr",
934 "VPMOVSXWDYrr",
935 "VPMOVSXWQYrr",
936 "VPMOVZXBDYrr",
937 "VPMOVZXBQYrr",
938 "VPMOVZXBWYrr",
939 "VPMOVZXDQYrr",
940 "VPMOVZXWDYrr",
941 "VPMOVZXWQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]942
943def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {
944 let Latency = 3;
945 let NumMicroOps = 1;
946 let ResourceCycles = [1];
947}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]948def: InstRW<[BWWriteResGroup29], (instregex "(V?)MULPD(Y?)rr",
949 "(V?)MULPS(Y?)rr",
950 "(V?)MULSDrr",
951 "(V?)MULSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]952
953def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
954 let Latency = 3;
955 let NumMicroOps = 3;
956 let ResourceCycles = [3];
957}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]958def: InstRW<[BWWriteResGroup30], (instregex "XADD(8|16|32|64)rr",
959 "XCHG8rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]960
961def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
962 let Latency = 3;
963 let NumMicroOps = 3;
964 let ResourceCycles = [2,1];
965}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]966def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVD(Y?)rr",
967 "VPSRAVD(Y?)rr",
968 "VPSRLVD(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]969
970def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
971 let Latency = 3;
972 let NumMicroOps = 3;
973 let ResourceCycles = [2,1];
974}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]975def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr",
976 "MMX_PHADDSWrr",
977 "MMX_PHADDWrr",
978 "MMX_PHSUBDrr",
979 "MMX_PHSUBSWrr",
980 "MMX_PHSUBWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]981 "(V?)PHADDD(Y?)rr",
982 "(V?)PHADDSW(Y?)rr",
983 "(V?)PHADDW(Y?)rr",
984 "(V?)PHSUBD(Y?)rr",
985 "(V?)PHSUBSW(Y?)rr",
986 "(V?)PHSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]987
988def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
989 let Latency = 3;
990 let NumMicroOps = 3;
991 let ResourceCycles = [2,1];
992}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]993def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr",
994 "MMX_PACKSSWBirr",
995 "MMX_PACKUSWBirr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]996
997def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
998 let Latency = 3;
999 let NumMicroOps = 3;
1000 let ResourceCycles = [1,2];
1001}
1002def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
1003
1004def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
1005 let Latency = 3;
1006 let NumMicroOps = 3;
1007 let ResourceCycles = [1,2];
1008}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1009def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
1010 "RCL(8|16|32|64)ri",
1011 "RCR(8|16|32|64)r1",
1012 "RCR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1013
1014def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
1015 let Latency = 3;
1016 let NumMicroOps = 3;
1017 let ResourceCycles = [2,1];
1018}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1019def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL",
1020 "ROR(8|16|32|64)rCL",
1021 "SAR(8|16|32|64)rCL",
1022 "SHL(8|16|32|64)rCL",
1023 "SHR(8|16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1024
1025def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
1026 let Latency = 3;
1027 let NumMicroOps = 4;
1028 let ResourceCycles = [1,1,1,1];
1029}
1030def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
1031
1032def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1033 let Latency = 3;
1034 let NumMicroOps = 4;
1035 let ResourceCycles = [1,1,1,1];
1036}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1037def: InstRW<[BWWriteResGroup38], (instregex "CALL64pcrel32",
1038 "SET(A|BE)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1039
1040def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
1041 let Latency = 4;
1042 let NumMicroOps = 2;
1043 let ResourceCycles = [1,1];
1044}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1045def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVTSD2SI64rr",
1046 "(V?)CVTSD2SIrr",
1047 "(V?)CVTSS2SI64rr",
1048 "(V?)CVTSS2SIrr",
1049 "(V?)CVTTSD2SI64rr",
1050 "(V?)CVTTSD2SIrr",
1051 "(V?)CVTTSS2SI64rr",
1052 "(V?)CVTTSS2SIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1053
1054def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
1055 let Latency = 4;
1056 let NumMicroOps = 2;
1057 let ResourceCycles = [1,1];
1058}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1059def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr",
1060 "VPSLLDYrr",
1061 "VPSLLQYrr",
1062 "VPSLLWYrr",
1063 "VPSRADYrr",
1064 "VPSRAWYrr",
1065 "VPSRLDYrr",
1066 "VPSRLQYrr",
1067 "VPSRLWYrr",
1068 "VPTESTYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1069
1070def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
1071 let Latency = 4;
1072 let NumMicroOps = 2;
1073 let ResourceCycles = [1,1];
1074}
1075def: InstRW<[BWWriteResGroup41], (instregex "FNSTSW16r")>;
1076
1077def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
1078 let Latency = 4;
1079 let NumMicroOps = 2;
1080 let ResourceCycles = [1,1];
1081}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1082def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1083def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1084 "MMX_CVTPI2PDirr",
1085 "MMX_CVTPS2PIirr",
1086 "MMX_CVTTPD2PIirr",
1087 "MMX_CVTTPS2PIirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1088 "(V?)CVTDQ2PDrr",
1089 "(V?)CVTPD2DQrr",
1090 "(V?)CVTPD2PSrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1091 "VCVTPS2PHrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1092 "(V?)CVTSD2SSrr",
1093 "(V?)CVTSI642SDrr",
1094 "(V?)CVTSI2SDrr",
1095 "(V?)CVTSI2SSrr",
1096 "(V?)CVTTPD2DQrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1097
1098def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1099 let Latency = 4;
1100 let NumMicroOps = 4;
1101}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1102def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1103
1104def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
1105 let Latency = 4;
1106 let NumMicroOps = 3;
1107 let ResourceCycles = [1,1,1];
1108}
1109def: InstRW<[BWWriteResGroup43], (instregex "FNSTSWm")>;
1110
1111def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
1112 let Latency = 4;
1113 let NumMicroOps = 3;
1114 let ResourceCycles = [1,1,1];
1115}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1116def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m",
1117 "ISTT_FP32m",
1118 "ISTT_FP64m",
1119 "IST_F16m",
1120 "IST_F32m",
1121 "IST_FP16m",
1122 "IST_FP32m",
1123 "IST_FP64m",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1124 "VCVTPS2PH(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1125
1126def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
1127 let Latency = 4;
1128 let NumMicroOps = 4;
1129 let ResourceCycles = [4];
1130}
1131def: InstRW<[BWWriteResGroup45], (instregex "FNCLEX")>;
1132
1133def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
1134 let Latency = 4;
1135 let NumMicroOps = 4;
1136 let ResourceCycles = [1,3];
1137}
1138def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>;
1139
1140def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
1141 let Latency = 5;
1142 let NumMicroOps = 1;
1143 let ResourceCycles = [1];
1144}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1145def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
1146 "MMX_PMADDWDirr",
1147 "MMX_PMULHRSWrr",
1148 "MMX_PMULHUWirr",
1149 "MMX_PMULHWirr",
1150 "MMX_PMULLWirr",
1151 "MMX_PMULUDQirr",
1152 "MMX_PSADBWirr",
1153 "MUL_FPrST0",
1154 "MUL_FST0r",
1155 "MUL_FrST0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1156 "(V?)PCMPGTQ(Y?)rr",
1157 "(V?)PHMINPOSUWrr",
1158 "(V?)PMADDUBSW(Y?)rr",
1159 "(V?)PMADDWD(Y?)rr",
1160 "(V?)PMULDQ(Y?)rr",
1161 "(V?)PMULHRSW(Y?)rr",
1162 "(V?)PMULHUW(Y?)rr",
1163 "(V?)PMULHW(Y?)rr",
1164 "(V?)PMULLW(Y?)rr",
1165 "(V?)PMULUDQ(Y?)rr",
1166 "(V?)PSADBW(Y?)rr",
1167 "(V?)RCPPSr",
1168 "(V?)RCPSSr",
1169 "(V?)RSQRTPSr",
1170 "(V?)RSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1171
1172def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> {
1173 let Latency = 5;
1174 let NumMicroOps = 1;
1175 let ResourceCycles = [1];
1176}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]1177def: InstRW<[BWWriteResGroup48],
1178 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
1179 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1180
1181def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
1182 let Latency = 5;
1183 let NumMicroOps = 1;
1184 let ResourceCycles = [1];
1185}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1186def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1187 "MMX_MOVD64to64rm",
1188 "MMX_MOVQ64rm",
1189 "MOV(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1190 "MOVSX(16|32|64)rm16",
1191 "MOVSX(16|32|64)rm32",
1192 "MOVSX(16|32|64)rm8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1193 "MOVZX(16|32|64)rm16",
1194 "MOVZX(16|32|64)rm8",
1195 "PREFETCHNTA",
1196 "PREFETCHT0",
1197 "PREFETCHT1",
1198 "PREFETCHT2",
1199 "VBROADCASTSSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1200 "(V?)LDDQUrm",
1201 "(V?)MOV64toPQIrm",
1202 "(V?)MOVAPDrm",
1203 "(V?)MOVAPSrm",
1204 "(V?)MOVDDUPrm",
1205 "(V?)MOVDI2PDIrm",
1206 "(V?)MOVDQArm",
1207 "(V?)MOVDQUrm",
1208 "(V?)MOVNTDQArm",
1209 "(V?)MOVQI2PQIrm",
1210 "(V?)MOVSDrm",
1211 "(V?)MOVSHDUPrm",
1212 "(V?)MOVSLDUPrm",
1213 "(V?)MOVSSrm",
1214 "(V?)MOVUPDrm",
1215 "(V?)MOVUPSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1216 "VPBROADCASTDrm",
1217 "VPBROADCASTQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1218
1219def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
1220 let Latency = 5;
1221 let NumMicroOps = 3;
1222 let ResourceCycles = [1,2];
1223}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1224def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr",
1225 "(V?)HADDPD(Y?)rr",
1226 "(V?)HADDPS(Y?)rr",
1227 "(V?)HSUBPD(Y?)rr",
1228 "(V?)HSUBPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1229
1230def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
1231 let Latency = 5;
1232 let NumMicroOps = 3;
1233 let ResourceCycles = [1,1,1];
1234}
1235def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
1236
1237def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1238 let Latency = 4;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1239 let NumMicroOps = 3;
1240 let ResourceCycles = [1,1,1];
1241}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1242def: InstRW<[BWWriteResGroup52], (instrs IMUL32r, MUL32r, MULX32rr)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1243
1244def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> {
1245 let Latency = 5;
1246 let NumMicroOps = 4;
1247 let ResourceCycles = [1,1,1,1];
1248}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1249def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPD(Y?)mr",
1250 "VMASKMOVPS(Y?)mr",
1251 "VPMASKMOVD(Y?)mr",
1252 "VPMASKMOVQ(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1253
1254def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
1255 let Latency = 5;
1256 let NumMicroOps = 5;
1257 let ResourceCycles = [1,4];
1258}
1259def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;
1260
1261def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
1262 let Latency = 5;
1263 let NumMicroOps = 5;
1264 let ResourceCycles = [1,4];
1265}
1266def: InstRW<[BWWriteResGroup55], (instregex "XSETBV")>;
1267
1268def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
1269 let Latency = 5;
1270 let NumMicroOps = 5;
1271 let ResourceCycles = [2,3];
1272}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1273def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1274
1275def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1276 let Latency = 5;
1277 let NumMicroOps = 6;
1278 let ResourceCycles = [1,1,4];
1279}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1280def: InstRW<[BWWriteResGroup57], (instregex "PUSHF16", "PUSHF64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1281
1282def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
1283 let Latency = 6;
1284 let NumMicroOps = 1;
1285 let ResourceCycles = [1];
1286}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1287def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
1288 "LD_F64m",
1289 "LD_F80m",
1290 "VBROADCASTF128",
1291 "VBROADCASTI128",
1292 "VBROADCASTSDYrm",
1293 "VBROADCASTSSYrm",
1294 "VLDDQUYrm",
1295 "VMOVAPDYrm",
1296 "VMOVAPSYrm",
1297 "VMOVDDUPYrm",
1298 "VMOVDQAYrm",
1299 "VMOVDQUYrm",
1300 "VMOVNTDQAYrm",
1301 "VMOVSHDUPYrm",
1302 "VMOVSLDUPYrm",
1303 "VMOVUPDYrm",
1304 "VMOVUPSYrm",
1305 "VPBROADCASTDYrm",
1306 "VPBROADCASTQYrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1307 "(V?)ROUNDPD(Y?)r",
1308 "(V?)ROUNDPS(Y?)r",
1309 "(V?)ROUNDSDr",
1310 "(V?)ROUNDSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1311
1312def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
1313 let Latency = 6;
1314 let NumMicroOps = 2;
1315 let ResourceCycles = [1,1];
1316}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1317def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1318 "MMX_PSLLQrm",
1319 "MMX_PSLLWrm",
1320 "MMX_PSRADrm",
1321 "MMX_PSRAWrm",
1322 "MMX_PSRLDrm",
1323 "MMX_PSRLQrm",
1324 "MMX_PSRLWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1325 "VCVTPH2PS(Y?)rm",
1326 "(V?)CVTPS2PDrm",
1327 "(V?)CVTSS2SDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1328 "VPSLLVQrm",
1329 "VPSRLVQrm",
1330 "VTESTPDrm",
1331 "VTESTPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1332
1333def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
1334 let Latency = 6;
1335 let NumMicroOps = 2;
1336 let ResourceCycles = [1,1];
1337}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1338def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
1339 "VCVTPD2DQYrr",
1340 "VCVTPD2PSYrr",
1341 "VCVTPS2PHYrr",
1342 "VCVTTPD2DQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1343
1344def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
1345 let Latency = 6;
1346 let NumMicroOps = 2;
1347 let ResourceCycles = [1,1];
1348}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1349def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1350 "MMX_PINSRWrm",
1351 "MMX_PSHUFBrm",
1352 "MMX_PSHUFWmi",
1353 "MMX_PUNPCKHBWirm",
1354 "MMX_PUNPCKHDQirm",
1355 "MMX_PUNPCKHWDirm",
1356 "MMX_PUNPCKLBWirm",
1357 "MMX_PUNPCKLDQirm",
1358 "MMX_PUNPCKLWDirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1359 "(V?)ANDNPDrm",
1360 "(V?)ANDNPSrm",
1361 "(V?)ANDPDrm",
1362 "(V?)ANDPSrm",
1363 "(V?)INSERTPSrm",
1364 "(V?)MOVHPDrm",
1365 "(V?)MOVHPSrm",
1366 "(V?)MOVLPDrm",
1367 "(V?)MOVLPSrm",
1368 "(V?)ORPDrm",
1369 "(V?)ORPSrm",
1370 "(V?)PACKSSDWrm",
1371 "(V?)PACKSSWBrm",
1372 "(V?)PACKUSDWrm",
1373 "(V?)PACKUSWBrm",
1374 "(V?)PALIGNRrmi",
1375 "(V?)PBLENDWrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1376 "VPERMILPDmi",
1377 "VPERMILPDrm",
1378 "VPERMILPSmi",
1379 "VPERMILPSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1380 "(V?)PINSRBrm",
1381 "(V?)PINSRDrm",
1382 "(V?)PINSRQrm",
1383 "(V?)PINSRWrm",
1384 "(V?)PMOVSXBDrm",
1385 "(V?)PMOVSXBQrm",
1386 "(V?)PMOVSXBWrm",
1387 "(V?)PMOVSXDQrm",
1388 "(V?)PMOVSXWDrm",
1389 "(V?)PMOVSXWQrm",
1390 "(V?)PMOVZXBDrm",
1391 "(V?)PMOVZXBQrm",
1392 "(V?)PMOVZXBWrm",
1393 "(V?)PMOVZXDQrm",
1394 "(V?)PMOVZXWDrm",
1395 "(V?)PMOVZXWQrm",
1396 "(V?)PSHUFBrm",
1397 "(V?)PSHUFDmi",
1398 "(V?)PSHUFHWmi",
1399 "(V?)PSHUFLWmi",
1400 "(V?)PUNPCKHBWrm",
1401 "(V?)PUNPCKHDQrm",
1402 "(V?)PUNPCKHQDQrm",
1403 "(V?)PUNPCKHWDrm",
1404 "(V?)PUNPCKLBWrm",
1405 "(V?)PUNPCKLDQrm",
1406 "(V?)PUNPCKLQDQrm",
1407 "(V?)PUNPCKLWDrm",
1408 "(V?)SHUFPDrmi",
1409 "(V?)SHUFPSrmi",
1410 "(V?)UNPCKHPDrm",
1411 "(V?)UNPCKHPSrm",
1412 "(V?)UNPCKLPDrm",
1413 "(V?)UNPCKLPSrm",
1414 "(V?)XORPDrm",
1415 "(V?)XORPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1416
1417def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
1418 let Latency = 6;
1419 let NumMicroOps = 2;
1420 let ResourceCycles = [1,1];
1421}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1422def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
1423 "JMP(16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1424
1425def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
1426 let Latency = 6;
1427 let NumMicroOps = 2;
1428 let ResourceCycles = [1,1];
1429}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1430def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm",
1431 "ADCX(32|64)rm",
1432 "ADOX(32|64)rm",
1433 "BT(16|32|64)mi8",
1434 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
1435 "RORX(32|64)mi",
1436 "SARX(32|64)rm",
1437 "SBB(8|16|32|64)rm",
1438 "SHLX(32|64)rm",
1439 "SHRX(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1440
1441def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1442 let Latency = 6;
1443 let NumMicroOps = 2;
1444 let ResourceCycles = [1,1];
1445}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1446def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1447 "BLSI(32|64)rm",
1448 "BLSMSK(32|64)rm",
1449 "BLSR(32|64)rm",
1450 "BZHI(32|64)rm",
1451 "MMX_PABSBrm",
1452 "MMX_PABSDrm",
1453 "MMX_PABSWrm",
1454 "MMX_PADDBirm",
1455 "MMX_PADDDirm",
1456 "MMX_PADDQirm",
1457 "MMX_PADDSBirm",
1458 "MMX_PADDSWirm",
1459 "MMX_PADDUSBirm",
1460 "MMX_PADDUSWirm",
1461 "MMX_PADDWirm",
1462 "MMX_PAVGBirm",
1463 "MMX_PAVGWirm",
1464 "MMX_PCMPEQBirm",
1465 "MMX_PCMPEQDirm",
1466 "MMX_PCMPEQWirm",
1467 "MMX_PCMPGTBirm",
1468 "MMX_PCMPGTDirm",
1469 "MMX_PCMPGTWirm",
1470 "MMX_PMAXSWirm",
1471 "MMX_PMAXUBirm",
1472 "MMX_PMINSWirm",
1473 "MMX_PMINUBirm",
1474 "MMX_PSIGNBrm",
1475 "MMX_PSIGNDrm",
1476 "MMX_PSIGNWrm",
1477 "MMX_PSUBBirm",
1478 "MMX_PSUBDirm",
1479 "MMX_PSUBQirm",
1480 "MMX_PSUBSBirm",
1481 "MMX_PSUBSWirm",
1482 "MMX_PSUBUSBirm",
1483 "MMX_PSUBUSWirm",
1484 "MMX_PSUBWirm",
1485 "MOVBE(16|32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1486 "(V?)PABSBrm",
1487 "(V?)PABSDrm",
1488 "(V?)PABSWrm",
1489 "(V?)PADDBrm",
1490 "(V?)PADDDrm",
1491 "(V?)PADDQrm",
1492 "(V?)PADDSBrm",
1493 "(V?)PADDSWrm",
1494 "(V?)PADDUSBrm",
1495 "(V?)PADDUSWrm",
1496 "(V?)PADDWrm",
1497 "(V?)PAVGBrm",
1498 "(V?)PAVGWrm",
1499 "(V?)PCMPEQBrm",
1500 "(V?)PCMPEQDrm",
1501 "(V?)PCMPEQQrm",
1502 "(V?)PCMPEQWrm",
1503 "(V?)PCMPGTBrm",
1504 "(V?)PCMPGTDrm",
1505 "(V?)PCMPGTWrm",
1506 "(V?)PMAXSBrm",
1507 "(V?)PMAXSDrm",
1508 "(V?)PMAXSWrm",
1509 "(V?)PMAXUBrm",
1510 "(V?)PMAXUDrm",
1511 "(V?)PMAXUWrm",
1512 "(V?)PMINSBrm",
1513 "(V?)PMINSDrm",
1514 "(V?)PMINSWrm",
1515 "(V?)PMINUBrm",
1516 "(V?)PMINUDrm",
1517 "(V?)PMINUWrm",
1518 "(V?)PSIGNBrm",
1519 "(V?)PSIGNDrm",
1520 "(V?)PSIGNWrm",
1521 "(V?)PSUBBrm",
1522 "(V?)PSUBDrm",
1523 "(V?)PSUBQrm",
1524 "(V?)PSUBSBrm",
1525 "(V?)PSUBSWrm",
1526 "(V?)PSUBUSBrm",
1527 "(V?)PSUBUSWrm",
1528 "(V?)PSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1529
1530def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
1531 let Latency = 6;
1532 let NumMicroOps = 2;
1533 let ResourceCycles = [1,1];
1534}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1535def: InstRW<[BWWriteResGroup65], (instregex "MMX_PANDNirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1536 "MMX_PANDirm",
1537 "MMX_PORirm",
1538 "MMX_PXORirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1539 "(V?)BLENDPDrmi",
1540 "(V?)BLENDPSrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1541 "VINSERTF128rm",
1542 "VINSERTI128rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1543 "(V?)PANDNrm",
1544 "(V?)PANDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1545 "VPBLENDDrmi",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1546 "(V?)PORrm",
1547 "(V?)PXORrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1548
1549def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1550 let Latency = 6;
1551 let NumMicroOps = 2;
1552 let ResourceCycles = [1,1];
1553}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1554def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1555def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm",
1556 "AND(8|16|32|64)rm",
1557 "CMP(8|16|32|64)mi",
1558 "CMP(8|16|32|64)mr",
1559 "CMP(8|16|32|64)rm",
1560 "OR(8|16|32|64)rm",
1561 "POP(16|32|64)rmr",
1562 "SUB(8|16|32|64)rm",
1563 "TEST(8|16|32|64)mr",
1564 "TEST(8|16|32|64)mi",
1565 "XOR(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1566
1567def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1568 let Latency = 6;
1569 let NumMicroOps = 4;
1570 let ResourceCycles = [1,1,2];
1571}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1572def: InstRW<[BWWriteResGroup67], (instregex "SHLD(16|32|64)rrCL",
1573 "SHRD(16|32|64)rrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1574
1575def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1576 let Latency = 6;
1577 let NumMicroOps = 4;
1578 let ResourceCycles = [1,1,1,1];
1579}
1580def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1581
1582def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1583 let Latency = 6;
1584 let NumMicroOps = 4;
1585 let ResourceCycles = [1,1,1,1];
1586}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1587def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
1588 "BTR(16|32|64)mi8",
1589 "BTS(16|32|64)mi8",
1590 "SAR(8|16|32|64)m1",
1591 "SAR(8|16|32|64)mi",
1592 "SHL(8|16|32|64)m1",
1593 "SHL(8|16|32|64)mi",
1594 "SHR(8|16|32|64)m1",
1595 "SHR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1596
1597def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1598 let Latency = 6;
1599 let NumMicroOps = 4;
1600 let ResourceCycles = [1,1,1,1];
1601}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1602def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi",
1603 "ADD(8|16|32|64)mr",
1604 "AND(8|16|32|64)mi",
1605 "AND(8|16|32|64)mr",
1606 "DEC(8|16|32|64)m",
1607 "INC(8|16|32|64)m",
1608 "NEG(8|16|32|64)m",
1609 "NOT(8|16|32|64)m",
1610 "OR(8|16|32|64)mi",
1611 "OR(8|16|32|64)mr",
1612 "POP(16|32|64)rmm",
1613 "PUSH(16|32|64)rmm",
1614 "SUB(8|16|32|64)mi",
1615 "SUB(8|16|32|64)mr",
1616 "XOR(8|16|32|64)mi",
1617 "XOR(8|16|32|64)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1618
1619def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1620 let Latency = 6;
1621 let NumMicroOps = 6;
1622 let ResourceCycles = [1,5];
1623}
1624def: InstRW<[BWWriteResGroup71], (instregex "STD")>;
1625
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1626def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1627 let Latency = 7;
1628 let NumMicroOps = 2;
1629 let ResourceCycles = [1,1];
1630}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1631def: InstRW<[BWWriteResGroup73], (instregex "VPSLLDYrm",
1632 "VPSLLQYrm",
1633 "VPSLLVQYrm",
1634 "VPSLLWYrm",
1635 "VPSRADYrm",
1636 "VPSRAWYrm",
1637 "VPSRLDYrm",
1638 "VPSRLQYrm",
1639 "VPSRLVQYrm",
1640 "VPSRLWYrm",
1641 "VTESTPDYrm",
1642 "VTESTPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1643
1644def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1645 let Latency = 7;
1646 let NumMicroOps = 2;
1647 let ResourceCycles = [1,1];
1648}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1649def: InstRW<[BWWriteResGroup74], (instregex "FCOM32m",
1650 "FCOM64m",
1651 "FCOMP32m",
1652 "FCOMP64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1653
1654def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {
1655 let Latency = 7;
1656 let NumMicroOps = 2;
1657 let ResourceCycles = [1,1];
1658}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1659def: InstRW<[BWWriteResGroup75], (instregex "VANDNPDYrm",
1660 "VANDNPSYrm",
1661 "VANDPDYrm",
1662 "VANDPSYrm",
1663 "VORPDYrm",
1664 "VORPSYrm",
1665 "VPACKSSDWYrm",
1666 "VPACKSSWBYrm",
1667 "VPACKUSDWYrm",
1668 "VPACKUSWBYrm",
1669 "VPALIGNRYrmi",
1670 "VPBLENDWYrmi",
1671 "VPERMILPDYmi",
1672 "VPERMILPDYrm",
1673 "VPERMILPSYmi",
1674 "VPERMILPSYrm",
1675 "VPSHUFBYrm",
1676 "VPSHUFDYmi",
1677 "VPSHUFHWYmi",
1678 "VPSHUFLWYmi",
1679 "VPUNPCKHBWYrm",
1680 "VPUNPCKHDQYrm",
1681 "VPUNPCKHQDQYrm",
1682 "VPUNPCKHWDYrm",
1683 "VPUNPCKLBWYrm",
1684 "VPUNPCKLDQYrm",
1685 "VPUNPCKLQDQYrm",
1686 "VPUNPCKLWDYrm",
1687 "VSHUFPDYrmi",
1688 "VSHUFPSYrmi",
1689 "VUNPCKHPDYrm",
1690 "VUNPCKHPSYrm",
1691 "VUNPCKLPDYrm",
1692 "VUNPCKLPSYrm",
1693 "VXORPDYrm",
1694 "VXORPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1695
1696def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {
1697 let Latency = 7;
1698 let NumMicroOps = 2;
1699 let ResourceCycles = [1,1];
1700}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1701def: InstRW<[BWWriteResGroup76], (instregex "VPABSBYrm",
1702 "VPABSDYrm",
1703 "VPABSWYrm",
1704 "VPADDBYrm",
1705 "VPADDDYrm",
1706 "VPADDQYrm",
1707 "VPADDSBYrm",
1708 "VPADDSWYrm",
1709 "VPADDUSBYrm",
1710 "VPADDUSWYrm",
1711 "VPADDWYrm",
1712 "VPAVGBYrm",
1713 "VPAVGWYrm",
1714 "VPCMPEQBYrm",
1715 "VPCMPEQDYrm",
1716 "VPCMPEQQYrm",
1717 "VPCMPEQWYrm",
1718 "VPCMPGTBYrm",
1719 "VPCMPGTDYrm",
1720 "VPCMPGTWYrm",
1721 "VPMAXSBYrm",
1722 "VPMAXSDYrm",
1723 "VPMAXSWYrm",
1724 "VPMAXUBYrm",
1725 "VPMAXUDYrm",
1726 "VPMAXUWYrm",
1727 "VPMINSBYrm",
1728 "VPMINSDYrm",
1729 "VPMINSWYrm",
1730 "VPMINUBYrm",
1731 "VPMINUDYrm",
1732 "VPMINUWYrm",
1733 "VPSIGNBYrm",
1734 "VPSIGNDYrm",
1735 "VPSIGNWYrm",
1736 "VPSUBBYrm",
1737 "VPSUBDYrm",
1738 "VPSUBQYrm",
1739 "VPSUBSBYrm",
1740 "VPSUBSWYrm",
1741 "VPSUBUSBYrm",
1742 "VPSUBUSWYrm",
1743 "VPSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1744
1745def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1746 let Latency = 7;
1747 let NumMicroOps = 2;
1748 let ResourceCycles = [1,1];
1749}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1750def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi",
1751 "VBLENDPSYrmi",
1752 "VPANDNYrm",
1753 "VPANDYrm",
1754 "VPBLENDDYrmi",
1755 "VPORYrm",
1756 "VPXORYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1757
1758def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> {
1759 let Latency = 7;
1760 let NumMicroOps = 3;
1761 let ResourceCycles = [1,2];
1762}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1763def: InstRW<[BWWriteResGroup78], (instregex "(V?)MPSADBW(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1764
1765def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1766 let Latency = 7;
1767 let NumMicroOps = 3;
1768 let ResourceCycles = [2,1];
1769}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1770def: InstRW<[BWWriteResGroup79], (instregex "BLENDVPDrm0",
1771 "BLENDVPSrm0",
1772 "MMX_PACKSSDWirm",
1773 "MMX_PACKSSWBirm",
1774 "MMX_PACKUSWBirm",
1775 "PBLENDVBrm0",
1776 "VBLENDVPDrm",
1777 "VBLENDVPSrm",
1778 "VMASKMOVPDrm",
1779 "VMASKMOVPSrm",
1780 "VPBLENDVBrm",
1781 "VPMASKMOVDrm",
1782 "VPMASKMOVQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1783
1784def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1785 let Latency = 7;
1786 let NumMicroOps = 3;
1787 let ResourceCycles = [1,2];
1788}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1789def: InstRW<[BWWriteResGroup80], (instregex "LEAVE64",
1790 "SCASB",
1791 "SCASL",
1792 "SCASQ",
1793 "SCASW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1794
1795def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1796 let Latency = 7;
1797 let NumMicroOps = 3;
1798 let ResourceCycles = [1,1,1];
1799}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1800def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm",
1801 "PSLLQrm",
1802 "PSLLWrm",
1803 "PSRADrm",
1804 "PSRAWrm",
1805 "PSRLDrm",
1806 "PSRLQrm",
1807 "PSRLWrm",
1808 "PTESTrm",
1809 "VPSLLDrm",
1810 "VPSLLQrm",
1811 "VPSLLWrm",
1812 "VPSRADrm",
1813 "VPSRAWrm",
1814 "VPSRLDrm",
1815 "VPSRLQrm",
1816 "VPSRLWrm",
1817 "VPTESTrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1818
1819def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1820 let Latency = 7;
1821 let NumMicroOps = 3;
1822 let ResourceCycles = [1,1,1];
1823}
1824def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;
1825
1826def BWWriteResGroup83 : SchedWriteRes<[BWPort0,BWPort23,BWPort0156]> {
1827 let Latency = 7;
1828 let NumMicroOps = 3;
1829 let ResourceCycles = [1,1,1];
1830}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1831def: InstRW<[BWWriteResGroup83], (instregex "(V?)LDMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1832
1833def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1834 let Latency = 7;
1835 let NumMicroOps = 3;
1836 let ResourceCycles = [1,1,1];
1837}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1838def: InstRW<[BWWriteResGroup84], (instregex "LRETQ",
1839 "RETQ")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1840
1841def BWWriteResGroup85 : SchedWriteRes<[BWPort23,BWPort06,BWPort15]> {
1842 let Latency = 7;
1843 let NumMicroOps = 3;
1844 let ResourceCycles = [1,1,1];
1845}
Craig Toppera42a2ba2017-12-16 18:35:31 +0000[diff] [blame]1846def: InstRW<[BWWriteResGroup85], (instregex "BEXTR(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1847
1848def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1849 let Latency = 7;
1850 let NumMicroOps = 3;
1851 let ResourceCycles = [1,1,1];
1852}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1853def: InstRW<[BWWriteResGroup86], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1854
1855def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1856 let Latency = 7;
1857 let NumMicroOps = 5;
1858 let ResourceCycles = [1,1,1,2];
1859}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1860def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
1861 "ROL(8|16|32|64)mi",
1862 "ROR(8|16|32|64)m1",
1863 "ROR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1864
1865def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1866 let Latency = 7;
1867 let NumMicroOps = 5;
1868 let ResourceCycles = [1,1,1,2];
1869}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1870def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1871
1872def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1873 let Latency = 7;
1874 let NumMicroOps = 5;
1875 let ResourceCycles = [1,1,1,1,1];
1876}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1877def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m",
1878 "FARCALL64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1879
1880def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1881 let Latency = 7;
1882 let NumMicroOps = 7;
1883 let ResourceCycles = [2,2,1,2];
1884}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1885def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1886
1887def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1888 let Latency = 8;
1889 let NumMicroOps = 2;
1890 let ResourceCycles = [1,1];
1891}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1892def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1893def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>;
Simon Pilgrimf33d9052018-03-26 18:19:28 +0000[diff] [blame]1894def: InstRW<[BWWriteResGroup91], (instregex "MMX_CVTPI2PSirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1895 "MMX_CVTPS2PIirm",
1896 "MMX_CVTTPS2PIirm",
1897 "PDEP(32|64)rm",
1898 "PEXT(32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1899 "(V?)ADDPDrm",
1900 "(V?)ADDPSrm",
1901 "(V?)ADDSDrm",
1902 "(V?)ADDSSrm",
1903 "(V?)ADDSUBPDrm",
1904 "(V?)ADDSUBPSrm",
1905 "(V?)CMPPDrmi",
1906 "(V?)CMPPSrmi",
1907 "(V?)CMPSDrm",
1908 "(V?)CMPSSrm",
1909 "(V?)COMISDrm",
1910 "(V?)COMISSrm",
1911 "(V?)CVTDQ2PSrm",
1912 "(V?)CVTPS2DQrm",
1913 "(V?)CVTTPS2DQrm",
1914 "(V?)MAX(C?)PDrm",
1915 "(V?)MAX(C?)PSrm",
1916 "(V?)MAX(C?)SDrm",
1917 "(V?)MAX(C?)SSrm",
1918 "(V?)MIN(C?)PDrm",
1919 "(V?)MIN(C?)PSrm",
1920 "(V?)MIN(C?)SDrm",
1921 "(V?)MIN(C?)SSrm",
1922 "(V?)SUBPDrm",
1923 "(V?)SUBPSrm",
1924 "(V?)SUBSDrm",
1925 "(V?)SUBSSrm",
1926 "(V?)UCOMISDrm",
1927 "(V?)UCOMISSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1928
1929def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1930 let Latency = 8;
1931 let NumMicroOps = 3;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1932 let ResourceCycles = [1,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1933}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1934def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1935
1936def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1937 let Latency = 8;
1938 let NumMicroOps = 5;
1939}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1940def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1941
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1942def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1943 let Latency = 8;
1944 let NumMicroOps = 2;
1945 let ResourceCycles = [1,1];
1946}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1947def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm",
1948 "VPMOVSXBQYrm",
1949 "VPMOVSXBWYrm",
1950 "VPMOVSXDQYrm",
1951 "VPMOVSXWDYrm",
1952 "VPMOVSXWQYrm",
1953 "VPMOVZXWDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1954
1955def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {
1956 let Latency = 8;
1957 let NumMicroOps = 2;
1958 let ResourceCycles = [1,1];
1959}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1960def: InstRW<[BWWriteResGroup93], (instregex "(V?)MULPDrm",
1961 "(V?)MULPSrm",
1962 "(V?)MULSDrm",
1963 "(V?)MULSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1964
1965def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {
1966 let Latency = 8;
1967 let NumMicroOps = 3;
1968 let ResourceCycles = [2,1];
1969}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1970def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPDYrm",
1971 "VBLENDVPSYrm",
1972 "VMASKMOVPDYrm",
1973 "VMASKMOVPSYrm",
1974 "VPBLENDVBYrm",
1975 "VPMASKMOVDYrm",
1976 "VPMASKMOVQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1977
1978def BWWriteResGroup95 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1979 let Latency = 8;
1980 let NumMicroOps = 4;
1981 let ResourceCycles = [2,1,1];
1982}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1983def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm",
1984 "VPSRAVDrm",
1985 "VPSRLVDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1986
1987def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
1988 let Latency = 8;
1989 let NumMicroOps = 4;
1990 let ResourceCycles = [2,1,1];
1991}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1992def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm",
1993 "MMX_PHADDSWrm",
1994 "MMX_PHADDWrm",
1995 "MMX_PHSUBDrm",
1996 "MMX_PHSUBSWrm",
1997 "MMX_PHSUBWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1998 "(V?)PHADDDrm",
1999 "(V?)PHADDSWrm",
2000 "(V?)PHADDWrm",
2001 "(V?)PHSUBDrm",
2002 "(V?)PHSUBSWrm",
2003 "(V?)PHSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2004
2005def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2006 let Latency = 8;
2007 let NumMicroOps = 5;
2008 let ResourceCycles = [1,1,1,2];
2009}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2010def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
2011 "RCL(8|16|32|64)mi",
2012 "RCR(8|16|32|64)m1",
2013 "RCR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2014
2015def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2016 let Latency = 8;
2017 let NumMicroOps = 5;
2018 let ResourceCycles = [1,1,2,1];
2019}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2020def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2021
2022def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2023 let Latency = 8;
2024 let NumMicroOps = 6;
2025 let ResourceCycles = [1,1,1,3];
2026}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2027def: InstRW<[BWWriteResGroup99], (instregex "ADC(8|16|32|64)mi",
2028 "XCHG(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2029
2030def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2031 let Latency = 8;
2032 let NumMicroOps = 6;
2033 let ResourceCycles = [1,1,1,2,1];
2034}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2035def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mr",
2036 "CMPXCHG(8|16|32|64)rm",
2037 "ROL(8|16|32|64)mCL",
2038 "SAR(8|16|32|64)mCL",
2039 "SBB(8|16|32|64)mi",
2040 "SBB(8|16|32|64)mr",
2041 "SHL(8|16|32|64)mCL",
2042 "SHR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2043
2044def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
2045 let Latency = 9;
2046 let NumMicroOps = 2;
2047 let ResourceCycles = [1,1];
2048}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2049def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m",
2050 "ADD_F64m",
2051 "ILD_F16m",
2052 "ILD_F32m",
2053 "ILD_F64m",
2054 "SUBR_F32m",
2055 "SUBR_F64m",
2056 "SUB_F32m",
2057 "SUB_F64m",
2058 "VADDPDYrm",
2059 "VADDPSYrm",
2060 "VADDSUBPDYrm",
2061 "VADDSUBPSYrm",
2062 "VCMPPDYrmi",
2063 "VCMPPSYrmi",
2064 "VCVTDQ2PSYrm",
2065 "VCVTPS2DQYrm",
2066 "VCVTTPS2DQYrm",
2067 "VMAX(C?)PDYrm",
2068 "VMAX(C?)PSYrm",
2069 "VMIN(C?)PDYrm",
2070 "VMIN(C?)PSYrm",
2071 "VSUBPDYrm",
2072 "VSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2073
2074def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
2075 let Latency = 9;
2076 let NumMicroOps = 2;
2077 let ResourceCycles = [1,1];
2078}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2079def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm",
2080 "VPERM2I128rm",
2081 "VPERMDYrm",
2082 "VPERMPDYmi",
2083 "VPERMPSYrm",
2084 "VPERMQYmi",
2085 "VPMOVZXBDYrm",
2086 "VPMOVZXBQYrm",
2087 "VPMOVZXBWYrm",
2088 "VPMOVZXDQYrm",
2089 "VPMOVZXWQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2090
2091def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {
2092 let Latency = 9;
2093 let NumMicroOps = 2;
2094 let ResourceCycles = [1,1];
2095}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2096def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm",
2097 "VMULPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2098
2099def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2100 let Latency = 9;
2101 let NumMicroOps = 3;
2102 let ResourceCycles = [1,1,1];
2103}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2104def: InstRW<[BWWriteResGroup104], (instregex "(V?)DPPDrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2105
2106def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2107 let Latency = 9;
2108 let NumMicroOps = 3;
2109 let ResourceCycles = [1,1,1];
2110}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2111def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSD2SI64rm",
2112 "(V?)CVTSD2SIrm",
2113 "(V?)CVTSS2SI64rm",
2114 "(V?)CVTSS2SIrm",
2115 "(V?)CVTTSD2SI64rm",
2116 "(V?)CVTTSD2SIrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2117 "VCVTTSS2SI64rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2118 "(V?)CVTTSS2SIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2119
2120def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2121 let Latency = 9;
2122 let NumMicroOps = 3;
2123 let ResourceCycles = [1,1,1];
2124}
2125def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;
2126
2127def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2128 let Latency = 9;
2129 let NumMicroOps = 3;
2130 let ResourceCycles = [1,1,1];
2131}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2132def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2133def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2DQrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2134 "CVTPD2PSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2135 "CVTTPD2DQrm",
2136 "MMX_CVTPD2PIirm",
2137 "MMX_CVTPI2PDirm",
2138 "MMX_CVTTPD2PIirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2139 "(V?)CVTDQ2PDrm",
2140 "(V?)CVTSD2SSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2141
2142def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
2143 let Latency = 9;
2144 let NumMicroOps = 3;
2145 let ResourceCycles = [1,1,1];
2146}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2147def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
2148 "VPBROADCASTW(Y?)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2149
2150def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2151 let Latency = 9;
2152 let NumMicroOps = 4;
2153 let ResourceCycles = [2,1,1];
2154}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2155def: InstRW<[BWWriteResGroup109], (instregex "VPSLLVDYrm",
2156 "VPSRAVDYrm",
2157 "VPSRLVDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2158
2159def BWWriteResGroup110 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2160 let Latency = 9;
2161 let NumMicroOps = 4;
2162 let ResourceCycles = [2,1,1];
2163}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2164def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm",
2165 "VPHADDSWYrm",
2166 "VPHADDWYrm",
2167 "VPHSUBDYrm",
2168 "VPHSUBSWYrm",
2169 "VPHSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2170
2171def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {
2172 let Latency = 9;
2173 let NumMicroOps = 4;
2174 let ResourceCycles = [1,1,1,1];
2175}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2176def: InstRW<[BWWriteResGroup111], (instregex "SHLD(16|32|64)mri8",
2177 "SHRD(16|32|64)mri8")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2178
2179def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2180 let Latency = 9;
2181 let NumMicroOps = 5;
2182 let ResourceCycles = [1,1,3];
2183}
2184def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
2185
2186def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2187 let Latency = 9;
2188 let NumMicroOps = 5;
2189 let ResourceCycles = [1,2,1,1];
2190}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2191def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
2192 "LSL(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2193
2194def BWWriteResGroup114 : SchedWriteRes<[BWPort0]> {
2195 let Latency = 10;
2196 let NumMicroOps = 2;
2197 let ResourceCycles = [2];
2198}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2199def: InstRW<[BWWriteResGroup114], (instregex "(V?)PMULLD(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2200
2201def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
2202 let Latency = 10;
2203 let NumMicroOps = 2;
2204 let ResourceCycles = [1,1];
2205}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2206def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
2207 "MMX_PMADDWDirm",
2208 "MMX_PMULHRSWrm",
2209 "MMX_PMULHUWirm",
2210 "MMX_PMULHWirm",
2211 "MMX_PMULLWirm",
2212 "MMX_PMULUDQirm",
2213 "MMX_PSADBWirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2214 "(V?)PCMPGTQrm",
2215 "(V?)PHMINPOSUWrm",
2216 "(V?)PMADDUBSWrm",
2217 "(V?)PMADDWDrm",
2218 "(V?)PMULDQrm",
2219 "(V?)PMULHRSWrm",
2220 "(V?)PMULHUWrm",
2221 "(V?)PMULHWrm",
2222 "(V?)PMULLWrm",
2223 "(V?)PMULUDQrm",
2224 "(V?)PSADBWrm",
2225 "(V?)RCPPSm",
2226 "(V?)RCPSSm",
2227 "(V?)RSQRTPSm",
2228 "(V?)RSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2229
2230def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {
2231 let Latency = 10;
2232 let NumMicroOps = 2;
2233 let ResourceCycles = [1,1];
2234}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2235def: InstRW<[BWWriteResGroup116],
2236 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m",
2237 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2238
2239def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
2240 let Latency = 10;
2241 let NumMicroOps = 3;
2242 let ResourceCycles = [2,1];
2243}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2244def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m",
2245 "FICOM32m",
2246 "FICOMP16m",
2247 "FICOMP32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2248
2249def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2250 let Latency = 10;
2251 let NumMicroOps = 3;
2252 let ResourceCycles = [1,1,1];
2253}
2254def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
2255
2256def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2257 let Latency = 10;
2258 let NumMicroOps = 4;
2259 let ResourceCycles = [1,2,1];
2260}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2261def: InstRW<[BWWriteResGroup119], (instregex "(V?)HADDPDrm",
2262 "(V?)HADDPSrm",
2263 "(V?)HSUBPDrm",
2264 "(V?)HSUBPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2265
2266def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2267 let Latency = 10;
2268 let NumMicroOps = 4;
2269 let ResourceCycles = [1,1,1,1];
2270}
2271def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
2272
2273def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2274 let Latency = 9;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2275 let NumMicroOps = 4;
2276 let ResourceCycles = [1,1,1,1];
2277}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2278def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2279
2280def BWWriteResGroup122 : SchedWriteRes<[BWPort0]> {
2281 let Latency = 11;
2282 let NumMicroOps = 1;
2283 let ResourceCycles = [1];
2284}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2285def: InstRW<[BWWriteResGroup122], (instregex "(V?)DIVPSrr",
2286 "(V?)DIVSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2287
2288def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
2289 let Latency = 11;
2290 let NumMicroOps = 2;
2291 let ResourceCycles = [1,1];
2292}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2293def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m",
2294 "MUL_F64m",
2295 "VPCMPGTQYrm",
2296 "VPMADDUBSWYrm",
2297 "VPMADDWDYrm",
2298 "VPMULDQYrm",
2299 "VPMULHRSWYrm",
2300 "VPMULHUWYrm",
2301 "VPMULHWYrm",
2302 "VPMULLWYrm",
2303 "VPMULUDQYrm",
2304 "VPSADBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2305
2306def BWWriteResGroup124 : SchedWriteRes<[BWPort01,BWPort23]> {
2307 let Latency = 11;
2308 let NumMicroOps = 2;
2309 let ResourceCycles = [1,1];
2310}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2311def: InstRW<[BWWriteResGroup124],
2312 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2313
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2314def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {
2315 let Latency = 11;
2316 let NumMicroOps = 3;
2317 let ResourceCycles = [2,1];
2318}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2319def: InstRW<[BWWriteResGroup126], (instregex "VRCPPSYr",
2320 "VRSQRTPSYr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2321
2322def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> {
2323 let Latency = 11;
2324 let NumMicroOps = 3;
2325 let ResourceCycles = [2,1];
2326}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2327def: InstRW<[BWWriteResGroup127], (instregex "(V?)ROUNDPDm",
2328 "(V?)ROUNDPSm",
2329 "(V?)ROUNDSDm",
2330 "(V?)ROUNDSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2331
2332def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2333 let Latency = 11;
2334 let NumMicroOps = 3;
2335 let ResourceCycles = [1,1,1];
2336}
2337def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;
2338
2339def BWWriteResGroup129 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2340 let Latency = 11;
2341 let NumMicroOps = 4;
2342 let ResourceCycles = [1,2,1];
2343}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2344def: InstRW<[BWWriteResGroup129], (instregex "VHADDPDYrm",
2345 "VHADDPSYrm",
2346 "VHSUBPDYrm",
2347 "VHSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2348
2349def BWWriteResGroup130 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2350 let Latency = 11;
2351 let NumMicroOps = 6;
2352 let ResourceCycles = [1,1,1,1,2];
2353}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2354def: InstRW<[BWWriteResGroup130], (instregex "SHLD(16|32|64)mrCL",
2355 "SHRD(16|32|64)mrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2356
2357def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
2358 let Latency = 11;
2359 let NumMicroOps = 7;
2360 let ResourceCycles = [2,2,3];
2361}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2362def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
2363 "RCR(16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2364
2365def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2366 let Latency = 11;
2367 let NumMicroOps = 9;
2368 let ResourceCycles = [1,4,1,3];
2369}
2370def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;
2371
2372def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
2373 let Latency = 11;
2374 let NumMicroOps = 11;
2375 let ResourceCycles = [2,9];
2376}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2377def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
2378def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2379
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2380def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
2381 let Latency = 12;
2382 let NumMicroOps = 3;
2383 let ResourceCycles = [2,1];
2384}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2385def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
2386 "ADD_FI32m",
2387 "SUBR_FI16m",
2388 "SUBR_FI32m",
2389 "SUB_FI16m",
2390 "SUB_FI32m",
Craig Topper40d3b322018-03-22 21:55:20 +0000[diff] [blame]2391 "VROUNDPDYm",
2392 "VROUNDPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2393
2394def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2395 let Latency = 12;
2396 let NumMicroOps = 4;
2397 let ResourceCycles = [1,2,1];
2398}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2399def: InstRW<[BWWriteResGroup136], (instregex "(V?)MPSADBWrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2400
2401def BWWriteResGroup137 : SchedWriteRes<[BWPort0]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2402 let Latency = 11;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2403 let NumMicroOps = 1;
2404 let ResourceCycles = [1];
2405}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2406def: InstRW<[BWWriteResGroup137], (instregex "(V?)SQRTPSr",
2407 "(V?)SQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2408
2409def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2410 let Latency = 13;
2411 let NumMicroOps = 4;
2412 let ResourceCycles = [1,2,1];
2413}
2414def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
2415
2416def BWWriteResGroup139 : SchedWriteRes<[BWPort0]> {
2417 let Latency = 14;
2418 let NumMicroOps = 1;
2419 let ResourceCycles = [1];
2420}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2421def: InstRW<[BWWriteResGroup139], (instregex "(V?)DIVPDrr",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2422 "(V?)DIVSDrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2423
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2424def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2425 let Latency = 14;
2426 let NumMicroOps = 3;
2427 let ResourceCycles = [1,1,1];
2428}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2429def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m",
2430 "MUL_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2431
2432def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2433 let Latency = 14;
2434 let NumMicroOps = 4;
2435 let ResourceCycles = [2,1,1];
2436}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2437def: InstRW<[BWWriteResGroup142], (instregex "(V?)DPPS(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2438
2439def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2440 let Latency = 14;
2441 let NumMicroOps = 4;
2442 let ResourceCycles = [1,1,1,1];
2443}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2444def: InstRW<[BWWriteResGroup143], (instregex "(V?)DPPDrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2445
2446def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2447 let Latency = 14;
2448 let NumMicroOps = 8;
2449 let ResourceCycles = [2,2,1,3];
2450}
2451def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
2452
2453def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2454 let Latency = 14;
2455 let NumMicroOps = 10;
2456 let ResourceCycles = [2,3,1,4];
2457}
2458def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;
2459
2460def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
2461 let Latency = 14;
2462 let NumMicroOps = 12;
2463 let ResourceCycles = [2,1,4,5];
2464}
2465def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>;
2466
2467def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
2468 let Latency = 15;
2469 let NumMicroOps = 1;
2470 let ResourceCycles = [1];
2471}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2472def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FPrST0",
2473 "DIVR_FST0r",
2474 "DIVR_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2475
2476def BWWriteResGroup148 : SchedWriteRes<[BWPort0,BWPort23]> {
2477 let Latency = 15;
2478 let NumMicroOps = 3;
2479 let ResourceCycles = [2,1];
2480}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2481def: InstRW<[BWWriteResGroup148], (instregex "(V?)PMULLDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2482
2483def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2484 let Latency = 15;
2485 let NumMicroOps = 10;
2486 let ResourceCycles = [1,1,1,4,1,2];
2487}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2488def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2489
2490def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23]> {
2491 let Latency = 16;
2492 let NumMicroOps = 2;
2493 let ResourceCycles = [1,1];
2494}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2495def: InstRW<[BWWriteResGroup150], (instregex "(V?)DIVPSrm",
2496 "(V?)DIVSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2497
2498def BWWriteResGroup151 : SchedWriteRes<[BWPort0,BWPort23]> {
2499 let Latency = 16;
2500 let NumMicroOps = 3;
2501 let ResourceCycles = [2,1];
2502}
2503def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;
2504
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2505def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2506 let Latency = 16;
2507 let NumMicroOps = 14;
2508 let ResourceCycles = [1,1,1,4,2,5];
2509}
2510def: InstRW<[BWWriteResGroup153], (instregex "CMPXCHG8B")>;
2511
2512def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {
2513 let Latency = 16;
2514 let NumMicroOps = 16;
2515 let ResourceCycles = [16];
2516}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2517def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2518
2519def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015]> {
2520 let Latency = 17;
2521 let NumMicroOps = 3;
2522 let ResourceCycles = [2,1];
2523}
2524def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;
2525
2526def BWWriteResGroup156 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2527 let Latency = 17;
2528 let NumMicroOps = 4;
2529 let ResourceCycles = [2,1,1];
2530}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2531def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm",
2532 "VRSQRTPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2533
2534def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2535 let Latency = 16;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2536 let NumMicroOps = 2;
2537 let ResourceCycles = [1,1];
2538}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2539def: InstRW<[BWWriteResGroup157], (instregex "(V?)SQRTPSm",
2540 "(V?)SQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2541
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2542def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
2543 let Latency = 18;
2544 let NumMicroOps = 8;
2545 let ResourceCycles = [1,1,1,5];
2546}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2547def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2548def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2549
2550def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2551 let Latency = 18;
2552 let NumMicroOps = 11;
2553 let ResourceCycles = [2,1,1,3,1,3];
2554}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2555def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2556
2557def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> {
2558 let Latency = 19;
2559 let NumMicroOps = 2;
2560 let ResourceCycles = [1,1];
2561}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2562def: InstRW<[BWWriteResGroup161], (instregex "(V?)DIVPDrm",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2563 "(V?)DIVSDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2564
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2565def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2566 let Latency = 19;
2567 let NumMicroOps = 5;
2568 let ResourceCycles = [2,1,1,1];
2569}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2570def: InstRW<[BWWriteResGroup163], (instregex "(V?)DPPSrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2571
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2572def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
2573 let Latency = 20;
2574 let NumMicroOps = 1;
2575 let ResourceCycles = [1];
2576}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2577def: InstRW<[BWWriteResGroup165], (instregex "DIV_FPrST0",
2578 "DIV_FST0r",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2579 "DIV_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2580
2581def BWWriteResGroup166 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2582 let Latency = 20;
2583 let NumMicroOps = 5;
2584 let ResourceCycles = [2,1,1,1];
2585}
2586def: InstRW<[BWWriteResGroup166], (instregex "VDPPSYrmi")>;
2587
2588def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2589 let Latency = 20;
2590 let NumMicroOps = 8;
2591 let ResourceCycles = [1,1,1,1,1,1,2];
2592}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2593def: InstRW<[BWWriteResGroup167], (instregex "INSB",
2594 "INSL",
2595 "INSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2596
2597def BWWriteResGroup168 : SchedWriteRes<[BWPort0]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2598 let Latency = 16;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2599 let NumMicroOps = 1;
2600 let ResourceCycles = [1];
2601}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2602def: InstRW<[BWWriteResGroup168], (instregex "(V?)SQRTPDr",
2603 "(V?)SQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2604
2605def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
2606 let Latency = 21;
2607 let NumMicroOps = 2;
2608 let ResourceCycles = [1,1];
2609}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2610def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
2611 "DIV_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2612
2613def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015]> {
2614 let Latency = 21;
2615 let NumMicroOps = 3;
2616 let ResourceCycles = [2,1];
2617}
2618def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;
2619
2620def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2621 let Latency = 21;
2622 let NumMicroOps = 19;
2623 let ResourceCycles = [2,1,4,1,1,4,6];
2624}
2625def: InstRW<[BWWriteResGroup171], (instregex "CMPXCHG16B")>;
2626
2627def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2628 let Latency = 22;
2629 let NumMicroOps = 18;
2630 let ResourceCycles = [1,1,16];
2631}
2632def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
2633
2634def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015]> {
2635 let Latency = 23;
2636 let NumMicroOps = 3;
2637 let ResourceCycles = [2,1];
2638}
2639def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;
2640
2641def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2642 let Latency = 23;
2643 let NumMicroOps = 4;
2644 let ResourceCycles = [2,1,1];
2645}
2646def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
2647
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2648def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2649 let Latency = 23;
2650 let NumMicroOps = 19;
2651 let ResourceCycles = [3,1,15];
2652}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]2653def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2654
2655def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2656 let Latency = 24;
2657 let NumMicroOps = 3;
2658 let ResourceCycles = [1,1,1];
2659}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2660def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
2661 "DIV_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2662
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2663def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23]> {
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2664 let Latency = 21;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2665 let NumMicroOps = 2;
2666 let ResourceCycles = [1,1];
2667}
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2668def: InstRW<[BWWriteResGroup179], (instregex "(V?)SQRTPDm",
2669 "(V?)SQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2670
2671def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
2672 let Latency = 26;
2673 let NumMicroOps = 2;
2674 let ResourceCycles = [1,1];
2675}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2676def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
Craig Toppercdfcf8e2018-03-26 05:05:10 +0000[diff] [blame]2677 "DIVR_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2678
2679def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2680 let Latency = 27;
2681 let NumMicroOps = 4;
2682 let ResourceCycles = [2,1,1];
2683}
2684def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;
2685
2686def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2687 let Latency = 29;
2688 let NumMicroOps = 3;
2689 let ResourceCycles = [1,1,1];
2690}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2691def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
2692 "DIVR_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2693
2694def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2695 let Latency = 29;
2696 let NumMicroOps = 4;
2697 let ResourceCycles = [2,1,1];
2698}
2699def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;
2700
2701def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2702 let Latency = 22;
2703 let NumMicroOps = 7;
2704 let ResourceCycles = [1,3,2,1];
2705}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2706def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2707
2708def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2709 let Latency = 23;
2710 let NumMicroOps = 9;
2711 let ResourceCycles = [1,3,4,1];
2712}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2713def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2714
2715def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2716 let Latency = 24;
2717 let NumMicroOps = 9;
2718 let ResourceCycles = [1,5,2,1];
2719}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2720def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2721
2722def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2723 let Latency = 25;
2724 let NumMicroOps = 7;
2725 let ResourceCycles = [1,3,2,1];
2726}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2727def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
2728 VGATHERDPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2729
2730def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2731 let Latency = 26;
2732 let NumMicroOps = 9;
2733 let ResourceCycles = [1,5,2,1];
2734}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2735def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2736
2737def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2738 let Latency = 26;
2739 let NumMicroOps = 14;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2740 let ResourceCycles = [1,4,8,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2741}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2742def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2743
2744def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2745 let Latency = 27;
2746 let NumMicroOps = 9;
2747 let ResourceCycles = [1,5,2,1];
2748}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2749def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2750
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2751def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2752 let Latency = 29;
2753 let NumMicroOps = 27;
2754 let ResourceCycles = [1,5,1,1,19];
2755}
2756def: InstRW<[BWWriteResGroup185], (instregex "XSAVE64")>;
2757
2758def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2759 let Latency = 30;
2760 let NumMicroOps = 28;
2761 let ResourceCycles = [1,6,1,1,19];
2762}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2763def: InstRW<[BWWriteResGroup186], (instregex "^XSAVE$", "XSAVEC", "XSAVES", "XSAVEOPT")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2764
2765def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {
2766 let Latency = 31;
2767 let NumMicroOps = 31;
2768 let ResourceCycles = [8,1,21,1];
2769}
2770def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
2771
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2772def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015]> {
2773 let Latency = 34;
2774 let NumMicroOps = 3;
2775 let ResourceCycles = [2,1];
2776}
2777def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;
2778
2779def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2780 let Latency = 34;
2781 let NumMicroOps = 8;
2782 let ResourceCycles = [2,2,2,1,1];
2783}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2784def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2785
2786def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
2787 let Latency = 34;
2788 let NumMicroOps = 23;
2789 let ResourceCycles = [1,5,3,4,10];
2790}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2791def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
2792 "IN(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2793
2794def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2795 let Latency = 35;
2796 let NumMicroOps = 8;
2797 let ResourceCycles = [2,2,2,1,1];
2798}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2799def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2800
2801def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2802 let Latency = 35;
2803 let NumMicroOps = 23;
2804 let ResourceCycles = [1,5,2,1,4,10];
2805}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2806def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
2807 "OUT(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2808
2809def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2810 let Latency = 40;
2811 let NumMicroOps = 4;
2812 let ResourceCycles = [2,1,1];
2813}
2814def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;
2815
2816def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
2817 let Latency = 42;
2818 let NumMicroOps = 22;
2819 let ResourceCycles = [2,20];
2820}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2821def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2822
2823def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
2824 let Latency = 60;
2825 let NumMicroOps = 64;
2826 let ResourceCycles = [2,2,8,1,10,2,39];
2827}
2828def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2829
2830def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2831 let Latency = 63;
2832 let NumMicroOps = 88;
2833 let ResourceCycles = [4,4,31,1,2,1,45];
2834}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2835def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2836
2837def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2838 let Latency = 63;
2839 let NumMicroOps = 90;
2840 let ResourceCycles = [4,2,33,1,2,1,47];
2841}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2842def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2843
2844def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
2845 let Latency = 75;
2846 let NumMicroOps = 15;
2847 let ResourceCycles = [6,3,6];
2848}
2849def: InstRW<[BWWriteResGroup200], (instregex "FNINIT")>;
2850
2851def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
2852 let Latency = 80;
2853 let NumMicroOps = 32;
2854 let ResourceCycles = [7,7,3,3,1,11];
2855}
2856def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;
2857
2858def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
2859 let Latency = 115;
2860 let NumMicroOps = 100;
2861 let ResourceCycles = [9,9,11,8,1,11,21,30];
2862}
2863def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2864
2865} // SchedModel
2866