commit a35f306740182bd02191f573983dbea0a0036ecd
author Chris Lattner <sabre@nondot.org> Fri Jun 16 17:34:12 2006 +0000
committer Chris Lattner <sabre@nondot.org> Fri Jun 16 17:34:12 2006 +0000
tree dda049ba457302630fb70f8c45e33d3a44c95b61
parent 29052c849fac31468cea718890c90026fd177072

Rename some subtarget features.  A CPU now can *have* 64-bit instructions,
can in 32-bit mode we can choose to optionally *use* 64-bit registers.

llvm-svn: 28824

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
index 607771b..b228ba7 100644
--- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
+++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp
@@ -73,8 +73,8 @@
   : StackAlignment(16)
   , InstrItins()
   , IsGigaProcessor(false)
-  , Is64Bit(false)
-  , Has64BitRegs(false)
+  , Has64BitSupport(false)
+  , Use64BitRegs(false)
   , HasAltivec(false)
   , HasFSQRT(false)
   , HasSTFIWX(false)