[opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
llvm-svn: 230794
diff --git a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll
index 8ce6091..a4d08f9 100644
--- a/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-fast-isel.ll
@@ -9,7 +9,7 @@
; CHECK: ret
%a.addr = alloca i32, align 4
store i32 %a, i32* %a.addr
- %tmp = load i32* %a.addr
+ %tmp = load i32, i32* %a.addr
store i32 %tmp, i32* %a.addr
ret void
}
@@ -22,7 +22,7 @@
; CHECK: ret
%a.addr = alloca i64, align 4
store i64 %a, i64* %a.addr
- %tmp = load i64* %a.addr
+ %tmp = load i64, i64* %a.addr
store i64 %tmp, i64* %a.addr
ret void
}
@@ -39,7 +39,7 @@
; CHECK: ret
%a.addr = alloca i1, align 1
store i1 %a, i1* %a.addr, align 1
- %0 = load i1* %a.addr, align 1
+ %0 = load i1, i1* %a.addr, align 1
ret i1 %0
}
@@ -49,7 +49,7 @@
; CHECK: ldur w0, [x0, #-4]
; CHECK: ret
%0 = getelementptr i32, i32 *%ptr, i32 -1
- %1 = load i32* %0, align 4
+ %1 = load i32, i32* %0, align 4
ret i32 %1
}
@@ -59,7 +59,7 @@
; CHECK: ldur w0, [x0, #-256]
; CHECK: ret
%0 = getelementptr i32, i32 *%ptr, i32 -64
- %1 = load i32* %0, align 4
+ %1 = load i32, i32* %0, align 4
ret i32 %1
}