Change the default scheduler from Latency to ILP, since Latency
is going away.
llvm-svn: 142810
diff --git a/llvm/test/CodeGen/Mips/i64arg.ll b/llvm/test/CodeGen/Mips/i64arg.ll
index 87cf2a6..8b1f71b 100644
--- a/llvm/test/CodeGen/Mips/i64arg.ll
+++ b/llvm/test/CodeGen/Mips/i64arg.ll
@@ -4,21 +4,21 @@
entry:
; CHECK: addu $[[R1:[0-9]+]], $zero, $5
; CHECK: addu $[[R0:[0-9]+]], $zero, $4
-; CHECK: lw $25, %call16(ff1)
; CHECK: ori $6, ${{[0-9]+}}, 3855
; CHECK: ori $7, ${{[0-9]+}}, 22136
+; CHECK: lw $25, %call16(ff1)
; CHECK: jalr
tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
; CHECK: lw $25, %call16(ff2)
-; CHECK: lw $[[R2:[0-9]+]], 88($sp)
-; CHECK: lw $[[R3:[0-9]+]], 92($sp)
+; CHECK: lw $[[R2:[0-9]+]], 80($sp)
+; CHECK: lw $[[R3:[0-9]+]], 84($sp)
; CHECK: addu $4, $zero, $[[R2]]
; CHECK: addu $5, $zero, $[[R3]]
; CHECK: jalr $25
tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
%sub = add nsw i32 %i, -1
-; CHECK: sw $[[R0]], 24($sp)
; CHECK: sw $[[R1]], 28($sp)
+; CHECK: sw $[[R0]], 24($sp)
; CHECK: lw $25, %call16(ff3)
; CHECK: addu $6, $zero, $[[R2]]
; CHECK: addu $7, $zero, $[[R3]]