commit c4b8d367a8bc9bf39fb0c8ebf08ce7e3f53aa9d3
author Simon Pilgrim <llvm-dev@redking.me.uk> Fri May 18 14:08:01 2018 +0000
committer Simon Pilgrim <llvm-dev@redking.me.uk> Fri May 18 14:08:01 2018 +0000
tree ce34a0f3cbd5ac525a2a92fde6e66ee902cc8e4b
parent a840a465579a91418575c77ca6c04ded28f55b1a

[X86][SSE] Ensure vector partial load/stores use the WriteVecLoad/WriteVecStore scheduler classes

Retag some instructions that were missed when we split off vector load/store/moves - MOVQ/MOVD etc.

Fixes BtVer2/SLM which have different behaviours for GPR stores.

llvm-svn: 332718

llvm/lib/Target/X86/X86SchedBroadwell.td

diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 743279d..568cef7 100755
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -600,13 +600,7 @@
   let ResourceCycles = [1,1];
 }
 def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
-                                            "MMX_MOVD64mr",
-                                            "ST_FP(32|64|80)m",
-                                            "(V?)MOV(H|L)(PD|PS)mr",
-                                            "(V?)MOVPDI2DImr",
-                                            "(V?)MOVPQI2QImr",
-                                            "(V?)MOVPQIto64mr",
-                                            "(V?)MOV(SD|SS)mr")>;
+                                            "ST_FP(32|64|80)m")>;
 
 def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
   let Latency = 2;