llvm/test/CodeGen/X86/pr14314.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i386-pc-linux -mcpu=corei7 | FileCheck %s

define i64 @atomicSub(i64* %a, i64 %b) nounwind {
; CHECK-LABEL: atomicSub:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    pushl %ebp
; CHECK-NEXT:    pushl %ebx
; CHECK-NEXT:    pushl %edi
; CHECK-NEXT:    pushl %esi
; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edi
; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ebp
; CHECK-NEXT:    movl (%ebp), %eax
; CHECK-NEXT:    movl 4(%ebp), %edx
; CHECK-NEXT:    .p2align 4, 0x90
; CHECK-NEXT:  .LBB0_1: # %atomicrmw.start
; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    movl %eax, %ebx
; CHECK-NEXT:    subl %edi, %ebx
; CHECK-NEXT:    movl %edx, %ecx
; CHECK-NEXT:    sbbl %esi, %ecx
; CHECK-NEXT:    lock cmpxchg8b (%ebp)
; CHECK-NEXT:    jne .LBB0_1
; CHECK-NEXT:  # %bb.2: # %atomicrmw.end
; CHECK-NEXT:    popl %esi
; CHECK-NEXT:    popl %edi
; CHECK-NEXT:    popl %ebx
; CHECK-NEXT:    popl %ebp
; CHECK-NEXT:    retl
entry:
  %0 = atomicrmw sub i64* %a, i64 %b seq_cst
  ret i64 %0
}