commit ddcb95664e4d94ca9b236066e29d3d92650097aa
author Mandeep Singh Grang <mgrang@codeaurora.org> Wed May 23 22:44:08 2018 +0000
committer Mandeep Singh Grang <mgrang@codeaurora.org> Wed May 23 22:44:08 2018 +0000
tree fc2f4940c01737854dd61c9c679accddbda1c6c4
parent 767d92e3fb538690a7524c314c825df827048829

[RISCV] Lower the tail pseudoinstruction

This patch lowers the tail pseudoinstruction. This has been modeled after ARM's
tail call opt.

llvm-svn: 333137

llvm/lib/Target/RISCV/RISCVISelLowering.h

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 83a3bfd..52bbfa1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -28,7 +28,8 @@
   CALL,
   SELECT_CC,
   BuildPairF64,
-  SplitF64
+  SplitF64,
+  TAIL
 };
 }
 
@@ -100,6 +101,10 @@
   SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
+
+  bool IsEligibleForTailCallOptimization(CCState &CCInfo,
+    CallLoweringInfo &CLI, MachineFunction &MF,
+    const SmallVector<CCValAssign, 16> &ArgLocs) const;
 };
 }