commit e3a676e9adba668a7da944766218e98dd4b2c10a
author Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jun 24 15:50:29 2019 +0000
committer Matt Arsenault <Matthew.Arsenault@amd.com> Mon Jun 24 15:50:29 2019 +0000
tree 632a983ae9fe72b635cf72262bf2e9a0cbe6dce3
parent 3260ef16bbdecc391d7da8fe3bbe19585f6ccb19

CodeGen: Introduce a class for registers

Avoids using a plain unsigned for registers throughoug codegen.
Doesn't attempt to change every register use, just something a little
more than the set needed to build after changing the return type of
MachineOperand::getReg().

llvm-svn: 364191

llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp

diff --git a/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp b/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
index f7dda96..aed0b3f 100644
--- a/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
+++ b/llvm/unittests/CodeGen/GlobalISel/PatternMatchTest.cpp
@@ -161,7 +161,7 @@
   bool match =
       mi_match(MIBAdd->getOperand(0).getReg(), MRI, m_GAdd(m_Reg(), m_Reg()));
   EXPECT_TRUE(match);
-  unsigned Src0, Src1, Src2;
+  Register Src0, Src1, Src2;
   match = mi_match(MIBAdd->getOperand(0).getReg(), MRI,
                    m_GAdd(m_Reg(Src0), m_Reg(Src1)));
   EXPECT_TRUE(match);
@@ -292,7 +292,7 @@
   bool match = mi_match(MIBFabs->getOperand(0).getReg(), MRI, m_GFabs(m_Reg()));
   EXPECT_TRUE(match);
 
-  unsigned Src;
+  Register Src;
   auto MIBFNeg = B.buildInstr(TargetOpcode::G_FNEG, {s32}, {Copy0s32});
   match = mi_match(MIBFNeg->getOperand(0).getReg(), MRI, m_GFNeg(m_Reg(Src)));
   EXPECT_TRUE(match);
@@ -360,7 +360,7 @@
   auto MIBAExt = B.buildAnyExt(s64, MIBTrunc);
   auto MIBZExt = B.buildZExt(s64, MIBTrunc);
   auto MIBSExt = B.buildSExt(s64, MIBTrunc);
-  unsigned Src0;
+  Register Src0;
   bool match =
       mi_match(MIBTrunc->getOperand(0).getReg(), MRI, m_GTrunc(m_Reg(Src0)));
   EXPECT_TRUE(match);
@@ -433,7 +433,7 @@
   LLT PtrTy = LLT::pointer(0, 64);
   auto MIBIntToPtr = B.buildCast(PtrTy, Copies[0]);
   auto MIBPtrToInt = B.buildCast(s64, MIBIntToPtr);
-  unsigned Src0;
+  Register Src0;
 
   // match the ptrtoint(inttoptr reg)
   bool match = mi_match(MIBPtrToInt->getOperand(0).getReg(), MRI,
@@ -459,7 +459,7 @@
   LLT s64 = LLT::scalar(64);
   LLT s32 = LLT::scalar(32);
   auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
-  unsigned Src0, Src1;
+  Register Src0, Src1;
   bool match =
       mi_match(MIBAdd->getOperand(0).getReg(), MRI,
                m_all_of(m_SpecificType(s64), m_GAdd(m_Reg(Src0), m_Reg(Src1))));