| Krzysztof Parzyszek | 046090d | 2018-03-12 14:01:28 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=hexagon -enable-pipeliner < %s |
| 2 | ; REQUIRES: asserts |
| 3 | |
| 4 | ; Test that the pipeliner doesn't ICE in the ScheduleDAG code because |
| 5 | ; the latency values are not updated properly. The pipeliner should |
| 6 | ; not change the latency of chain edges. |
| 7 | |
| 8 | ; Function Attrs: nounwind |
| 9 | define void @f0() #0 { |
| 10 | b0: |
| 11 | %v0 = alloca [10 x i16], align 8 |
| 12 | br label %b1 |
| 13 | |
| 14 | b1: ; preds = %b1, %b0 |
| 15 | %v1 = phi i32 [ %v7, %b1 ], [ undef, %b0 ] |
| 16 | %v2 = add i32 %v1, -1 |
| 17 | %v3 = getelementptr inbounds [10 x i16], [10 x i16]* %v0, i32 0, i32 %v2 |
| 18 | %v4 = add i32 %v1, -2 |
| 19 | %v5 = getelementptr inbounds [10 x i16], [10 x i16]* %v0, i32 0, i32 %v4 |
| 20 | %v6 = load i16, i16* %v5, align 2, !tbaa !0 |
| 21 | store i16 %v6, i16* %v3, align 2, !tbaa !0 |
| 22 | %v7 = add i32 %v1, -4 |
| 23 | %v8 = icmp sgt i32 %v7, 3 |
| 24 | br i1 %v8, label %b1, label %b2 |
| 25 | |
| 26 | b2: ; preds = %b2, %b1 |
| 27 | br label %b2 |
| 28 | } |
| 29 | |
| 30 | attributes #0 = { nounwind "target-cpu"="hexagonv55" } |
| 31 | |
| 32 | !0 = !{!1, !1, i64 0} |
| 33 | !1 = !{!"short", !2, i64 0} |
| 34 | !2 = !{!"omnipotent char", !3, i64 0} |
| 35 | !3 = !{!"Simple C/C++ TBAA"} |