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gerrit-public.fairphone.software / toolchain / llvm-project / 00bb397b0dc79fcad27bfe63456a2100039706f2 / . / llvm / test / CodeGen / Thumb2 / mve-div-expand.ll
blob: ef804cb3bc54222545f41fbe5610e1fec907d642 [file] [log] [blame]
David Greenfc410242019-06-28 08:18:55 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
David Greeneecba952020-04-22 16:33:11 +0100[diff] [blame]2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
3; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
David Greenfc410242019-06-28 08:18:55 +0000[diff] [blame]4
5define arm_aapcs_vfpcc <4 x i32> @udiv_i32(<4 x i32> %in1, <4 x i32> %in2) {
6; CHECK-LABEL: udiv_i32:
7; CHECK: @ %bb.0: @ %entry
8; CHECK-NEXT: vmov r0, s4
9; CHECK-NEXT: vmov r1, s0
10; CHECK-NEXT: udiv r0, r1, r0
11; CHECK-NEXT: vmov r1, s5
12; CHECK-NEXT: vmov r2, s1
13; CHECK-NEXT: vmov.32 q2[0], r0
14; CHECK-NEXT: udiv r1, r2, r1
15; CHECK-NEXT: vmov r0, s6
16; CHECK-NEXT: vmov.32 q2[1], r1
17; CHECK-NEXT: vmov r1, s2
18; CHECK-NEXT: udiv r0, r1, r0
19; CHECK-NEXT: vmov r1, s3
20; CHECK-NEXT: vmov.32 q2[2], r0
21; CHECK-NEXT: vmov r0, s7
22; CHECK-NEXT: udiv r0, r1, r0
23; CHECK-NEXT: vmov.32 q2[3], r0
24; CHECK-NEXT: vmov q0, q2
25; CHECK-NEXT: bx lr
26entry:
27 %out = udiv <4 x i32> %in1, %in2
28 ret <4 x i32> %out
29}
30
31define arm_aapcs_vfpcc <4 x i32> @sdiv_i32(<4 x i32> %in1, <4 x i32> %in2) {
32; CHECK-LABEL: sdiv_i32:
33; CHECK: @ %bb.0: @ %entry
34; CHECK-NEXT: vmov r0, s4
35; CHECK-NEXT: vmov r1, s0
36; CHECK-NEXT: sdiv r0, r1, r0
37; CHECK-NEXT: vmov r1, s5
38; CHECK-NEXT: vmov r2, s1
39; CHECK-NEXT: vmov.32 q2[0], r0
40; CHECK-NEXT: sdiv r1, r2, r1
41; CHECK-NEXT: vmov r0, s6
42; CHECK-NEXT: vmov.32 q2[1], r1
43; CHECK-NEXT: vmov r1, s2
44; CHECK-NEXT: sdiv r0, r1, r0
45; CHECK-NEXT: vmov r1, s3
46; CHECK-NEXT: vmov.32 q2[2], r0
47; CHECK-NEXT: vmov r0, s7
48; CHECK-NEXT: sdiv r0, r1, r0
49; CHECK-NEXT: vmov.32 q2[3], r0
50; CHECK-NEXT: vmov q0, q2
51; CHECK-NEXT: bx lr
52entry:
53 %out = sdiv <4 x i32> %in1, %in2
54 ret <4 x i32> %out
55}
56
57define arm_aapcs_vfpcc <4 x i32> @urem_i32(<4 x i32> %in1, <4 x i32> %in2) {
58; CHECK-LABEL: urem_i32:
59; CHECK: @ %bb.0: @ %entry
60; CHECK-NEXT: .save {r7, lr}
61; CHECK-NEXT: push {r7, lr}
62; CHECK-NEXT: vmov r0, s4
63; CHECK-NEXT: vmov r1, s0
64; CHECK-NEXT: udiv r2, r1, r0
65; CHECK-NEXT: mls r12, r2, r0, r1
66; CHECK-NEXT: vmov r1, s5
67; CHECK-NEXT: vmov r2, s1
68; CHECK-NEXT: udiv r3, r2, r1
69; CHECK-NEXT: mls lr, r3, r1, r2
70; CHECK-NEXT: vmov r2, s6
71; CHECK-NEXT: vmov r3, s2
72; CHECK-NEXT: udiv r0, r3, r2
73; CHECK-NEXT: mls r0, r0, r2, r3
74; CHECK-NEXT: vmov r2, s7
75; CHECK-NEXT: vmov r3, s3
76; CHECK-NEXT: vmov.32 q0[0], r12
77; CHECK-NEXT: udiv r1, r3, r2
78; CHECK-NEXT: vmov.32 q0[1], lr
79; CHECK-NEXT: vmov.32 q0[2], r0
80; CHECK-NEXT: mls r1, r1, r2, r3
81; CHECK-NEXT: vmov.32 q0[3], r1
82; CHECK-NEXT: pop {r7, pc}
83entry:
84 %out = urem <4 x i32> %in1, %in2
85 ret <4 x i32> %out
86}
87
88define arm_aapcs_vfpcc <4 x i32> @srem_i32(<4 x i32> %in1, <4 x i32> %in2) {
89; CHECK-LABEL: srem_i32:
90; CHECK: @ %bb.0: @ %entry
91; CHECK-NEXT: .save {r7, lr}
92; CHECK-NEXT: push {r7, lr}
93; CHECK-NEXT: vmov r0, s4
94; CHECK-NEXT: vmov r1, s0
95; CHECK-NEXT: sdiv r2, r1, r0
96; CHECK-NEXT: mls r12, r2, r0, r1
97; CHECK-NEXT: vmov r1, s5
98; CHECK-NEXT: vmov r2, s1
99; CHECK-NEXT: sdiv r3, r2, r1
100; CHECK-NEXT: mls lr, r3, r1, r2
101; CHECK-NEXT: vmov r2, s6
102; CHECK-NEXT: vmov r3, s2
103; CHECK-NEXT: sdiv r0, r3, r2
104; CHECK-NEXT: mls r0, r0, r2, r3
105; CHECK-NEXT: vmov r2, s7
106; CHECK-NEXT: vmov r3, s3
107; CHECK-NEXT: vmov.32 q0[0], r12
108; CHECK-NEXT: sdiv r1, r3, r2
109; CHECK-NEXT: vmov.32 q0[1], lr
110; CHECK-NEXT: vmov.32 q0[2], r0
111; CHECK-NEXT: mls r1, r1, r2, r3
112; CHECK-NEXT: vmov.32 q0[3], r1
113; CHECK-NEXT: pop {r7, pc}
114entry:
115 %out = srem <4 x i32> %in1, %in2
116 ret <4 x i32> %out
117}
118
119
120define arm_aapcs_vfpcc <8 x i16> @udiv_i16(<8 x i16> %in1, <8 x i16> %in2) {
121; CHECK-LABEL: udiv_i16:
122; CHECK: @ %bb.0: @ %entry
123; CHECK-NEXT: vmov.u16 r0, q1[0]
124; CHECK-NEXT: vmov.u16 r1, q0[0]
125; CHECK-NEXT: udiv r0, r1, r0
126; CHECK-NEXT: vmov.u16 r1, q1[1]
127; CHECK-NEXT: vmov.u16 r2, q0[1]
128; CHECK-NEXT: vmov.16 q2[0], r0
129; CHECK-NEXT: udiv r1, r2, r1
130; CHECK-NEXT: vmov.u16 r0, q1[2]
131; CHECK-NEXT: vmov.16 q2[1], r1
132; CHECK-NEXT: vmov.u16 r1, q0[2]
133; CHECK-NEXT: udiv r0, r1, r0
134; CHECK-NEXT: vmov.u16 r1, q0[3]
135; CHECK-NEXT: vmov.16 q2[2], r0
136; CHECK-NEXT: vmov.u16 r0, q1[3]
137; CHECK-NEXT: udiv r0, r1, r0
138; CHECK-NEXT: vmov.u16 r1, q0[4]
139; CHECK-NEXT: vmov.16 q2[3], r0
140; CHECK-NEXT: vmov.u16 r0, q1[4]
141; CHECK-NEXT: udiv r0, r1, r0
142; CHECK-NEXT: vmov.u16 r1, q0[5]
143; CHECK-NEXT: vmov.16 q2[4], r0
144; CHECK-NEXT: vmov.u16 r0, q1[5]
145; CHECK-NEXT: udiv r0, r1, r0
146; CHECK-NEXT: vmov.u16 r1, q0[6]
147; CHECK-NEXT: vmov.16 q2[5], r0
148; CHECK-NEXT: vmov.u16 r0, q1[6]
149; CHECK-NEXT: udiv r0, r1, r0
150; CHECK-NEXT: vmov.u16 r1, q0[7]
151; CHECK-NEXT: vmov.16 q2[6], r0
152; CHECK-NEXT: vmov.u16 r0, q1[7]
153; CHECK-NEXT: udiv r0, r1, r0
154; CHECK-NEXT: vmov.16 q2[7], r0
155; CHECK-NEXT: vmov q0, q2
156; CHECK-NEXT: bx lr
157entry:
158 %out = udiv <8 x i16> %in1, %in2
159 ret <8 x i16> %out
160}
161
162define arm_aapcs_vfpcc <8 x i16> @sdiv_i16(<8 x i16> %in1, <8 x i16> %in2) {
163; CHECK-LABEL: sdiv_i16:
164; CHECK: @ %bb.0: @ %entry
165; CHECK-NEXT: .save {r4, r5, r6, lr}
166; CHECK-NEXT: push {r4, r5, r6, lr}
167; CHECK-NEXT: vmov.u16 r0, q1[3]
168; CHECK-NEXT: vmov.u16 r1, q0[3]
169; CHECK-NEXT: sxth r0, r0
170; CHECK-NEXT: sxth r1, r1
171; CHECK-NEXT: vmov.u16 r2, q0[2]
172; CHECK-NEXT: sdiv r12, r1, r0
173; CHECK-NEXT: vmov.u16 r1, q1[2]
174; CHECK-NEXT: sxth r2, r2
175; CHECK-NEXT: sxth r1, r1
176; CHECK-NEXT: vmov.u16 r4, q1[6]
177; CHECK-NEXT: sdiv r3, r2, r1
178; CHECK-NEXT: vmov.u16 r1, q1[1]
179; CHECK-NEXT: vmov.u16 r2, q0[1]
180; CHECK-NEXT: sxth r1, r1
181; CHECK-NEXT: sxth r2, r2
182; CHECK-NEXT: vmov.u16 r5, q0[6]
183; CHECK-NEXT: sdiv r0, r2, r1
184; CHECK-NEXT: vmov.u16 r1, q1[0]
185; CHECK-NEXT: vmov.u16 r2, q0[0]
186; CHECK-NEXT: sxth r1, r1
187; CHECK-NEXT: sxth r2, r2
188; CHECK-NEXT: sxth r4, r4
189; CHECK-NEXT: sdiv r1, r2, r1
190; CHECK-NEXT: vmov.u16 r2, q1[7]
191; CHECK-NEXT: vmov.16 q2[0], r1
192; CHECK-NEXT: sxth.w lr, r2
193; CHECK-NEXT: vmov.16 q2[1], r0
194; CHECK-NEXT: vmov.u16 r2, q0[7]
195; CHECK-NEXT: vmov.16 q2[2], r3
196; CHECK-NEXT: vmov.u16 r3, q1[4]
197; CHECK-NEXT: sxth r6, r2
198; CHECK-NEXT: vmov.u16 r2, q0[4]
199; CHECK-NEXT: vmov.u16 r1, q1[5]
200; CHECK-NEXT: vmov.u16 r0, q0[5]
201; CHECK-NEXT: sxth r3, r3
202; CHECK-NEXT: sxth r2, r2
203; CHECK-NEXT: sxth r1, r1
204; CHECK-NEXT: sxth r0, r0
205; CHECK-NEXT: vmov.16 q2[3], r12
206; CHECK-NEXT: sdiv r2, r2, r3
207; CHECK-NEXT: sxth r5, r5
208; CHECK-NEXT: vmov.16 q2[4], r2
209; CHECK-NEXT: sdiv r0, r0, r1
210; CHECK-NEXT: vmov.16 q2[5], r0
211; CHECK-NEXT: sdiv r0, r5, r4
212; CHECK-NEXT: vmov.16 q2[6], r0
213; CHECK-NEXT: sdiv r0, r6, lr
214; CHECK-NEXT: vmov.16 q2[7], r0
215; CHECK-NEXT: vmov q0, q2
216; CHECK-NEXT: pop {r4, r5, r6, pc}
217entry:
218 %out = sdiv <8 x i16> %in1, %in2
219 ret <8 x i16> %out
220}
221
222define arm_aapcs_vfpcc <8 x i16> @urem_i16(<8 x i16> %in1, <8 x i16> %in2) {
223; CHECK-LABEL: urem_i16:
224; CHECK: @ %bb.0: @ %entry
225; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
226; CHECK-NEXT: push {r4, r5, r6, r7, lr}
227; CHECK-NEXT: vmov.u16 r0, q1[6]
228; CHECK-NEXT: vmov.u16 r1, q0[6]
229; CHECK-NEXT: udiv r2, r1, r0
230; CHECK-NEXT: mls r12, r2, r0, r1
231; CHECK-NEXT: vmov.u16 r1, q1[7]
232; CHECK-NEXT: vmov.u16 r2, q0[7]
233; CHECK-NEXT: udiv r3, r2, r1
234; CHECK-NEXT: mls lr, r3, r1, r2
235; CHECK-NEXT: vmov.u16 r2, q1[4]
236; CHECK-NEXT: vmov.u16 r3, q0[4]
237; CHECK-NEXT: udiv r0, r3, r2
238; CHECK-NEXT: mls r2, r0, r2, r3
239; CHECK-NEXT: vmov.u16 r0, q1[5]
240; CHECK-NEXT: vmov.u16 r3, q0[5]
241; CHECK-NEXT: udiv r1, r3, r0
242; CHECK-NEXT: mls r0, r1, r0, r3
243; CHECK-NEXT: vmov.u16 r1, q1[2]
244; CHECK-NEXT: vmov.u16 r3, q0[2]
245; CHECK-NEXT: udiv r4, r3, r1
246; CHECK-NEXT: mls r1, r4, r1, r3
247; CHECK-NEXT: vmov.u16 r3, q1[3]
248; CHECK-NEXT: vmov.u16 r4, q0[3]
249; CHECK-NEXT: udiv r5, r4, r3
250; CHECK-NEXT: mls r3, r5, r3, r4
251; CHECK-NEXT: vmov.u16 r4, q1[0]
252; CHECK-NEXT: vmov.u16 r5, q0[0]
253; CHECK-NEXT: udiv r6, r5, r4
254; CHECK-NEXT: mls r4, r6, r4, r5
255; CHECK-NEXT: vmov.u16 r6, q0[1]
256; CHECK-NEXT: vmov.u16 r5, q1[1]
257; CHECK-NEXT: udiv r7, r6, r5
258; CHECK-NEXT: vmov.16 q0[0], r4
259; CHECK-NEXT: mls r5, r7, r5, r6
260; CHECK-NEXT: vmov.16 q0[1], r5
261; CHECK-NEXT: vmov.16 q0[2], r1
262; CHECK-NEXT: vmov.16 q0[3], r3
263; CHECK-NEXT: vmov.16 q0[4], r2
264; CHECK-NEXT: vmov.16 q0[5], r0
265; CHECK-NEXT: vmov.16 q0[6], r12
266; CHECK-NEXT: vmov.16 q0[7], lr
267; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
268entry:
269 %out = urem <8 x i16> %in1, %in2
270 ret <8 x i16> %out
271}
272
273define arm_aapcs_vfpcc <8 x i16> @srem_i16(<8 x i16> %in1, <8 x i16> %in2) {
274; CHECK-LABEL: srem_i16:
275; CHECK: @ %bb.0: @ %entry
276; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
277; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
278; CHECK-NEXT: vmov.u16 r5, q1[6]
279; CHECK-NEXT: vmov.u16 r6, q0[6]
280; CHECK-NEXT: sxth r5, r5
281; CHECK-NEXT: sxth r6, r6
282; CHECK-NEXT: vmov.u16 r0, q1[0]
283; CHECK-NEXT: sdiv r7, r6, r5
284; CHECK-NEXT: vmov.u16 r2, q1[7]
285; CHECK-NEXT: sxth.w r8, r0
286; CHECK-NEXT: vmov.u16 r0, q1[3]
287; CHECK-NEXT: mls r12, r7, r5, r6
288; CHECK-NEXT: vmov.u16 r7, q0[7]
289; CHECK-NEXT: sxth r3, r0
290; CHECK-NEXT: vmov.u16 r0, q1[2]
291; CHECK-NEXT: sxth r2, r2
292; CHECK-NEXT: sxth r7, r7
293; CHECK-NEXT: sxth r4, r0
294; CHECK-NEXT: vmov.u16 r0, q1[5]
295; CHECK-NEXT: sdiv r6, r7, r2
296; CHECK-NEXT: mls lr, r6, r2, r7
297; CHECK-NEXT: vmov.u16 r2, q0[4]
298; CHECK-NEXT: sxth r1, r0
299; CHECK-NEXT: vmov.u16 r0, q1[4]
300; CHECK-NEXT: sxth r0, r0
301; CHECK-NEXT: sxth r2, r2
302; CHECK-NEXT: sdiv r5, r2, r0
303; CHECK-NEXT: vmov.u16 r6, q0[1]
304; CHECK-NEXT: mls r0, r5, r0, r2
305; CHECK-NEXT: vmov.u16 r2, q0[5]
306; CHECK-NEXT: sxth r2, r2
307; CHECK-NEXT: sdiv r5, r2, r1
308; CHECK-NEXT: sxth r6, r6
309; CHECK-NEXT: mls r1, r5, r1, r2
310; CHECK-NEXT: vmov.u16 r2, q0[2]
311; CHECK-NEXT: sxth r2, r2
312; CHECK-NEXT: sdiv r5, r2, r4
313; CHECK-NEXT: mls r2, r5, r4, r2
314; CHECK-NEXT: vmov.u16 r4, q0[3]
315; CHECK-NEXT: sxth r4, r4
316; CHECK-NEXT: sdiv r5, r4, r3
317; CHECK-NEXT: mls r3, r5, r3, r4
318; CHECK-NEXT: vmov.u16 r4, q0[0]
319; CHECK-NEXT: sxth r4, r4
320; CHECK-NEXT: sdiv r5, r4, r8
321; CHECK-NEXT: mls r4, r5, r8, r4
322; CHECK-NEXT: vmov.u16 r5, q1[1]
323; CHECK-NEXT: sxth r5, r5
324; CHECK-NEXT: sdiv r7, r6, r5
325; CHECK-NEXT: vmov.16 q0[0], r4
326; CHECK-NEXT: mls r5, r7, r5, r6
327; CHECK-NEXT: vmov.16 q0[1], r5
328; CHECK-NEXT: vmov.16 q0[2], r2
329; CHECK-NEXT: vmov.16 q0[3], r3
330; CHECK-NEXT: vmov.16 q0[4], r0
331; CHECK-NEXT: vmov.16 q0[5], r1
332; CHECK-NEXT: vmov.16 q0[6], r12
333; CHECK-NEXT: vmov.16 q0[7], lr
334; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
335entry:
336 %out = srem <8 x i16> %in1, %in2
337 ret <8 x i16> %out
338}
339
340
341define arm_aapcs_vfpcc <16 x i8> @udiv_i8(<16 x i8> %in1, <16 x i8> %in2) {
342; CHECK-LABEL: udiv_i8:
343; CHECK: @ %bb.0: @ %entry
344; CHECK-NEXT: vmov.u8 r0, q1[0]
345; CHECK-NEXT: vmov.u8 r1, q0[0]
346; CHECK-NEXT: udiv r0, r1, r0
347; CHECK-NEXT: vmov.u8 r1, q1[1]
348; CHECK-NEXT: vmov.u8 r2, q0[1]
349; CHECK-NEXT: vmov.8 q2[0], r0
350; CHECK-NEXT: udiv r1, r2, r1
351; CHECK-NEXT: vmov.u8 r0, q1[2]
352; CHECK-NEXT: vmov.8 q2[1], r1
353; CHECK-NEXT: vmov.u8 r1, q0[2]
354; CHECK-NEXT: udiv r0, r1, r0
355; CHECK-NEXT: vmov.u8 r1, q0[3]
356; CHECK-NEXT: vmov.8 q2[2], r0
357; CHECK-NEXT: vmov.u8 r0, q1[3]
358; CHECK-NEXT: udiv r0, r1, r0
359; CHECK-NEXT: vmov.u8 r1, q0[4]
360; CHECK-NEXT: vmov.8 q2[3], r0
361; CHECK-NEXT: vmov.u8 r0, q1[4]
362; CHECK-NEXT: udiv r0, r1, r0
363; CHECK-NEXT: vmov.u8 r1, q0[5]
364; CHECK-NEXT: vmov.8 q2[4], r0
365; CHECK-NEXT: vmov.u8 r0, q1[5]
366; CHECK-NEXT: udiv r0, r1, r0
367; CHECK-NEXT: vmov.u8 r1, q0[6]
368; CHECK-NEXT: vmov.8 q2[5], r0
369; CHECK-NEXT: vmov.u8 r0, q1[6]
370; CHECK-NEXT: udiv r0, r1, r0
371; CHECK-NEXT: vmov.u8 r1, q0[7]
372; CHECK-NEXT: vmov.8 q2[6], r0
373; CHECK-NEXT: vmov.u8 r0, q1[7]
374; CHECK-NEXT: udiv r0, r1, r0
375; CHECK-NEXT: vmov.u8 r1, q0[8]
376; CHECK-NEXT: vmov.8 q2[7], r0
377; CHECK-NEXT: vmov.u8 r0, q1[8]
378; CHECK-NEXT: udiv r0, r1, r0
379; CHECK-NEXT: vmov.u8 r1, q0[9]
380; CHECK-NEXT: vmov.8 q2[8], r0
381; CHECK-NEXT: vmov.u8 r0, q1[9]
382; CHECK-NEXT: udiv r0, r1, r0
383; CHECK-NEXT: vmov.u8 r1, q0[10]
384; CHECK-NEXT: vmov.8 q2[9], r0
385; CHECK-NEXT: vmov.u8 r0, q1[10]
386; CHECK-NEXT: udiv r0, r1, r0
387; CHECK-NEXT: vmov.u8 r1, q0[11]
388; CHECK-NEXT: vmov.8 q2[10], r0
389; CHECK-NEXT: vmov.u8 r0, q1[11]
390; CHECK-NEXT: udiv r0, r1, r0
391; CHECK-NEXT: vmov.u8 r1, q0[12]
392; CHECK-NEXT: vmov.8 q2[11], r0
393; CHECK-NEXT: vmov.u8 r0, q1[12]
394; CHECK-NEXT: udiv r0, r1, r0
395; CHECK-NEXT: vmov.u8 r1, q0[13]
396; CHECK-NEXT: vmov.8 q2[12], r0
397; CHECK-NEXT: vmov.u8 r0, q1[13]
398; CHECK-NEXT: udiv r0, r1, r0
399; CHECK-NEXT: vmov.u8 r1, q0[14]
400; CHECK-NEXT: vmov.8 q2[13], r0
401; CHECK-NEXT: vmov.u8 r0, q1[14]
402; CHECK-NEXT: udiv r0, r1, r0
403; CHECK-NEXT: vmov.u8 r1, q0[15]
404; CHECK-NEXT: vmov.8 q2[14], r0
405; CHECK-NEXT: vmov.u8 r0, q1[15]
406; CHECK-NEXT: udiv r0, r1, r0
407; CHECK-NEXT: vmov.8 q2[15], r0
408; CHECK-NEXT: vmov q0, q2
409; CHECK-NEXT: bx lr
410entry:
411 %out = udiv <16 x i8> %in1, %in2
412 ret <16 x i8> %out
413}
414
415define arm_aapcs_vfpcc <16 x i8> @sdiv_i8(<16 x i8> %in1, <16 x i8> %in2) {
416; CHECK-LABEL: sdiv_i8:
417; CHECK: @ %bb.0: @ %entry
418; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
419; CHECK-NEXT: push {r4, r5, r6, r7, lr}
420; CHECK-NEXT: vmov.u8 r0, q1[1]
421; CHECK-NEXT: vmov.u8 r1, q0[1]
422; CHECK-NEXT: sxtb r0, r0
423; CHECK-NEXT: sxtb r1, r1
424; CHECK-NEXT: vmov.u8 r2, q0[0]
425; CHECK-NEXT: sdiv r0, r1, r0
426; CHECK-NEXT: vmov.u8 r1, q1[0]
427; CHECK-NEXT: sxtb r2, r2
428; CHECK-NEXT: sxtb r1, r1
429; CHECK-NEXT: vmov.u8 r4, q1[3]
430; CHECK-NEXT: sdiv r1, r2, r1
431; CHECK-NEXT: vmov.u8 r5, q0[3]
432; CHECK-NEXT: vmov.8 q2[0], r1
433; CHECK-NEXT: vmov.u8 r1, q1[2]
434; CHECK-NEXT: vmov.8 q2[1], r0
435; CHECK-NEXT: vmov.u8 r0, q0[2]
436; CHECK-NEXT: vmov.u8 r2, q1[11]
437; CHECK-NEXT: vmov.u8 r3, q0[11]
438; CHECK-NEXT: sxtb r1, r1
439; CHECK-NEXT: sxtb r0, r0
440; CHECK-NEXT: sdiv r0, r0, r1
441; CHECK-NEXT: sxtb.w r12, r2
442; CHECK-NEXT: sxtb.w lr, r3
443; CHECK-NEXT: vmov.u8 r2, q1[4]
444; CHECK-NEXT: vmov.u8 r3, q0[4]
445; CHECK-NEXT: sxtb r4, r4
446; CHECK-NEXT: sxtb r5, r5
447; CHECK-NEXT: vmov.8 q2[2], r0
448; CHECK-NEXT: sdiv r0, r5, r4
449; CHECK-NEXT: sxtb r2, r2
450; CHECK-NEXT: sxtb r3, r3
451; CHECK-NEXT: vmov.8 q2[3], r0
452; CHECK-NEXT: sdiv r0, r3, r2
453; CHECK-NEXT: vmov.u8 r1, q0[10]
454; CHECK-NEXT: vmov.8 q2[4], r0
455; CHECK-NEXT: vmov.u8 r0, q1[10]
456; CHECK-NEXT: sxtb r0, r0
457; CHECK-NEXT: sxtb r1, r1
458; CHECK-NEXT: sdiv r12, lr, r12
459; CHECK-NEXT: sdiv lr, r1, r0
460; CHECK-NEXT: vmov.u8 r0, q1[9]
461; CHECK-NEXT: vmov.u8 r1, q0[9]
462; CHECK-NEXT: sxtb r0, r0
463; CHECK-NEXT: sxtb r1, r1
464; CHECK-NEXT: sdiv r2, r1, r0
465; CHECK-NEXT: vmov.u8 r0, q1[8]
466; CHECK-NEXT: vmov.u8 r1, q0[8]
467; CHECK-NEXT: sxtb r0, r0
468; CHECK-NEXT: sxtb r1, r1
469; CHECK-NEXT: vmov.u8 r3, q0[7]
470; CHECK-NEXT: sdiv r1, r1, r0
471; CHECK-NEXT: vmov.u8 r0, q1[7]
472; CHECK-NEXT: sxtb r0, r0
473; CHECK-NEXT: sxtb r3, r3
474; CHECK-NEXT: sdiv r4, r3, r0
475; CHECK-NEXT: vmov.u8 r0, q1[6]
476; CHECK-NEXT: vmov.u8 r3, q0[6]
477; CHECK-NEXT: sxtb r0, r0
478; CHECK-NEXT: sxtb r3, r3
479; CHECK-NEXT: vmov.u8 r6, q0[12]
480; CHECK-NEXT: sdiv r5, r3, r0
481; CHECK-NEXT: vmov.u8 r0, q1[5]
482; CHECK-NEXT: vmov.u8 r3, q0[5]
483; CHECK-NEXT: sxtb r0, r0
484; CHECK-NEXT: sxtb r3, r3
485; CHECK-NEXT: sxtb r6, r6
486; CHECK-NEXT: sdiv r0, r3, r0
487; CHECK-NEXT: vmov.u8 r3, q1[15]
488; CHECK-NEXT: vmov.8 q2[5], r0
489; CHECK-NEXT: sxtb r7, r3
490; CHECK-NEXT: vmov.8 q2[6], r5
491; CHECK-NEXT: vmov.u8 r3, q1[12]
492; CHECK-NEXT: vmov.8 q2[7], r4
493; CHECK-NEXT: sxtb r3, r3
494; CHECK-NEXT: vmov.8 q2[8], r1
495; CHECK-NEXT: vmov.u8 r1, q1[13]
496; CHECK-NEXT: vmov.8 q2[9], r2
497; CHECK-NEXT: vmov.u8 r2, q0[13]
498; CHECK-NEXT: vmov.8 q2[10], lr
499; CHECK-NEXT: vmov.u8 r5, q1[14]
500; CHECK-NEXT: vmov.u8 r4, q0[14]
501; CHECK-NEXT: sxtb r1, r1
502; CHECK-NEXT: sxtb r2, r2
503; CHECK-NEXT: vmov.8 q2[11], r12
504; CHECK-NEXT: sdiv r3, r6, r3
505; CHECK-NEXT: vmov.u8 r0, q0[15]
506; CHECK-NEXT: sxtb r5, r5
507; CHECK-NEXT: sxtb r4, r4
508; CHECK-NEXT: vmov.8 q2[12], r3
509; CHECK-NEXT: sdiv r1, r2, r1
510; CHECK-NEXT: sxtb r0, r0
511; CHECK-NEXT: vmov.8 q2[13], r1
512; CHECK-NEXT: sdiv r1, r4, r5
513; CHECK-NEXT: sdiv r0, r0, r7
514; CHECK-NEXT: vmov.8 q2[14], r1
515; CHECK-NEXT: vmov.8 q2[15], r0
516; CHECK-NEXT: vmov q0, q2
517; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
518entry:
519 %out = sdiv <16 x i8> %in1, %in2
520 ret <16 x i8> %out
521}
522
523define arm_aapcs_vfpcc <16 x i8> @urem_i8(<16 x i8> %in1, <16 x i8> %in2) {
524; CHECK-LABEL: urem_i8:
525; CHECK: @ %bb.0: @ %entry
526; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
527; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
528; CHECK-NEXT: vmov.u8 r0, q1[14]
529; CHECK-NEXT: vmov.u8 r1, q0[14]
530; CHECK-NEXT: udiv r2, r1, r0
531; CHECK-NEXT: mls r12, r2, r0, r1
532; CHECK-NEXT: vmov.u8 r0, q1[15]
533; CHECK-NEXT: vmov.u8 r1, q0[15]
534; CHECK-NEXT: udiv r2, r1, r0
535; CHECK-NEXT: mls lr, r2, r0, r1
536; CHECK-NEXT: vmov.u8 r0, q1[12]
537; CHECK-NEXT: vmov.u8 r1, q0[12]
538; CHECK-NEXT: udiv r2, r1, r0
539; CHECK-NEXT: mls r8, r2, r0, r1
540; CHECK-NEXT: vmov.u8 r0, q1[13]
541; CHECK-NEXT: vmov.u8 r1, q0[13]
542; CHECK-NEXT: udiv r3, r1, r0
543; CHECK-NEXT: mls r3, r3, r0, r1
544; CHECK-NEXT: vmov.u8 r0, q1[10]
545; CHECK-NEXT: vmov.u8 r1, q0[10]
546; CHECK-NEXT: udiv r4, r1, r0
547; CHECK-NEXT: mls r0, r4, r0, r1
548; CHECK-NEXT: vmov.u8 r1, q1[11]
549; CHECK-NEXT: vmov.u8 r4, q0[11]
550; CHECK-NEXT: udiv r5, r4, r1
551; CHECK-NEXT: mls r1, r5, r1, r4
552; CHECK-NEXT: vmov.u8 r4, q1[8]
553; CHECK-NEXT: vmov.u8 r5, q0[8]
554; CHECK-NEXT: udiv r6, r5, r4
555; CHECK-NEXT: mls r4, r6, r4, r5
556; CHECK-NEXT: vmov.u8 r5, q1[0]
557; CHECK-NEXT: vmov.u8 r6, q0[0]
558; CHECK-NEXT: udiv r7, r6, r5
559; CHECK-NEXT: mls r5, r7, r5, r6
560; CHECK-NEXT: vmov.u8 r6, q1[1]
561; CHECK-NEXT: vmov.u8 r7, q0[1]
562; CHECK-NEXT: udiv r2, r7, r6
563; CHECK-NEXT: vmov.8 q2[0], r5
564; CHECK-NEXT: mls r2, r2, r6, r7
565; CHECK-NEXT: vmov.u8 r5, q0[2]
566; CHECK-NEXT: vmov.8 q2[1], r2
567; CHECK-NEXT: vmov.u8 r2, q1[2]
568; CHECK-NEXT: udiv r6, r5, r2
569; CHECK-NEXT: mls r2, r6, r2, r5
570; CHECK-NEXT: vmov.u8 r5, q0[3]
571; CHECK-NEXT: vmov.8 q2[2], r2
572; CHECK-NEXT: vmov.u8 r2, q1[3]
573; CHECK-NEXT: udiv r6, r5, r2
574; CHECK-NEXT: mls r2, r6, r2, r5
575; CHECK-NEXT: vmov.u8 r5, q0[4]
576; CHECK-NEXT: vmov.8 q2[3], r2
577; CHECK-NEXT: vmov.u8 r2, q1[4]
578; CHECK-NEXT: udiv r6, r5, r2
579; CHECK-NEXT: mls r2, r6, r2, r5
580; CHECK-NEXT: vmov.u8 r5, q0[5]
581; CHECK-NEXT: vmov.8 q2[4], r2
582; CHECK-NEXT: vmov.u8 r2, q1[5]
583; CHECK-NEXT: udiv r6, r5, r2
584; CHECK-NEXT: mls r2, r6, r2, r5
585; CHECK-NEXT: vmov.u8 r5, q0[6]
586; CHECK-NEXT: vmov.8 q2[5], r2
587; CHECK-NEXT: vmov.u8 r2, q1[6]
588; CHECK-NEXT: udiv r6, r5, r2
589; CHECK-NEXT: mls r2, r6, r2, r5
590; CHECK-NEXT: vmov.u8 r5, q0[7]
591; CHECK-NEXT: vmov.8 q2[6], r2
592; CHECK-NEXT: vmov.u8 r2, q1[7]
593; CHECK-NEXT: udiv r6, r5, r2
594; CHECK-NEXT: mls r2, r6, r2, r5
595; CHECK-NEXT: vmov.u8 r5, q0[9]
596; CHECK-NEXT: vmov.8 q2[7], r2
597; CHECK-NEXT: vmov.u8 r2, q1[9]
598; CHECK-NEXT: udiv r6, r5, r2
599; CHECK-NEXT: vmov.8 q2[8], r4
600; CHECK-NEXT: mls r2, r6, r2, r5
601; CHECK-NEXT: vmov.8 q2[9], r2
602; CHECK-NEXT: vmov.8 q2[10], r0
603; CHECK-NEXT: vmov.8 q2[11], r1
604; CHECK-NEXT: vmov.8 q2[12], r8
605; CHECK-NEXT: vmov.8 q2[13], r3
606; CHECK-NEXT: vmov.8 q2[14], r12
607; CHECK-NEXT: vmov.8 q2[15], lr
608; CHECK-NEXT: vmov q0, q2
609; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
610entry:
611 %out = urem <16 x i8> %in1, %in2
612 ret <16 x i8> %out
613}
614
615define arm_aapcs_vfpcc <16 x i8> @srem_i8(<16 x i8> %in1, <16 x i8> %in2) {
616; CHECK-LABEL: srem_i8:
617; CHECK: @ %bb.0: @ %entry
618; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
619; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
620; CHECK-NEXT: vmov.u8 r5, q1[14]
621; CHECK-NEXT: vmov.u8 r6, q0[14]
622; CHECK-NEXT: sxtb r5, r5
623; CHECK-NEXT: sxtb r6, r6
624; CHECK-NEXT: sdiv r7, r6, r5
625; CHECK-NEXT: vmov.u8 r4, q1[15]
626; CHECK-NEXT: mls r12, r7, r5, r6
627; CHECK-NEXT: vmov.u8 r7, q0[15]
628; CHECK-NEXT: sxtb r4, r4
629; CHECK-NEXT: vmov.u8 r2, q1[13]
630; CHECK-NEXT: sxtb r7, r7
631; CHECK-NEXT: sxtb r3, r2
632; CHECK-NEXT: sdiv r6, r7, r4
633; CHECK-NEXT: vmov.u8 r2, q1[12]
634; CHECK-NEXT: mls lr, r6, r4, r7
635; CHECK-NEXT: vmov.u8 r4, q0[12]
636; CHECK-NEXT: sxtb r2, r2
637; CHECK-NEXT: vmov.u8 r0, q1[8]
638; CHECK-NEXT: sxtb r4, r4
639; CHECK-NEXT: sxtb.w r8, r0
640; CHECK-NEXT: sdiv r5, r4, r2
641; CHECK-NEXT: vmov.u8 r0, q1[11]
642; CHECK-NEXT: mls r9, r5, r2, r4
643; CHECK-NEXT: vmov.u8 r4, q0[13]
644; CHECK-NEXT: sxtb r4, r4
645; CHECK-NEXT: vmov.u8 r6, q0[0]
646; CHECK-NEXT: sdiv r5, r4, r3
647; CHECK-NEXT: sxtb r1, r0
648; CHECK-NEXT: vmov.u8 r0, q1[10]
649; CHECK-NEXT: mls r3, r5, r3, r4
650; CHECK-NEXT: vmov.u8 r4, q0[10]
651; CHECK-NEXT: sxtb r0, r0
652; CHECK-NEXT: sxtb r4, r4
653; CHECK-NEXT: sxtb r6, r6
654; CHECK-NEXT: sdiv r5, r4, r0
655; CHECK-NEXT: mls r0, r5, r0, r4
656; CHECK-NEXT: vmov.u8 r4, q0[11]
657; CHECK-NEXT: sxtb r4, r4
658; CHECK-NEXT: sdiv r5, r4, r1
659; CHECK-NEXT: mls r1, r5, r1, r4
660; CHECK-NEXT: vmov.u8 r4, q0[8]
661; CHECK-NEXT: sxtb r4, r4
662; CHECK-NEXT: sdiv r5, r4, r8
663; CHECK-NEXT: mls r4, r5, r8, r4
664; CHECK-NEXT: vmov.u8 r5, q1[0]
665; CHECK-NEXT: sxtb r5, r5
666; CHECK-NEXT: sdiv r7, r6, r5
667; CHECK-NEXT: mls r5, r7, r5, r6
668; CHECK-NEXT: vmov.u8 r6, q1[1]
669; CHECK-NEXT: vmov.u8 r7, q0[1]
670; CHECK-NEXT: sxtb r6, r6
671; CHECK-NEXT: sxtb r7, r7
672; CHECK-NEXT: vmov.8 q2[0], r5
673; CHECK-NEXT: sdiv r2, r7, r6
674; CHECK-NEXT: vmov.u8 r5, q0[2]
675; CHECK-NEXT: mls r2, r2, r6, r7
676; CHECK-NEXT: sxtb r5, r5
677; CHECK-NEXT: vmov.8 q2[1], r2
678; CHECK-NEXT: vmov.u8 r2, q1[2]
679; CHECK-NEXT: sxtb r2, r2
680; CHECK-NEXT: sdiv r6, r5, r2
681; CHECK-NEXT: mls r2, r6, r2, r5
682; CHECK-NEXT: vmov.u8 r5, q0[3]
683; CHECK-NEXT: sxtb r5, r5
684; CHECK-NEXT: vmov.8 q2[2], r2
685; CHECK-NEXT: vmov.u8 r2, q1[3]
686; CHECK-NEXT: sxtb r2, r2
687; CHECK-NEXT: sdiv r6, r5, r2
688; CHECK-NEXT: mls r2, r6, r2, r5
689; CHECK-NEXT: vmov.u8 r5, q0[4]
690; CHECK-NEXT: sxtb r5, r5
691; CHECK-NEXT: vmov.8 q2[3], r2
692; CHECK-NEXT: vmov.u8 r2, q1[4]
693; CHECK-NEXT: sxtb r2, r2
694; CHECK-NEXT: sdiv r6, r5, r2
695; CHECK-NEXT: mls r2, r6, r2, r5
696; CHECK-NEXT: vmov.u8 r5, q0[5]
697; CHECK-NEXT: sxtb r5, r5
698; CHECK-NEXT: vmov.8 q2[4], r2
699; CHECK-NEXT: vmov.u8 r2, q1[5]
700; CHECK-NEXT: sxtb r2, r2
701; CHECK-NEXT: sdiv r6, r5, r2
702; CHECK-NEXT: mls r2, r6, r2, r5
703; CHECK-NEXT: vmov.u8 r5, q0[6]
704; CHECK-NEXT: sxtb r5, r5
705; CHECK-NEXT: vmov.8 q2[5], r2
706; CHECK-NEXT: vmov.u8 r2, q1[6]
707; CHECK-NEXT: sxtb r2, r2
708; CHECK-NEXT: sdiv r6, r5, r2
709; CHECK-NEXT: mls r2, r6, r2, r5
710; CHECK-NEXT: vmov.u8 r5, q0[7]
711; CHECK-NEXT: sxtb r5, r5
712; CHECK-NEXT: vmov.8 q2[6], r2
713; CHECK-NEXT: vmov.u8 r2, q1[7]
714; CHECK-NEXT: sxtb r2, r2
715; CHECK-NEXT: sdiv r6, r5, r2
716; CHECK-NEXT: mls r2, r6, r2, r5
717; CHECK-NEXT: vmov.u8 r5, q0[9]
718; CHECK-NEXT: sxtb r5, r5
719; CHECK-NEXT: vmov.8 q2[7], r2
720; CHECK-NEXT: vmov.u8 r2, q1[9]
721; CHECK-NEXT: sxtb r2, r2
722; CHECK-NEXT: vmov.8 q2[8], r4
723; CHECK-NEXT: sdiv r6, r5, r2
724; CHECK-NEXT: mls r2, r6, r2, r5
725; CHECK-NEXT: vmov.8 q2[9], r2
726; CHECK-NEXT: vmov.8 q2[10], r0
727; CHECK-NEXT: vmov.8 q2[11], r1
728; CHECK-NEXT: vmov.8 q2[12], r9
729; CHECK-NEXT: vmov.8 q2[13], r3
730; CHECK-NEXT: vmov.8 q2[14], r12
731; CHECK-NEXT: vmov.8 q2[15], lr
732; CHECK-NEXT: vmov q0, q2
733; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
734entry:
735 %out = srem <16 x i8> %in1, %in2
736 ret <16 x i8> %out
737}
738
David Greendc569952019-07-15 18:42:54 +0000[diff] [blame]739define arm_aapcs_vfpcc <2 x i64> @udiv_i64(<2 x i64> %in1, <2 x i64> %in2) {
740; CHECK-LABEL: udiv_i64:
741; CHECK: @ %bb.0: @ %entry
742; CHECK-NEXT: .save {r7, lr}
743; CHECK-NEXT: push {r7, lr}
744; CHECK-NEXT: .vsave {d8, d9, d10, d11}
745; CHECK-NEXT: vpush {d8, d9, d10, d11}
746; CHECK-NEXT: vmov q4, q1
747; CHECK-NEXT: vmov q5, q0
748; CHECK-NEXT: vmov r0, s20
749; CHECK-NEXT: vmov r1, s21
750; CHECK-NEXT: vmov r2, s16
751; CHECK-NEXT: vmov r3, s17
752; CHECK-NEXT: bl __aeabi_uldivmod
753; CHECK-NEXT: vmov r12, s22
754; CHECK-NEXT: vmov lr, s23
755; CHECK-NEXT: vmov r2, s18
756; CHECK-NEXT: vmov r3, s19
757; CHECK-NEXT: vmov.32 q4[0], r0
Sam Tebbsa69d9d62019-08-22 10:29:20 +0000[diff] [blame]758; CHECK-NEXT: vmov.32 q4[1], r1
David Greendc569952019-07-15 18:42:54 +0000[diff] [blame]759; CHECK-NEXT: mov r0, r12
760; CHECK-NEXT: mov r1, lr
761; CHECK-NEXT: bl __aeabi_uldivmod
762; CHECK-NEXT: vmov.32 q4[2], r0
Sam Tebbsa69d9d62019-08-22 10:29:20 +0000[diff] [blame]763; CHECK-NEXT: vmov.32 q4[3], r1
David Greendc569952019-07-15 18:42:54 +0000[diff] [blame]764; CHECK-NEXT: vmov q0, q4
765; CHECK-NEXT: vpop {d8, d9, d10, d11}
766; CHECK-NEXT: pop {r7, pc}
767entry:
768 %out = udiv <2 x i64> %in1, %in2
769 ret <2 x i64> %out
770}
771
772define arm_aapcs_vfpcc <2 x i64> @sdiv_i64(<2 x i64> %in1, <2 x i64> %in2) {
773; CHECK-LABEL: sdiv_i64:
774; CHECK: @ %bb.0: @ %entry
775; CHECK-NEXT: .save {r7, lr}
776; CHECK-NEXT: push {r7, lr}
777; CHECK-NEXT: .vsave {d8, d9, d10, d11}
778; CHECK-NEXT: vpush {d8, d9, d10, d11}
779; CHECK-NEXT: vmov q4, q1
780; CHECK-NEXT: vmov q5, q0
781; CHECK-NEXT: vmov r0, s20
782; CHECK-NEXT: vmov r1, s21
783; CHECK-NEXT: vmov r2, s16
784; CHECK-NEXT: vmov r3, s17
785; CHECK-NEXT: bl __aeabi_ldivmod
786; CHECK-NEXT: vmov r12, s22
787; CHECK-NEXT: vmov lr, s23
788; CHECK-NEXT: vmov r2, s18
789; CHECK-NEXT: vmov r3, s19
790; CHECK-NEXT: vmov.32 q4[0], r0
Sam Tebbsa69d9d62019-08-22 10:29:20 +0000[diff] [blame]791; CHECK-NEXT: vmov.32 q4[1], r1
David Greendc569952019-07-15 18:42:54 +0000[diff] [blame]792; CHECK-NEXT: mov r0, r12
793; CHECK-NEXT: mov r1, lr
794; CHECK-NEXT: bl __aeabi_ldivmod
795; CHECK-NEXT: vmov.32 q4[2], r0
Sam Tebbsa69d9d62019-08-22 10:29:20 +0000[diff] [blame]796; CHECK-NEXT: vmov.32 q4[3], r1
David Greendc569952019-07-15 18:42:54 +0000[diff] [blame]797; CHECK-NEXT: vmov q0, q4
798; CHECK-NEXT: vpop {d8, d9, d10, d11}
799; CHECK-NEXT: pop {r7, pc}
800entry:
801 %out = sdiv <2 x i64> %in1, %in2
802 ret <2 x i64> %out
803}
804
805define arm_aapcs_vfpcc <2 x i64> @urem_i64(<2 x i64> %in1, <2 x i64> %in2) {
806; CHECK-LABEL: urem_i64:
807; CHECK: @ %bb.0: @ %entry
808; CHECK-NEXT: .save {r7, lr}
809; CHECK-NEXT: push {r7, lr}
810; CHECK-NEXT: .vsave {d8, d9, d10, d11}
811; CHECK-NEXT: vpush {d8, d9, d10, d11}
812; CHECK-NEXT: vmov q4, q1
813; CHECK-NEXT: vmov q5, q0
814; CHECK-NEXT: vmov r0, s20
815; CHECK-NEXT: vmov r1, s21
816; CHECK-NEXT: vmov r2, s16
817; CHECK-NEXT: vmov r3, s17
818; CHECK-NEXT: bl __aeabi_uldivmod
819; CHECK-NEXT: vmov r12, s18
820; CHECK-NEXT: vmov lr, s19
821; CHECK-NEXT: vmov.32 q4[0], r2
822; CHECK-NEXT: vmov r0, s22
823; CHECK-NEXT: vmov.32 q4[1], r3
824; CHECK-NEXT: vmov r1, s23
825; CHECK-NEXT: mov r2, r12
826; CHECK-NEXT: mov r3, lr
827; CHECK-NEXT: bl __aeabi_uldivmod
828; CHECK-NEXT: vmov.32 q4[2], r2
829; CHECK-NEXT: vmov.32 q4[3], r3
830; CHECK-NEXT: vmov q0, q4
831; CHECK-NEXT: vpop {d8, d9, d10, d11}
832; CHECK-NEXT: pop {r7, pc}
833entry:
834 %out = urem <2 x i64> %in1, %in2
835 ret <2 x i64> %out
836}
837
838define arm_aapcs_vfpcc <2 x i64> @srem_i64(<2 x i64> %in1, <2 x i64> %in2) {
839; CHECK-LABEL: srem_i64:
840; CHECK: @ %bb.0: @ %entry
841; CHECK-NEXT: .save {r7, lr}
842; CHECK-NEXT: push {r7, lr}
843; CHECK-NEXT: .vsave {d8, d9, d10, d11}
844; CHECK-NEXT: vpush {d8, d9, d10, d11}
845; CHECK-NEXT: vmov q4, q1
846; CHECK-NEXT: vmov q5, q0
847; CHECK-NEXT: vmov r0, s20
848; CHECK-NEXT: vmov r1, s21
849; CHECK-NEXT: vmov r2, s16
850; CHECK-NEXT: vmov r3, s17
851; CHECK-NEXT: bl __aeabi_ldivmod
852; CHECK-NEXT: vmov r12, s18
853; CHECK-NEXT: vmov lr, s19
854; CHECK-NEXT: vmov.32 q4[0], r2
855; CHECK-NEXT: vmov r0, s22
856; CHECK-NEXT: vmov.32 q4[1], r3
857; CHECK-NEXT: vmov r1, s23
858; CHECK-NEXT: mov r2, r12
859; CHECK-NEXT: mov r3, lr
860; CHECK-NEXT: bl __aeabi_ldivmod
861; CHECK-NEXT: vmov.32 q4[2], r2
862; CHECK-NEXT: vmov.32 q4[3], r3
863; CHECK-NEXT: vmov q0, q4
864; CHECK-NEXT: vpop {d8, d9, d10, d11}
865; CHECK-NEXT: pop {r7, pc}
866entry:
867 %out = srem <2 x i64> %in1, %in2
868 ret <2 x i64> %out
869}
870
871
872
David Greenfc410242019-06-28 08:18:55 +0000[diff] [blame]873
874define arm_aapcs_vfpcc <4 x float> @fdiv_f32(<4 x float> %in1, <4 x float> %in2) {
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]875; CHECK-LABEL: fdiv_f32:
876; CHECK: @ %bb.0: @ %entry
877; CHECK-NEXT: vdiv.f32 s11, s3, s7
878; CHECK-NEXT: vdiv.f32 s10, s2, s6
879; CHECK-NEXT: vdiv.f32 s9, s1, s5
880; CHECK-NEXT: vdiv.f32 s8, s0, s4
881; CHECK-NEXT: vmov q0, q2
882; CHECK-NEXT: bx lr
David Greenfc410242019-06-28 08:18:55 +0000[diff] [blame]883entry:
884 %out = fdiv <4 x float> %in1, %in2
885 ret <4 x float> %out
886}
887
888define arm_aapcs_vfpcc <4 x float> @frem_f32(<4 x float> %in1, <4 x float> %in2) {
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]889; CHECK-LABEL: frem_f32:
890; CHECK: @ %bb.0: @ %entry
891; CHECK-NEXT: .save {r4, r5, r6, lr}
892; CHECK-NEXT: push {r4, r5, r6, lr}
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]893; CHECK-NEXT: .vsave {d8, d9, d10, d11}
894; CHECK-NEXT: vpush {d8, d9, d10, d11}
895; CHECK-NEXT: vmov q4, q1
896; CHECK-NEXT: vmov q5, q0
897; CHECK-NEXT: vmov r0, s22
898; CHECK-NEXT: vmov r1, s18
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]899; CHECK-NEXT: bl fmodf
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]900; CHECK-NEXT: mov r4, r0
901; CHECK-NEXT: vmov r0, s23
902; CHECK-NEXT: vmov r1, s19
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]903; CHECK-NEXT: bl fmodf
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]904; CHECK-NEXT: vmov r2, s21
905; CHECK-NEXT: vmov r1, s17
906; CHECK-NEXT: vmov r6, s16
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]907; CHECK-NEXT: vmov s19, r0
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]908; CHECK-NEXT: vmov r5, s20
909; CHECK-NEXT: vmov s18, r4
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]910; CHECK-NEXT: mov r0, r2
911; CHECK-NEXT: bl fmodf
912; CHECK-NEXT: vmov s17, r0
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]913; CHECK-NEXT: mov r0, r5
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]914; CHECK-NEXT: mov r1, r6
915; CHECK-NEXT: bl fmodf
916; CHECK-NEXT: vmov s16, r0
917; CHECK-NEXT: vmov q0, q4
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]918; CHECK-NEXT: vpop {d8, d9, d10, d11}
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]919; CHECK-NEXT: pop {r4, r5, r6, pc}
David Greenfc410242019-06-28 08:18:55 +0000[diff] [blame]920entry:
921 %out = frem <4 x float> %in1, %in2
922 ret <4 x float> %out
923}
924
925
926define arm_aapcs_vfpcc <8 x half> @fdiv_f16(<8 x half> %in1, <8 x half> %in2) {
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]927; CHECK-LABEL: fdiv_f16:
928; CHECK: @ %bb.0: @ %entry
David Green1c5b1432019-08-28 10:13:23 +0000[diff] [blame]929; CHECK-NEXT: vdiv.f16 s8, s0, s4
930; CHECK-NEXT: vmovx.f16 s10, s0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]931; CHECK-NEXT: vmov r0, s8
David Green1c5b1432019-08-28 10:13:23 +0000[diff] [blame]932; CHECK-NEXT: vmovx.f16 s8, s4
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]933; CHECK-NEXT: vdiv.f16 s8, s10, s8
David Green1c5b1432019-08-28 10:13:23 +0000[diff] [blame]934; CHECK-NEXT: vdiv.f16 s12, s1, s5
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]935; CHECK-NEXT: vmov r1, s8
936; CHECK-NEXT: vmov.16 q2[0], r0
David Green1c5b1432019-08-28 10:13:23 +0000[diff] [blame]937; CHECK-NEXT: vmov r0, s12
938; CHECK-NEXT: vmovx.f16 s12, s5
939; CHECK-NEXT: vmovx.f16 s14, s1
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]940; CHECK-NEXT: vmov.16 q2[1], r1
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]941; CHECK-NEXT: vdiv.f16 s12, s14, s12
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]942; CHECK-NEXT: vmov.16 q2[2], r0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]943; CHECK-NEXT: vmov r0, s12
David Green1c5b1432019-08-28 10:13:23 +0000[diff] [blame]944; CHECK-NEXT: vdiv.f16 s12, s2, s6
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]945; CHECK-NEXT: vmov.16 q2[3], r0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]946; CHECK-NEXT: vmov r0, s12
David Green1c5b1432019-08-28 10:13:23 +0000[diff] [blame]947; CHECK-NEXT: vmovx.f16 s12, s6
948; CHECK-NEXT: vmovx.f16 s14, s2
949; CHECK-NEXT: vdiv.f16 s12, s14, s12
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]950; CHECK-NEXT: vmov.16 q2[4], r0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]951; CHECK-NEXT: vmov r0, s12
David Green1c5b1432019-08-28 10:13:23 +0000[diff] [blame]952; CHECK-NEXT: vdiv.f16 s12, s3, s7
953; CHECK-NEXT: vmovx.f16 s4, s7
954; CHECK-NEXT: vmovx.f16 s0, s3
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]955; CHECK-NEXT: vmov.16 q2[5], r0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]956; CHECK-NEXT: vmov r0, s12
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]957; CHECK-NEXT: vdiv.f16 s0, s0, s4
David Green1c5b1432019-08-28 10:13:23 +0000[diff] [blame]958; CHECK-NEXT: vmov.16 q2[6], r0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]959; CHECK-NEXT: vmov r0, s0
960; CHECK-NEXT: vmov.16 q2[7], r0
961; CHECK-NEXT: vmov q0, q2
962; CHECK-NEXT: bx lr
David Greenfc410242019-06-28 08:18:55 +0000[diff] [blame]963entry:
964 %out = fdiv <8 x half> %in1, %in2
965 ret <8 x half> %out
966}
967
968define arm_aapcs_vfpcc <8 x half> @frem_f16(<8 x half> %in1, <8 x half> %in2) {
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]969; CHECK-LABEL: frem_f16:
970; CHECK: @ %bb.0: @ %entry
David Greend428f882020-06-26 09:01:56 +0100[diff] [blame]971; CHECK-NEXT: .save {r7, lr}
972; CHECK-NEXT: push {r7, lr}
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]973; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
974; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]975; CHECK-NEXT: vmov q5, q0
976; CHECK-NEXT: vmov q4, q1
David Green1c5b1432019-08-28 10:13:23 +0000[diff] [blame]977; CHECK-NEXT: vcvtb.f32.f16 s0, s20
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]978; CHECK-NEXT: vmov r0, s0
979; CHECK-NEXT: vcvtb.f32.f16 s0, s16
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]980; CHECK-NEXT: vmov r1, s0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]981; CHECK-NEXT: bl fmodf
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]982; CHECK-NEXT: vcvtt.f32.f16 s0, s20
David Greend428f882020-06-26 09:01:56 +0100[diff] [blame]983; CHECK-NEXT: vmov s24, r0
984; CHECK-NEXT: vmov r2, s0
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]985; CHECK-NEXT: vcvtt.f32.f16 s0, s16
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]986; CHECK-NEXT: vmov r1, s0
David Greend428f882020-06-26 09:01:56 +0100[diff] [blame]987; CHECK-NEXT: mov r0, r2
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]988; CHECK-NEXT: bl fmodf
989; CHECK-NEXT: vmov s0, r0
David Greend428f882020-06-26 09:01:56 +0100[diff] [blame]990; CHECK-NEXT: vcvtb.f16.f32 s24, s24
991; CHECK-NEXT: vcvtt.f16.f32 s24, s0
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]992; CHECK-NEXT: vcvtb.f32.f16 s0, s21
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]993; CHECK-NEXT: vmov r0, s0
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]994; CHECK-NEXT: vcvtb.f32.f16 s0, s17
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]995; CHECK-NEXT: vmov r1, s0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]996; CHECK-NEXT: bl fmodf
997; CHECK-NEXT: vmov s0, r0
David Greend428f882020-06-26 09:01:56 +0100[diff] [blame]998; CHECK-NEXT: vcvtb.f16.f32 s25, s0
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]999; CHECK-NEXT: vcvtt.f32.f16 s0, s21
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]1000; CHECK-NEXT: vmov r0, s0
1001; CHECK-NEXT: vcvtt.f32.f16 s0, s17
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]1002; CHECK-NEXT: vmov r1, s0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]1003; CHECK-NEXT: bl fmodf
1004; CHECK-NEXT: vmov s0, r0
David Greend428f882020-06-26 09:01:56 +0100[diff] [blame]1005; CHECK-NEXT: vcvtt.f16.f32 s25, s0
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]1006; CHECK-NEXT: vcvtb.f32.f16 s0, s22
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]1007; CHECK-NEXT: vmov r0, s0
1008; CHECK-NEXT: vcvtb.f32.f16 s0, s18
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]1009; CHECK-NEXT: vmov r1, s0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]1010; CHECK-NEXT: bl fmodf
1011; CHECK-NEXT: vmov s0, r0
David Greend428f882020-06-26 09:01:56 +0100[diff] [blame]1012; CHECK-NEXT: vcvtb.f16.f32 s26, s0
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]1013; CHECK-NEXT: vcvtt.f32.f16 s0, s22
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]1014; CHECK-NEXT: vmov r0, s0
1015; CHECK-NEXT: vcvtt.f32.f16 s0, s18
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]1016; CHECK-NEXT: vmov r1, s0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]1017; CHECK-NEXT: bl fmodf
1018; CHECK-NEXT: vmov s0, r0
David Greend428f882020-06-26 09:01:56 +0100[diff] [blame]1019; CHECK-NEXT: vcvtt.f16.f32 s26, s0
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]1020; CHECK-NEXT: vcvtb.f32.f16 s0, s23
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]1021; CHECK-NEXT: vmov r0, s0
1022; CHECK-NEXT: vcvtb.f32.f16 s0, s19
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]1023; CHECK-NEXT: vmov r1, s0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]1024; CHECK-NEXT: bl fmodf
1025; CHECK-NEXT: vmov s0, r0
David Greend428f882020-06-26 09:01:56 +0100[diff] [blame]1026; CHECK-NEXT: vcvtb.f16.f32 s27, s0
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]1027; CHECK-NEXT: vcvtt.f32.f16 s0, s23
David Green76e0e1a2020-06-26 08:02:26 +0100[diff] [blame]1028; CHECK-NEXT: vmov r0, s0
1029; CHECK-NEXT: vcvtt.f32.f16 s0, s19
David Green13f2a582020-02-25 11:26:53 +0000[diff] [blame]1030; CHECK-NEXT: vmov r1, s0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]1031; CHECK-NEXT: bl fmodf
1032; CHECK-NEXT: vmov s0, r0
David Greend428f882020-06-26 09:01:56 +0100[diff] [blame]1033; CHECK-NEXT: vcvtt.f16.f32 s27, s0
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]1034; CHECK-NEXT: vmov q0, q6
Simon Tathambffd0992019-07-02 11:26:11 +0000[diff] [blame]1035; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
David Greend428f882020-06-26 09:01:56 +0100[diff] [blame]1036; CHECK-NEXT: pop {r7, pc}
David Greenfc410242019-06-28 08:18:55 +0000[diff] [blame]1037entry:
1038 %out = frem <8 x half> %in1, %in2
1039 ret <8 x half> %out
1040}
David Greendc569952019-07-15 18:42:54 +0000[diff] [blame]1041
1042define arm_aapcs_vfpcc <2 x double> @fdiv_f64(<2 x double> %in1, <2 x double> %in2) {
1043; CHECK-LABEL: fdiv_f64:
1044; CHECK: @ %bb.0: @ %entry
1045; CHECK-NEXT: .save {r7, lr}
1046; CHECK-NEXT: push {r7, lr}
1047; CHECK-NEXT: .vsave {d8, d9, d10, d11}
1048; CHECK-NEXT: vpush {d8, d9, d10, d11}
1049; CHECK-NEXT: vmov q4, q1
1050; CHECK-NEXT: vmov q5, q0
1051; CHECK-NEXT: vmov r0, r1, d11
1052; CHECK-NEXT: vmov r2, r3, d9
1053; CHECK-NEXT: bl __aeabi_ddiv
1054; CHECK-NEXT: vmov lr, r12, d10
1055; CHECK-NEXT: vmov r2, r3, d8
1056; CHECK-NEXT: vmov d9, r0, r1
1057; CHECK-NEXT: mov r0, lr
1058; CHECK-NEXT: mov r1, r12
1059; CHECK-NEXT: bl __aeabi_ddiv
1060; CHECK-NEXT: vmov d8, r0, r1
1061; CHECK-NEXT: vmov q0, q4
1062; CHECK-NEXT: vpop {d8, d9, d10, d11}
1063; CHECK-NEXT: pop {r7, pc}
1064entry:
1065 %out = fdiv <2 x double> %in1, %in2
1066 ret <2 x double> %out
1067}
1068
1069define arm_aapcs_vfpcc <2 x double> @frem_f64(<2 x double> %in1, <2 x double> %in2) {
1070; CHECK-LABEL: frem_f64:
1071; CHECK: @ %bb.0: @ %entry
1072; CHECK-NEXT: .save {r7, lr}
1073; CHECK-NEXT: push {r7, lr}
1074; CHECK-NEXT: .vsave {d8, d9, d10, d11}
1075; CHECK-NEXT: vpush {d8, d9, d10, d11}
1076; CHECK-NEXT: vmov q4, q1
1077; CHECK-NEXT: vmov q5, q0
1078; CHECK-NEXT: vmov r0, r1, d11
1079; CHECK-NEXT: vmov r2, r3, d9
1080; CHECK-NEXT: bl fmod
1081; CHECK-NEXT: vmov lr, r12, d10
1082; CHECK-NEXT: vmov r2, r3, d8
1083; CHECK-NEXT: vmov d9, r0, r1
1084; CHECK-NEXT: mov r0, lr
1085; CHECK-NEXT: mov r1, r12
1086; CHECK-NEXT: bl fmod
1087; CHECK-NEXT: vmov d8, r0, r1
1088; CHECK-NEXT: vmov q0, q4
1089; CHECK-NEXT: vpop {d8, d9, d10, d11}
1090; CHECK-NEXT: pop {r7, pc}
1091entry:
1092 %out = frem <2 x double> %in1, %in2
1093 ret <2 x double> %out
1094}
1095
1096