Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 00ed9964c65962e2afc8e3c83a2f7114b0ce25a0 / . / llvm / lib / Target / ARM64 / MCTargetDesc / ARM64BaseInfo.h
blob: d3c2cf7230fb9d82d684c4f93a8052633ec054dd [file] [log] [blame]
Tim Northover00ed9962014-03-29 10:18:08 +0000[diff] [blame^]1//===-- ARM64BaseInfo.h - Top level definitions for ARM64 -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains small standalone helper functions and enum definitions for
11// the ARM64 target useful for the compiler back-end and the MC libraries.
12// As such, it deliberately does not include references to LLVM core
13// code gen types, passes, etc..
14//
15//===----------------------------------------------------------------------===//
16
17#ifndef ARM64BASEINFO_H
18#define ARM64BASEINFO_H
19
20#include "ARM64MCTargetDesc.h"
21#include "llvm/Support/ErrorHandling.h"
22
23namespace llvm {
24
25inline static unsigned getWRegFromXReg(unsigned Reg) {
26 switch (Reg) {
27 case ARM64::X0: return ARM64::W0;
28 case ARM64::X1: return ARM64::W1;
29 case ARM64::X2: return ARM64::W2;
30 case ARM64::X3: return ARM64::W3;
31 case ARM64::X4: return ARM64::W4;
32 case ARM64::X5: return ARM64::W5;
33 case ARM64::X6: return ARM64::W6;
34 case ARM64::X7: return ARM64::W7;
35 case ARM64::X8: return ARM64::W8;
36 case ARM64::X9: return ARM64::W9;
37 case ARM64::X10: return ARM64::W10;
38 case ARM64::X11: return ARM64::W11;
39 case ARM64::X12: return ARM64::W12;
40 case ARM64::X13: return ARM64::W13;
41 case ARM64::X14: return ARM64::W14;
42 case ARM64::X15: return ARM64::W15;
43 case ARM64::X16: return ARM64::W16;
44 case ARM64::X17: return ARM64::W17;
45 case ARM64::X18: return ARM64::W18;
46 case ARM64::X19: return ARM64::W19;
47 case ARM64::X20: return ARM64::W20;
48 case ARM64::X21: return ARM64::W21;
49 case ARM64::X22: return ARM64::W22;
50 case ARM64::X23: return ARM64::W23;
51 case ARM64::X24: return ARM64::W24;
52 case ARM64::X25: return ARM64::W25;
53 case ARM64::X26: return ARM64::W26;
54 case ARM64::X27: return ARM64::W27;
55 case ARM64::X28: return ARM64::W28;
56 case ARM64::FP: return ARM64::W29;
57 case ARM64::LR: return ARM64::W30;
58 case ARM64::SP: return ARM64::WSP;
59 case ARM64::XZR: return ARM64::WZR;
60 }
61 // For anything else, return it unchanged.
62 return Reg;
63}
64
65inline static unsigned getXRegFromWReg(unsigned Reg) {
66 switch (Reg) {
67 case ARM64::W0: return ARM64::X0;
68 case ARM64::W1: return ARM64::X1;
69 case ARM64::W2: return ARM64::X2;
70 case ARM64::W3: return ARM64::X3;
71 case ARM64::W4: return ARM64::X4;
72 case ARM64::W5: return ARM64::X5;
73 case ARM64::W6: return ARM64::X6;
74 case ARM64::W7: return ARM64::X7;
75 case ARM64::W8: return ARM64::X8;
76 case ARM64::W9: return ARM64::X9;
77 case ARM64::W10: return ARM64::X10;
78 case ARM64::W11: return ARM64::X11;
79 case ARM64::W12: return ARM64::X12;
80 case ARM64::W13: return ARM64::X13;
81 case ARM64::W14: return ARM64::X14;
82 case ARM64::W15: return ARM64::X15;
83 case ARM64::W16: return ARM64::X16;
84 case ARM64::W17: return ARM64::X17;
85 case ARM64::W18: return ARM64::X18;
86 case ARM64::W19: return ARM64::X19;
87 case ARM64::W20: return ARM64::X20;
88 case ARM64::W21: return ARM64::X21;
89 case ARM64::W22: return ARM64::X22;
90 case ARM64::W23: return ARM64::X23;
91 case ARM64::W24: return ARM64::X24;
92 case ARM64::W25: return ARM64::X25;
93 case ARM64::W26: return ARM64::X26;
94 case ARM64::W27: return ARM64::X27;
95 case ARM64::W28: return ARM64::X28;
96 case ARM64::W29: return ARM64::FP;
97 case ARM64::W30: return ARM64::LR;
98 case ARM64::WSP: return ARM64::SP;
99 case ARM64::WZR: return ARM64::XZR;
100 }
101 // For anything else, return it unchanged.
102 return Reg;
103}
104
105static inline unsigned getBRegFromDReg(unsigned Reg) {
106 switch (Reg) {
107 case ARM64::D0: return ARM64::B0;
108 case ARM64::D1: return ARM64::B1;
109 case ARM64::D2: return ARM64::B2;
110 case ARM64::D3: return ARM64::B3;
111 case ARM64::D4: return ARM64::B4;
112 case ARM64::D5: return ARM64::B5;
113 case ARM64::D6: return ARM64::B6;
114 case ARM64::D7: return ARM64::B7;
115 case ARM64::D8: return ARM64::B8;
116 case ARM64::D9: return ARM64::B9;
117 case ARM64::D10: return ARM64::B10;
118 case ARM64::D11: return ARM64::B11;
119 case ARM64::D12: return ARM64::B12;
120 case ARM64::D13: return ARM64::B13;
121 case ARM64::D14: return ARM64::B14;
122 case ARM64::D15: return ARM64::B15;
123 case ARM64::D16: return ARM64::B16;
124 case ARM64::D17: return ARM64::B17;
125 case ARM64::D18: return ARM64::B18;
126 case ARM64::D19: return ARM64::B19;
127 case ARM64::D20: return ARM64::B20;
128 case ARM64::D21: return ARM64::B21;
129 case ARM64::D22: return ARM64::B22;
130 case ARM64::D23: return ARM64::B23;
131 case ARM64::D24: return ARM64::B24;
132 case ARM64::D25: return ARM64::B25;
133 case ARM64::D26: return ARM64::B26;
134 case ARM64::D27: return ARM64::B27;
135 case ARM64::D28: return ARM64::B28;
136 case ARM64::D29: return ARM64::B29;
137 case ARM64::D30: return ARM64::B30;
138 case ARM64::D31: return ARM64::B31;
139 }
140 // For anything else, return it unchanged.
141 return Reg;
142}
143
144
145static inline unsigned getDRegFromBReg(unsigned Reg) {
146 switch (Reg) {
147 case ARM64::B0: return ARM64::D0;
148 case ARM64::B1: return ARM64::D1;
149 case ARM64::B2: return ARM64::D2;
150 case ARM64::B3: return ARM64::D3;
151 case ARM64::B4: return ARM64::D4;
152 case ARM64::B5: return ARM64::D5;
153 case ARM64::B6: return ARM64::D6;
154 case ARM64::B7: return ARM64::D7;
155 case ARM64::B8: return ARM64::D8;
156 case ARM64::B9: return ARM64::D9;
157 case ARM64::B10: return ARM64::D10;
158 case ARM64::B11: return ARM64::D11;
159 case ARM64::B12: return ARM64::D12;
160 case ARM64::B13: return ARM64::D13;
161 case ARM64::B14: return ARM64::D14;
162 case ARM64::B15: return ARM64::D15;
163 case ARM64::B16: return ARM64::D16;
164 case ARM64::B17: return ARM64::D17;
165 case ARM64::B18: return ARM64::D18;
166 case ARM64::B19: return ARM64::D19;
167 case ARM64::B20: return ARM64::D20;
168 case ARM64::B21: return ARM64::D21;
169 case ARM64::B22: return ARM64::D22;
170 case ARM64::B23: return ARM64::D23;
171 case ARM64::B24: return ARM64::D24;
172 case ARM64::B25: return ARM64::D25;
173 case ARM64::B26: return ARM64::D26;
174 case ARM64::B27: return ARM64::D27;
175 case ARM64::B28: return ARM64::D28;
176 case ARM64::B29: return ARM64::D29;
177 case ARM64::B30: return ARM64::D30;
178 case ARM64::B31: return ARM64::D31;
179 }
180 // For anything else, return it unchanged.
181 return Reg;
182}
183
184namespace ARM64CC {
185
186// The CondCodes constants map directly to the 4-bit encoding of the condition
187// field for predicated instructions.
188enum CondCode { // Meaning (integer) Meaning (floating-point)
189 EQ = 0x0, // Equal Equal
190 NE = 0x1, // Not equal Not equal, or unordered
191 CS = 0x2, // Carry set >, ==, or unordered
192 CC = 0x3, // Carry clear Less than
193 MI = 0x4, // Minus, negative Less than
194 PL = 0x5, // Plus, positive or zero >, ==, or unordered
195 VS = 0x6, // Overflow Unordered
196 VC = 0x7, // No overflow Not unordered
197 HI = 0x8, // Unsigned higher Greater than, or unordered
198 LS = 0x9, // Unsigned lower or same Less than or equal
199 GE = 0xa, // Greater than or equal Greater than or equal
200 LT = 0xb, // Less than Less than, or unordered
201 GT = 0xc, // Greater than Greater than
202 LE = 0xd, // Less than or equal <, ==, or unordered
203 AL = 0xe // Always (unconditional) Always (unconditional)
204};
205
206inline static const char *getCondCodeName(CondCode Code) {
207 // cond<0> is ignored when cond<3:1> = 111, where 1110 is 0xe (aka AL).
208 if ((Code & AL) == AL)
209 Code = AL;
210 switch (Code) {
211 case EQ: return "eq";
212 case NE: return "ne";
213 case CS: return "cs";
214 case CC: return "cc";
215 case MI: return "mi";
216 case PL: return "pl";
217 case VS: return "vs";
218 case VC: return "vc";
219 case HI: return "hi";
220 case LS: return "ls";
221 case GE: return "ge";
222 case LT: return "lt";
223 case GT: return "gt";
224 case LE: return "le";
225 case AL: return "al";
226 }
227 llvm_unreachable("Unknown condition code");
228}
229
230inline static CondCode getInvertedCondCode(CondCode Code) {
231 switch (Code) {
232 default: llvm_unreachable("Unknown condition code");
233 case EQ: return NE;
234 case NE: return EQ;
235 case CS: return CC;
236 case CC: return CS;
237 case MI: return PL;
238 case PL: return MI;
239 case VS: return VC;
240 case VC: return VS;
241 case HI: return LS;
242 case LS: return HI;
243 case GE: return LT;
244 case LT: return GE;
245 case GT: return LE;
246 case LE: return GT;
247 }
248}
249
250/// Given a condition code, return NZCV flags that would satisfy that condition.
251/// The flag bits are in the format expected by the ccmp instructions.
252/// Note that many different flag settings can satisfy a given condition code,
253/// this function just returns one of them.
254inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
255 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
256 enum { N = 8, Z = 4, C = 2, V = 1 };
257 switch (Code) {
258 default: llvm_unreachable("Unknown condition code");
259 case EQ: return Z; // Z == 1
260 case NE: return 0; // Z == 0
261 case CS: return C; // C == 1
262 case CC: return 0; // C == 0
263 case MI: return N; // N == 1
264 case PL: return 0; // N == 0
265 case VS: return V; // V == 1
266 case VC: return 0; // V == 0
267 case HI: return C; // C == 1 && Z == 0
268 case LS: return 0; // C == 0 || Z == 1
269 case GE: return 0; // N == V
270 case LT: return N; // N != V
271 case GT: return 0; // Z == 0 && N == V
272 case LE: return Z; // Z == 1 || N != V
273 }
274}
275} // end namespace ARM64CC
276
277namespace ARM64SYS {
278enum BarrierOption {
279 InvalidBarrier = 0xff,
280 OSHLD = 0x1,
281 OSHST = 0x2,
282 OSH = 0x3,
283 NSHLD = 0x5,
284 NSHST = 0x6,
285 NSH = 0x7,
286 ISHLD = 0x9,
287 ISHST = 0xa,
288 ISH = 0xb,
289 LD = 0xd,
290 ST = 0xe,
291 SY = 0xf
292};
293
294inline static const char *getBarrierOptName(BarrierOption Opt) {
295 switch (Opt) {
296 default: return NULL;
297 case 0x1: return "oshld";
298 case 0x2: return "oshst";
299 case 0x3: return "osh";
300 case 0x5: return "nshld";
301 case 0x6: return "nshst";
302 case 0x7: return "nsh";
303 case 0x9: return "ishld";
304 case 0xa: return "ishst";
305 case 0xb: return "ish";
306 case 0xd: return "ld";
307 case 0xe: return "st";
308 case 0xf: return "sy";
309 }
310}
311
312#define A64_SYSREG_ENC(op0,CRn,op2,CRm,op1) ((op0) << 14 | (op1) << 11 | \
313 (CRn) << 7 | (CRm) << 3 | (op2))
314enum SystemRegister {
315 InvalidSystemReg = 0,
316 // Table in section 3.10.3
317 SPSR_EL1 = 0xc200,
318 SPSR_svc = SPSR_EL1,
319 ELR_EL1 = 0xc201,
320 SP_EL0 = 0xc208,
321 SPSel = 0xc210,
322 CurrentEL = 0xc212,
323 DAIF = 0xda11,
324 NZCV = 0xda10,
325 FPCR = 0xda20,
326 FPSR = 0xda21,
327 DSPSR = 0xda28,
328 DLR = 0xda29,
329 SPSR_EL2 = 0xe200,
330 SPSR_hyp = SPSR_EL2,
331 ELR_EL2 = 0xe201,
332 SP_EL1 = 0xe208,
333 SPSR_irq = 0xe218,
334 SPSR_abt = 0xe219,
335 SPSR_und = 0xe21a,
336 SPSR_fiq = 0xe21b,
337 SPSR_EL3 = 0xf200,
338 ELR_EL3 = 0xf201,
339 SP_EL2 = 0xf208,
340
341
342 // Table in section 3.10.8
343 MIDR_EL1 = 0xc000,
344 CTR_EL0 = 0xd801,
345 MPIDR_EL1 = 0xc005,
346 ECOIDR_EL1 = 0xc006,
347 DCZID_EL0 = 0xd807,
348 MVFR0_EL1 = 0xc018,
349 MVFR1_EL1 = 0xc019,
350 ID_AA64PFR0_EL1 = 0xc020,
351 ID_AA64PFR1_EL1 = 0xc021,
352 ID_AA64DFR0_EL1 = 0xc028,
353 ID_AA64DFR1_EL1 = 0xc029,
354 ID_AA64ISAR0_EL1 = 0xc030,
355 ID_AA64ISAR1_EL1 = 0xc031,
356 ID_AA64MMFR0_EL1 = 0xc038,
357 ID_AA64MMFR1_EL1 = 0xc039,
358 CCSIDR_EL1 = 0xc800,
359 CLIDR_EL1 = 0xc801,
360 AIDR_EL1 = 0xc807,
361 CSSELR_EL1 = 0xd000,
362 VPIDR_EL2 = 0xe000,
363 VMPIDR_EL2 = 0xe005,
364 SCTLR_EL1 = 0xc080,
365 SCTLR_EL2 = 0xe080,
366 SCTLR_EL3 = 0xf080,
367 ACTLR_EL1 = 0xc081,
368 ACTLR_EL2 = 0xe081,
369 ACTLR_EL3 = 0xf081,
370 CPACR_EL1 = 0xc082,
371 CPTR_EL2 = 0xe08a,
372 CPTR_EL3 = 0xf08a,
373 SCR_EL3 = 0xf088,
374 HCR_EL2 = 0xe088,
375 MDCR_EL2 = 0xe089,
376 MDCR_EL3 = 0xf099,
377 HSTR_EL2 = 0xe08b,
378 HACR_EL2 = 0xe08f,
379 TTBR0_EL1 = 0xc100,
380 TTBR1_EL1 = 0xc101,
381 TTBR0_EL2 = 0xe100,
382 TTBR0_EL3 = 0xf100,
383 VTTBR_EL2 = 0xe108,
384 TCR_EL1 = 0xc102,
385 TCR_EL2 = 0xe102,
386 TCR_EL3 = 0xf102,
387 VTCR_EL2 = 0xe10a,
388 ADFSR_EL1 = 0xc288,
389 AIFSR_EL1 = 0xc289,
390 ADFSR_EL2 = 0xe288,
391 AIFSR_EL2 = 0xe289,
392 ADFSR_EL3 = 0xf288,
393 AIFSR_EL3 = 0xf289,
394 ESR_EL1 = 0xc290,
395 ESR_EL2 = 0xe290,
396 ESR_EL3 = 0xf290,
397 FAR_EL1 = 0xc300,
398 FAR_EL2 = 0xe300,
399 FAR_EL3 = 0xf300,
400 HPFAR_EL2 = 0xe304,
401 PAR_EL1 = 0xc3a0,
402 MAIR_EL1 = 0xc510,
403 MAIR_EL2 = 0xe510,
404 MAIR_EL3 = 0xf510,
405 AMAIR_EL1 = 0xc518,
406 AMAIR_EL2 = 0xe518,
407 AMAIR_EL3 = 0xf518,
408 VBAR_EL1 = 0xc600,
409 VBAR_EL2 = 0xe600,
410 VBAR_EL3 = 0xf600,
411 RVBAR_EL1 = 0xc601,
412 RVBAR_EL2 = 0xe601,
413 RVBAR_EL3 = 0xf601,
414 ISR_EL1 = 0xc608,
415 CONTEXTIDR_EL1 = 0xc681,
416 TPIDR_EL0 = 0xde82,
417 TPIDRRO_EL0 = 0xde83,
418 TPIDR_EL1 = 0xc684,
419 TPIDR_EL2 = 0xe682,
420 TPIDR_EL3 = 0xf682,
421 TEECR32_EL1 = 0x9000,
422 CNTFRQ_EL0 = 0xdf00,
423 CNTPCT_EL0 = 0xdf01,
424 CNTVCT_EL0 = 0xdf02,
425 CNTVOFF_EL2 = 0xe703,
426 CNTKCTL_EL1 = 0xc708,
427 CNTHCTL_EL2 = 0xe708,
428 CNTP_TVAL_EL0 = 0xdf10,
429 CNTP_CTL_EL0 = 0xdf11,
430 CNTP_CVAL_EL0 = 0xdf12,
431 CNTV_TVAL_EL0 = 0xdf18,
432 CNTV_CTL_EL0 = 0xdf19,
433 CNTV_CVAL_EL0 = 0xdf1a,
434 CNTHP_TVAL_EL2 = 0xe710,
435 CNTHP_CTL_EL2 = 0xe711,
436 CNTHP_CVAL_EL2 = 0xe712,
437 CNTPS_TVAL_EL1 = 0xff10,
438 CNTPS_CTL_EL1 = 0xff11,
439 CNTPS_CVAL_EL1= 0xff12,
440
441 PMEVCNTR0_EL0 = 0xdf40,
442 PMEVCNTR1_EL0 = 0xdf41,
443 PMEVCNTR2_EL0 = 0xdf42,
444 PMEVCNTR3_EL0 = 0xdf43,
445 PMEVCNTR4_EL0 = 0xdf44,
446 PMEVCNTR5_EL0 = 0xdf45,
447 PMEVCNTR6_EL0 = 0xdf46,
448 PMEVCNTR7_EL0 = 0xdf47,
449 PMEVCNTR8_EL0 = 0xdf48,
450 PMEVCNTR9_EL0 = 0xdf49,
451 PMEVCNTR10_EL0 = 0xdf4a,
452 PMEVCNTR11_EL0 = 0xdf4b,
453 PMEVCNTR12_EL0 = 0xdf4c,
454 PMEVCNTR13_EL0 = 0xdf4d,
455 PMEVCNTR14_EL0 = 0xdf4e,
456 PMEVCNTR15_EL0 = 0xdf4f,
457 PMEVCNTR16_EL0 = 0xdf50,
458 PMEVCNTR17_EL0 = 0xdf51,
459 PMEVCNTR18_EL0 = 0xdf52,
460 PMEVCNTR19_EL0 = 0xdf53,
461 PMEVCNTR20_EL0 = 0xdf54,
462 PMEVCNTR21_EL0 = 0xdf55,
463 PMEVCNTR22_EL0 = 0xdf56,
464 PMEVCNTR23_EL0 = 0xdf57,
465 PMEVCNTR24_EL0 = 0xdf58,
466 PMEVCNTR25_EL0 = 0xdf59,
467 PMEVCNTR26_EL0 = 0xdf5a,
468 PMEVCNTR27_EL0 = 0xdf5b,
469 PMEVCNTR28_EL0 = 0xdf5c,
470 PMEVCNTR29_EL0 = 0xdf5d,
471 PMEVCNTR30_EL0 = 0xdf5e,
472
473 PMEVTYPER0_EL0 = 0xdf60,
474 PMEVTYPER1_EL0 = 0xdf61,
475 PMEVTYPER2_EL0 = 0xdf62,
476 PMEVTYPER3_EL0 = 0xdf63,
477 PMEVTYPER4_EL0 = 0xdf64,
478 PMEVTYPER5_EL0 = 0xdf65,
479 PMEVTYPER6_EL0 = 0xdf66,
480 PMEVTYPER7_EL0 = 0xdf67,
481 PMEVTYPER8_EL0 = 0xdf68,
482 PMEVTYPER9_EL0 = 0xdf69,
483 PMEVTYPER10_EL0 = 0xdf6a,
484 PMEVTYPER11_EL0 = 0xdf6b,
485 PMEVTYPER12_EL0 = 0xdf6c,
486 PMEVTYPER13_EL0 = 0xdf6d,
487 PMEVTYPER14_EL0 = 0xdf6e,
488 PMEVTYPER15_EL0 = 0xdf6f,
489 PMEVTYPER16_EL0 = 0xdf70,
490 PMEVTYPER17_EL0 = 0xdf71,
491 PMEVTYPER18_EL0 = 0xdf72,
492 PMEVTYPER19_EL0 = 0xdf73,
493 PMEVTYPER20_EL0 = 0xdf74,
494 PMEVTYPER21_EL0 = 0xdf75,
495 PMEVTYPER22_EL0 = 0xdf76,
496 PMEVTYPER23_EL0 = 0xdf77,
497 PMEVTYPER24_EL0 = 0xdf78,
498 PMEVTYPER25_EL0 = 0xdf79,
499 PMEVTYPER26_EL0 = 0xdf7a,
500 PMEVTYPER27_EL0 = 0xdf7b,
501 PMEVTYPER28_EL0 = 0xdf7c,
502 PMEVTYPER29_EL0 = 0xdf7d,
503 PMEVTYPER30_EL0 = 0xdf7e,
504
505 PMCCFILTR_EL0 = 0xdf7f,
506
507 RMR_EL3 = 0xf602,
508 RMR_EL2 = 0xd602,
509 RMR_EL1 = 0xce02,
510
511 // Debug Architecture 5.3, Table 17.
512 MDCCSR_EL0 = A64_SYSREG_ENC(2, 0, 0, 1, 3),
513 MDCCINT_EL1 = A64_SYSREG_ENC(2, 0, 0, 2, 0),
514 DBGDTR_EL0 = A64_SYSREG_ENC(2, 0, 0, 4, 3),
515 DBGDTRRX_EL0 = A64_SYSREG_ENC(2, 0, 0, 5, 3),
516 DBGDTRTX_EL0 = DBGDTRRX_EL0,
517 DBGVCR32_EL2 = A64_SYSREG_ENC(2, 0, 0, 7, 4),
518 OSDTRRX_EL1 = A64_SYSREG_ENC(2, 0, 2, 0, 0),
519 MDSCR_EL1 = A64_SYSREG_ENC(2, 0, 2, 2, 0),
520 OSDTRTX_EL1 = A64_SYSREG_ENC(2, 0, 2, 3, 0),
521 OSECCR_EL11 = A64_SYSREG_ENC(2, 0, 2, 6, 0),
522
523 DBGBVR0_EL1 = A64_SYSREG_ENC(2, 0, 4, 0, 0),
524 DBGBVR1_EL1 = A64_SYSREG_ENC(2, 0, 4, 1, 0),
525 DBGBVR2_EL1 = A64_SYSREG_ENC(2, 0, 4, 2, 0),
526 DBGBVR3_EL1 = A64_SYSREG_ENC(2, 0, 4, 3, 0),
527 DBGBVR4_EL1 = A64_SYSREG_ENC(2, 0, 4, 4, 0),
528 DBGBVR5_EL1 = A64_SYSREG_ENC(2, 0, 4, 5, 0),
529 DBGBVR6_EL1 = A64_SYSREG_ENC(2, 0, 4, 6, 0),
530 DBGBVR7_EL1 = A64_SYSREG_ENC(2, 0, 4, 7, 0),
531 DBGBVR8_EL1 = A64_SYSREG_ENC(2, 0, 4, 8, 0),
532 DBGBVR9_EL1 = A64_SYSREG_ENC(2, 0, 4, 9, 0),
533 DBGBVR10_EL1 = A64_SYSREG_ENC(2, 0, 4, 10, 0),
534 DBGBVR11_EL1 = A64_SYSREG_ENC(2, 0, 4, 11, 0),
535 DBGBVR12_EL1 = A64_SYSREG_ENC(2, 0, 4, 12, 0),
536 DBGBVR13_EL1 = A64_SYSREG_ENC(2, 0, 4, 13, 0),
537 DBGBVR14_EL1 = A64_SYSREG_ENC(2, 0, 4, 14, 0),
538 DBGBVR15_EL1 = A64_SYSREG_ENC(2, 0, 4, 15, 0),
539
540 DBGBCR0_EL1 = A64_SYSREG_ENC(2, 0, 5, 0, 0),
541 DBGBCR1_EL1 = A64_SYSREG_ENC(2, 0, 5, 1, 0),
542 DBGBCR2_EL1 = A64_SYSREG_ENC(2, 0, 5, 2, 0),
543 DBGBCR3_EL1 = A64_SYSREG_ENC(2, 0, 5, 3, 0),
544 DBGBCR4_EL1 = A64_SYSREG_ENC(2, 0, 5, 4, 0),
545 DBGBCR5_EL1 = A64_SYSREG_ENC(2, 0, 5, 5, 0),
546 DBGBCR6_EL1 = A64_SYSREG_ENC(2, 0, 5, 6, 0),
547 DBGBCR7_EL1 = A64_SYSREG_ENC(2, 0, 5, 7, 0),
548 DBGBCR8_EL1 = A64_SYSREG_ENC(2, 0, 5, 8, 0),
549 DBGBCR9_EL1 = A64_SYSREG_ENC(2, 0, 5, 9, 0),
550 DBGBCR10_EL1 = A64_SYSREG_ENC(2, 0, 5, 10, 0),
551 DBGBCR11_EL1 = A64_SYSREG_ENC(2, 0, 5, 11, 0),
552 DBGBCR12_EL1 = A64_SYSREG_ENC(2, 0, 5, 12, 0),
553 DBGBCR13_EL1 = A64_SYSREG_ENC(2, 0, 5, 13, 0),
554 DBGBCR14_EL1 = A64_SYSREG_ENC(2, 0, 5, 14, 0),
555 DBGBCR15_EL1 = A64_SYSREG_ENC(2, 0, 5, 15, 0),
556
557 DBGWVR0_EL1 = A64_SYSREG_ENC(2, 0, 6, 0, 0),
558 DBGWVR1_EL1 = A64_SYSREG_ENC(2, 0, 6, 1, 0),
559 DBGWVR2_EL1 = A64_SYSREG_ENC(2, 0, 6, 2, 0),
560 DBGWVR3_EL1 = A64_SYSREG_ENC(2, 0, 6, 3, 0),
561 DBGWVR4_EL1 = A64_SYSREG_ENC(2, 0, 6, 4, 0),
562 DBGWVR5_EL1 = A64_SYSREG_ENC(2, 0, 6, 5, 0),
563 DBGWVR6_EL1 = A64_SYSREG_ENC(2, 0, 6, 6, 0),
564 DBGWVR7_EL1 = A64_SYSREG_ENC(2, 0, 6, 7, 0),
565 DBGWVR8_EL1 = A64_SYSREG_ENC(2, 0, 6, 8, 0),
566 DBGWVR9_EL1 = A64_SYSREG_ENC(2, 0, 6, 9, 0),
567 DBGWVR10_EL1 = A64_SYSREG_ENC(2, 0, 6, 10, 0),
568 DBGWVR11_EL1 = A64_SYSREG_ENC(2, 0, 6, 11, 0),
569 DBGWVR12_EL1 = A64_SYSREG_ENC(2, 0, 6, 12, 0),
570 DBGWVR13_EL1 = A64_SYSREG_ENC(2, 0, 6, 13, 0),
571 DBGWVR14_EL1 = A64_SYSREG_ENC(2, 0, 6, 14, 0),
572 DBGWVR15_EL1 = A64_SYSREG_ENC(2, 0, 6, 15, 0),
573
574 DBGWCR0_EL1 = A64_SYSREG_ENC(2, 0, 7, 0, 0),
575 DBGWCR1_EL1 = A64_SYSREG_ENC(2, 0, 7, 1, 0),
576 DBGWCR2_EL1 = A64_SYSREG_ENC(2, 0, 7, 2, 0),
577 DBGWCR3_EL1 = A64_SYSREG_ENC(2, 0, 7, 3, 0),
578 DBGWCR4_EL1 = A64_SYSREG_ENC(2, 0, 7, 4, 0),
579 DBGWCR5_EL1 = A64_SYSREG_ENC(2, 0, 7, 5, 0),
580 DBGWCR6_EL1 = A64_SYSREG_ENC(2, 0, 7, 6, 0),
581 DBGWCR7_EL1 = A64_SYSREG_ENC(2, 0, 7, 7, 0),
582 DBGWCR8_EL1 = A64_SYSREG_ENC(2, 0, 7, 8, 0),
583 DBGWCR9_EL1 = A64_SYSREG_ENC(2, 0, 7, 9, 0),
584 DBGWCR10_EL1 = A64_SYSREG_ENC(2, 0, 7, 10, 0),
585 DBGWCR11_EL1 = A64_SYSREG_ENC(2, 0, 7, 11, 0),
586 DBGWCR12_EL1 = A64_SYSREG_ENC(2, 0, 7, 12, 0),
587 DBGWCR13_EL1 = A64_SYSREG_ENC(2, 0, 7, 13, 0),
588 DBGWCR14_EL1 = A64_SYSREG_ENC(2, 0, 7, 14, 0),
589 DBGWCR15_EL1 = A64_SYSREG_ENC(2, 0, 7, 15, 0),
590
591 MDRAR_EL1 = A64_SYSREG_ENC(2, 1, 0, 0, 0),
592 OSLAR_EL1 = A64_SYSREG_ENC(2, 1, 4, 0, 0),
593 OSLSR_EL1 = A64_SYSREG_ENC(2, 1, 4, 1, 0),
594 OSDLR_EL1 = A64_SYSREG_ENC(2, 1, 4, 3, 0),
595 DBGPRCR_EL1 = A64_SYSREG_ENC(2, 1, 4, 4, 0),
596
597 DBGCLAIMSET_EL1 = A64_SYSREG_ENC(2, 7, 6, 8, 0),
598 DBGCLAIMCLR_EL1 = A64_SYSREG_ENC(2, 7, 6, 9, 0),
599 DBGAUTHSTATUS_EL1 = A64_SYSREG_ENC(2, 7, 6, 14, 0),
600
601 DBGDEVID2 = A64_SYSREG_ENC(2, 7, 7, 0, 0),
602 DBGDEVID1 = A64_SYSREG_ENC(2, 7, 7, 1, 0),
603 DBGDEVID0 = A64_SYSREG_ENC(2, 7, 7, 2, 0),
604
605 // The following registers are defined to allow access from AArch64 to
606 // registers which are only used in the AArch32 architecture.
607 DACR32_EL2 = 0xe180,
608 IFSR32_EL2 = 0xe281,
609 TEEHBR32_EL1 = 0x9080,
610 SDER32_EL3 = 0xf089,
611 FPEXC32_EL2 = 0xe298,
612
613 // Cyclone specific system registers
614 CPM_IOACC_CTL_EL3 = 0xff90,
615
616 // Architectural system registers
617 ID_PFR0_EL1 = 0xc008,
618 ID_PFR1_EL1 = 0xc009,
619 ID_DFR0_EL1 = 0xc00a,
620 ID_AFR0_EL1 = 0xc00b,
621 ID_ISAR0_EL1 = 0xc010,
622 ID_ISAR1_EL1 = 0xc011,
623 ID_ISAR2_EL1 = 0xc012,
624 ID_ISAR3_EL1 = 0xc013,
625 ID_ISAR4_EL1 = 0xc014,
626 ID_ISAR5_EL1 = 0xc015,
627 AFSR1_EL1 = 0xc289, // note same as old AIFSR_EL1
628 AFSR0_EL1 = 0xc288, // note same as old ADFSR_EL1
629 REVIDR_EL1 = 0xc006 // note same as old ECOIDR_EL1
630
631};
632#undef A64_SYSREG_ENC
633
634static inline const char *getSystemRegisterName(SystemRegister Reg) {
635 switch(Reg) {
636 default: return NULL; // Caller is responsible for handling invalid value.
637 case SPSR_EL1: return "SPSR_EL1";
638 case ELR_EL1: return "ELR_EL1";
639 case SP_EL0: return "SP_EL0";
640 case SPSel: return "SPSel";
641 case DAIF: return "DAIF";
642 case CurrentEL: return "CurrentEL";
643 case NZCV: return "NZCV";
644 case FPCR: return "FPCR";
645 case FPSR: return "FPSR";
646 case DSPSR: return "DSPSR";
647 case DLR: return "DLR";
648 case SPSR_EL2: return "SPSR_EL2";
649 case ELR_EL2: return "ELR_EL2";
650 case SP_EL1: return "SP_EL1";
651 case SPSR_irq: return "SPSR_irq";
652 case SPSR_abt: return "SPSR_abt";
653 case SPSR_und: return "SPSR_und";
654 case SPSR_fiq: return "SPSR_fiq";
655 case SPSR_EL3: return "SPSR_EL3";
656 case ELR_EL3: return "ELR_EL3";
657 case SP_EL2: return "SP_EL2";
658 case MIDR_EL1: return "MIDR_EL1";
659 case CTR_EL0: return "CTR_EL0";
660 case MPIDR_EL1: return "MPIDR_EL1";
661 case DCZID_EL0: return "DCZID_EL0";
662 case MVFR0_EL1: return "MVFR0_EL1";
663 case MVFR1_EL1: return "MVFR1_EL1";
664 case ID_AA64PFR0_EL1: return "ID_AA64PFR0_EL1";
665 case ID_AA64PFR1_EL1: return "ID_AA64PFR1_EL1";
666 case ID_AA64DFR0_EL1: return "ID_AA64DFR0_EL1";
667 case ID_AA64DFR1_EL1: return "ID_AA64DFR1_EL1";
668 case ID_AA64ISAR0_EL1: return "ID_AA64ISAR0_EL1";
669 case ID_AA64ISAR1_EL1: return "ID_AA64ISAR1_EL1";
670 case ID_AA64MMFR0_EL1: return "ID_AA64MMFR0_EL1";
671 case ID_AA64MMFR1_EL1: return "ID_AA64MMFR1_EL1";
672 case CCSIDR_EL1: return "CCSIDR_EL1";
673 case CLIDR_EL1: return "CLIDR_EL1";
674 case AIDR_EL1: return "AIDR_EL1";
675 case CSSELR_EL1: return "CSSELR_EL1";
676 case VPIDR_EL2: return "VPIDR_EL2";
677 case VMPIDR_EL2: return "VMPIDR_EL2";
678 case SCTLR_EL1: return "SCTLR_EL1";
679 case SCTLR_EL2: return "SCTLR_EL2";
680 case SCTLR_EL3: return "SCTLR_EL3";
681 case ACTLR_EL1: return "ACTLR_EL1";
682 case ACTLR_EL2: return "ACTLR_EL2";
683 case ACTLR_EL3: return "ACTLR_EL3";
684 case CPACR_EL1: return "CPACR_EL1";
685 case CPTR_EL2: return "CPTR_EL2";
686 case CPTR_EL3: return "CPTR_EL3";
687 case SCR_EL3: return "SCR_EL3";
688 case HCR_EL2: return "HCR_EL2";
689 case MDCR_EL2: return "MDCR_EL2";
690 case MDCR_EL3: return "MDCR_EL3";
691 case HSTR_EL2: return "HSTR_EL2";
692 case HACR_EL2: return "HACR_EL2";
693 case TTBR0_EL1: return "TTBR0_EL1";
694 case TTBR1_EL1: return "TTBR1_EL1";
695 case TTBR0_EL2: return "TTBR0_EL2";
696 case TTBR0_EL3: return "TTBR0_EL3";
697 case VTTBR_EL2: return "VTTBR_EL2";
698 case TCR_EL1: return "TCR_EL1";
699 case TCR_EL2: return "TCR_EL2";
700 case TCR_EL3: return "TCR_EL3";
701 case VTCR_EL2: return "VTCR_EL2";
702 case ADFSR_EL2: return "ADFSR_EL2";
703 case AIFSR_EL2: return "AIFSR_EL2";
704 case ADFSR_EL3: return "ADFSR_EL3";
705 case AIFSR_EL3: return "AIFSR_EL3";
706 case ESR_EL1: return "ESR_EL1";
707 case ESR_EL2: return "ESR_EL2";
708 case ESR_EL3: return "ESR_EL3";
709 case FAR_EL1: return "FAR_EL1";
710 case FAR_EL2: return "FAR_EL2";
711 case FAR_EL3: return "FAR_EL3";
712 case HPFAR_EL2: return "HPFAR_EL2";
713 case PAR_EL1: return "PAR_EL1";
714 case MAIR_EL1: return "MAIR_EL1";
715 case MAIR_EL2: return "MAIR_EL2";
716 case MAIR_EL3: return "MAIR_EL3";
717 case AMAIR_EL1: return "AMAIR_EL1";
718 case AMAIR_EL2: return "AMAIR_EL2";
719 case AMAIR_EL3: return "AMAIR_EL3";
720 case VBAR_EL1: return "VBAR_EL1";
721 case VBAR_EL2: return "VBAR_EL2";
722 case VBAR_EL3: return "VBAR_EL3";
723 case RVBAR_EL1: return "RVBAR_EL1";
724 case RVBAR_EL2: return "RVBAR_EL2";
725 case RVBAR_EL3: return "RVBAR_EL3";
726 case ISR_EL1: return "ISR_EL1";
727 case CONTEXTIDR_EL1: return "CONTEXTIDR_EL1";
728 case TPIDR_EL0: return "TPIDR_EL0";
729 case TPIDRRO_EL0: return "TPIDRRO_EL0";
730 case TPIDR_EL1: return "TPIDR_EL1";
731 case TPIDR_EL2: return "TPIDR_EL2";
732 case TPIDR_EL3: return "TPIDR_EL3";
733 case TEECR32_EL1: return "TEECR32_EL1";
734 case CNTFRQ_EL0: return "CNTFRQ_EL0";
735 case CNTPCT_EL0: return "CNTPCT_EL0";
736 case CNTVCT_EL0: return "CNTVCT_EL0";
737 case CNTVOFF_EL2: return "CNTVOFF_EL2";
738 case CNTKCTL_EL1: return "CNTKCTL_EL1";
739 case CNTHCTL_EL2: return "CNTHCTL_EL2";
740 case CNTP_TVAL_EL0: return "CNTP_TVAL_EL0";
741 case CNTP_CTL_EL0: return "CNTP_CTL_EL0";
742 case CNTP_CVAL_EL0: return "CNTP_CVAL_EL0";
743 case CNTV_TVAL_EL0: return "CNTV_TVAL_EL0";
744 case CNTV_CTL_EL0: return "CNTV_CTL_EL0";
745 case CNTV_CVAL_EL0: return "CNTV_CVAL_EL0";
746 case CNTHP_TVAL_EL2: return "CNTHP_TVAL_EL2";
747 case CNTHP_CTL_EL2: return "CNTHP_CTL_EL2";
748 case CNTHP_CVAL_EL2: return "CNTHP_CVAL_EL2";
749 case CNTPS_TVAL_EL1: return "CNTPS_TVAL_EL1";
750 case CNTPS_CTL_EL1: return "CNTPS_CTL_EL1";
751 case CNTPS_CVAL_EL1: return "CNTPS_CVAL_EL1";
752 case DACR32_EL2: return "DACR32_EL2";
753 case IFSR32_EL2: return "IFSR32_EL2";
754 case TEEHBR32_EL1: return "TEEHBR32_EL1";
755 case SDER32_EL3: return "SDER32_EL3";
756 case FPEXC32_EL2: return "FPEXC32_EL2";
757 case PMEVCNTR0_EL0: return "PMEVCNTR0_EL0";
758 case PMEVCNTR1_EL0: return "PMEVCNTR1_EL0";
759 case PMEVCNTR2_EL0: return "PMEVCNTR2_EL0";
760 case PMEVCNTR3_EL0: return "PMEVCNTR3_EL0";
761 case PMEVCNTR4_EL0: return "PMEVCNTR4_EL0";
762 case PMEVCNTR5_EL0: return "PMEVCNTR5_EL0";
763 case PMEVCNTR6_EL0: return "PMEVCNTR6_EL0";
764 case PMEVCNTR7_EL0: return "PMEVCNTR7_EL0";
765 case PMEVCNTR8_EL0: return "PMEVCNTR8_EL0";
766 case PMEVCNTR9_EL0: return "PMEVCNTR9_EL0";
767 case PMEVCNTR10_EL0: return "PMEVCNTR10_EL0";
768 case PMEVCNTR11_EL0: return "PMEVCNTR11_EL0";
769 case PMEVCNTR12_EL0: return "PMEVCNTR12_EL0";
770 case PMEVCNTR13_EL0: return "PMEVCNTR13_EL0";
771 case PMEVCNTR14_EL0: return "PMEVCNTR14_EL0";
772 case PMEVCNTR15_EL0: return "PMEVCNTR15_EL0";
773 case PMEVCNTR16_EL0: return "PMEVCNTR16_EL0";
774 case PMEVCNTR17_EL0: return "PMEVCNTR17_EL0";
775 case PMEVCNTR18_EL0: return "PMEVCNTR18_EL0";
776 case PMEVCNTR19_EL0: return "PMEVCNTR19_EL0";
777 case PMEVCNTR20_EL0: return "PMEVCNTR20_EL0";
778 case PMEVCNTR21_EL0: return "PMEVCNTR21_EL0";
779 case PMEVCNTR22_EL0: return "PMEVCNTR22_EL0";
780 case PMEVCNTR23_EL0: return "PMEVCNTR23_EL0";
781 case PMEVCNTR24_EL0: return "PMEVCNTR24_EL0";
782 case PMEVCNTR25_EL0: return "PMEVCNTR25_EL0";
783 case PMEVCNTR26_EL0: return "PMEVCNTR26_EL0";
784 case PMEVCNTR27_EL0: return "PMEVCNTR27_EL0";
785 case PMEVCNTR28_EL0: return "PMEVCNTR28_EL0";
786 case PMEVCNTR29_EL0: return "PMEVCNTR29_EL0";
787 case PMEVCNTR30_EL0: return "PMEVCNTR30_EL0";
788 case PMEVTYPER0_EL0: return "PMEVTYPER0_EL0";
789 case PMEVTYPER1_EL0: return "PMEVTYPER1_EL0";
790 case PMEVTYPER2_EL0: return "PMEVTYPER2_EL0";
791 case PMEVTYPER3_EL0: return "PMEVTYPER3_EL0";
792 case PMEVTYPER4_EL0: return "PMEVTYPER4_EL0";
793 case PMEVTYPER5_EL0: return "PMEVTYPER5_EL0";
794 case PMEVTYPER6_EL0: return "PMEVTYPER6_EL0";
795 case PMEVTYPER7_EL0: return "PMEVTYPER7_EL0";
796 case PMEVTYPER8_EL0: return "PMEVTYPER8_EL0";
797 case PMEVTYPER9_EL0: return "PMEVTYPER9_EL0";
798 case PMEVTYPER10_EL0: return "PMEVTYPER10_EL0";
799 case PMEVTYPER11_EL0: return "PMEVTYPER11_EL0";
800 case PMEVTYPER12_EL0: return "PMEVTYPER12_EL0";
801 case PMEVTYPER13_EL0: return "PMEVTYPER13_EL0";
802 case PMEVTYPER14_EL0: return "PMEVTYPER14_EL0";
803 case PMEVTYPER15_EL0: return "PMEVTYPER15_EL0";
804 case PMEVTYPER16_EL0: return "PMEVTYPER16_EL0";
805 case PMEVTYPER17_EL0: return "PMEVTYPER17_EL0";
806 case PMEVTYPER18_EL0: return "PMEVTYPER18_EL0";
807 case PMEVTYPER19_EL0: return "PMEVTYPER19_EL0";
808 case PMEVTYPER20_EL0: return "PMEVTYPER20_EL0";
809 case PMEVTYPER21_EL0: return "PMEVTYPER21_EL0";
810 case PMEVTYPER22_EL0: return "PMEVTYPER22_EL0";
811 case PMEVTYPER23_EL0: return "PMEVTYPER23_EL0";
812 case PMEVTYPER24_EL0: return "PMEVTYPER24_EL0";
813 case PMEVTYPER25_EL0: return "PMEVTYPER25_EL0";
814 case PMEVTYPER26_EL0: return "PMEVTYPER26_EL0";
815 case PMEVTYPER27_EL0: return "PMEVTYPER27_EL0";
816 case PMEVTYPER28_EL0: return "PMEVTYPER28_EL0";
817 case PMEVTYPER29_EL0: return "PMEVTYPER29_EL0";
818 case PMEVTYPER30_EL0: return "PMEVTYPER30_EL0";
819 case PMCCFILTR_EL0: return "PMCCFILTR_EL0";
820 case RMR_EL3: return "RMR_EL3";
821 case RMR_EL2: return "RMR_EL2";
822 case RMR_EL1: return "RMR_EL1";
823 case CPM_IOACC_CTL_EL3: return "CPM_IOACC_CTL_EL3";
824 case MDCCSR_EL0: return "MDCCSR_EL0";
825 case MDCCINT_EL1: return "MDCCINT_EL1";
826 case DBGDTR_EL0: return "DBGDTR_EL0";
827 case DBGDTRRX_EL0: return "DBGDTRRX_EL0";
828 case DBGVCR32_EL2: return "DBGVCR32_EL2";
829 case OSDTRRX_EL1: return "OSDTRRX_EL1";
830 case MDSCR_EL1: return "MDSCR_EL1";
831 case OSDTRTX_EL1: return "OSDTRTX_EL1";
832 case OSECCR_EL11: return "OSECCR_EL11";
833 case DBGBVR0_EL1: return "DBGBVR0_EL1";
834 case DBGBVR1_EL1: return "DBGBVR1_EL1";
835 case DBGBVR2_EL1: return "DBGBVR2_EL1";
836 case DBGBVR3_EL1: return "DBGBVR3_EL1";
837 case DBGBVR4_EL1: return "DBGBVR4_EL1";
838 case DBGBVR5_EL1: return "DBGBVR5_EL1";
839 case DBGBVR6_EL1: return "DBGBVR6_EL1";
840 case DBGBVR7_EL1: return "DBGBVR7_EL1";
841 case DBGBVR8_EL1: return "DBGBVR8_EL1";
842 case DBGBVR9_EL1: return "DBGBVR9_EL1";
843 case DBGBVR10_EL1: return "DBGBVR10_EL1";
844 case DBGBVR11_EL1: return "DBGBVR11_EL1";
845 case DBGBVR12_EL1: return "DBGBVR12_EL1";
846 case DBGBVR13_EL1: return "DBGBVR13_EL1";
847 case DBGBVR14_EL1: return "DBGBVR14_EL1";
848 case DBGBVR15_EL1: return "DBGBVR15_EL1";
849 case DBGBCR0_EL1: return "DBGBCR0_EL1";
850 case DBGBCR1_EL1: return "DBGBCR1_EL1";
851 case DBGBCR2_EL1: return "DBGBCR2_EL1";
852 case DBGBCR3_EL1: return "DBGBCR3_EL1";
853 case DBGBCR4_EL1: return "DBGBCR4_EL1";
854 case DBGBCR5_EL1: return "DBGBCR5_EL1";
855 case DBGBCR6_EL1: return "DBGBCR6_EL1";
856 case DBGBCR7_EL1: return "DBGBCR7_EL1";
857 case DBGBCR8_EL1: return "DBGBCR8_EL1";
858 case DBGBCR9_EL1: return "DBGBCR9_EL1";
859 case DBGBCR10_EL1: return "DBGBCR10_EL1";
860 case DBGBCR11_EL1: return "DBGBCR11_EL1";
861 case DBGBCR12_EL1: return "DBGBCR12_EL1";
862 case DBGBCR13_EL1: return "DBGBCR13_EL1";
863 case DBGBCR14_EL1: return "DBGBCR14_EL1";
864 case DBGBCR15_EL1: return "DBGBCR15_EL1";
865 case DBGWVR0_EL1: return "DBGWVR0_EL1";
866 case DBGWVR1_EL1: return "DBGWVR1_EL1";
867 case DBGWVR2_EL1: return "DBGWVR2_EL1";
868 case DBGWVR3_EL1: return "DBGWVR3_EL1";
869 case DBGWVR4_EL1: return "DBGWVR4_EL1";
870 case DBGWVR5_EL1: return "DBGWVR5_EL1";
871 case DBGWVR6_EL1: return "DBGWVR6_EL1";
872 case DBGWVR7_EL1: return "DBGWVR7_EL1";
873 case DBGWVR8_EL1: return "DBGWVR8_EL1";
874 case DBGWVR9_EL1: return "DBGWVR9_EL1";
875 case DBGWVR10_EL1: return "DBGWVR10_EL1";
876 case DBGWVR11_EL1: return "DBGWVR11_EL1";
877 case DBGWVR12_EL1: return "DBGWVR12_EL1";
878 case DBGWVR13_EL1: return "DBGWVR13_EL1";
879 case DBGWVR14_EL1: return "DBGWVR14_EL1";
880 case DBGWVR15_EL1: return "DBGWVR15_EL1";
881 case DBGWCR0_EL1: return "DBGWCR0_EL1";
882 case DBGWCR1_EL1: return "DBGWCR1_EL1";
883 case DBGWCR2_EL1: return "DBGWCR2_EL1";
884 case DBGWCR3_EL1: return "DBGWCR3_EL1";
885 case DBGWCR4_EL1: return "DBGWCR4_EL1";
886 case DBGWCR5_EL1: return "DBGWCR5_EL1";
887 case DBGWCR6_EL1: return "DBGWCR6_EL1";
888 case DBGWCR7_EL1: return "DBGWCR7_EL1";
889 case DBGWCR8_EL1: return "DBGWCR8_EL1";
890 case DBGWCR9_EL1: return "DBGWCR9_EL1";
891 case DBGWCR10_EL1: return "DBGWCR10_EL1";
892 case DBGWCR11_EL1: return "DBGWCR11_EL1";
893 case DBGWCR12_EL1: return "DBGWCR12_EL1";
894 case DBGWCR13_EL1: return "DBGWCR13_EL1";
895 case DBGWCR14_EL1: return "DBGWCR14_EL1";
896 case DBGWCR15_EL1: return "DBGWCR15_EL1";
897 case MDRAR_EL1: return "MDRAR_EL1";
898 case OSLAR_EL1: return "OSLAR_EL1";
899 case OSLSR_EL1: return "OSLSR_EL1";
900 case OSDLR_EL1: return "OSDLR_EL1";
901 case DBGPRCR_EL1: return "DBGPRCR_EL1";
902 case DBGCLAIMSET_EL1: return "DBGCLAIMSET_EL1";
903 case DBGCLAIMCLR_EL1: return "DBGCLAIMCLR_EL1";
904 case DBGAUTHSTATUS_EL1: return "DBGAUTHSTATUS_EL1";
905 case DBGDEVID2: return "DBGDEVID2";
906 case DBGDEVID1: return "DBGDEVID1";
907 case DBGDEVID0: return "DBGDEVID0";
908 case ID_PFR0_EL1: return "ID_PFR0_EL1";
909 case ID_PFR1_EL1: return "ID_PFR1_EL1";
910 case ID_DFR0_EL1: return "ID_DFR0_EL1";
911 case ID_AFR0_EL1: return "ID_AFR0_EL1";
912 case ID_ISAR0_EL1: return "ID_ISAR0_EL1";
913 case ID_ISAR1_EL1: return "ID_ISAR1_EL1";
914 case ID_ISAR2_EL1: return "ID_ISAR2_EL1";
915 case ID_ISAR3_EL1: return "ID_ISAR3_EL1";
916 case ID_ISAR4_EL1: return "ID_ISAR4_EL1";
917 case ID_ISAR5_EL1: return "ID_ISAR5_EL1";
918 case AFSR1_EL1: return "AFSR1_EL1";
919 case AFSR0_EL1: return "AFSR0_EL1";
920 case REVIDR_EL1: return "REVIDR_EL1";
921 }
922}
923
924enum CPSRField {
925 InvalidCPSRField = 0xff,
926 cpsr_SPSel = 0x5,
927 cpsr_DAIFSet = 0x1e,
928 cpsr_DAIFClr = 0x1f
929};
930
931static inline const char *getCPSRFieldName(CPSRField Val) {
932 switch(Val) {
933 default: assert(0 && "Invalid system register value!");
934 case cpsr_SPSel: return "SPSel";
935 case cpsr_DAIFSet: return "DAIFSet";
936 case cpsr_DAIFClr: return "DAIFClr";
937 }
938}
939
940} // end namespace ARM64SYS
941
942namespace ARM64II {
943 /// Target Operand Flag enum.
944 enum TOF {
945 //===------------------------------------------------------------------===//
946 // ARM64 Specific MachineOperand flags.
947
948 MO_NO_FLAG,
949
950 MO_FRAGMENT = 0x7,
951
952 /// MO_PAGE - A symbol operand with this flag represents the pc-relative
953 /// offset of the 4K page containing the symbol. This is used with the
954 /// ADRP instruction.
955 MO_PAGE = 1,
956
957 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
958 /// that symbol within a 4K page. This offset is added to the page address
959 /// to produce the complete address.
960 MO_PAGEOFF = 2,
961
962 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
963 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
964 MO_G3 = 3,
965
966 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
967 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
968 MO_G2 = 4,
969
970 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
971 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
972 MO_G1 = 5,
973
974 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
975 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
976 MO_G0 = 6,
977
978 /// MO_GOT - This flag indicates that a symbol operand represents the
979 /// address of the GOT entry for the symbol, rather than the address of
980 /// the symbol itself.
981 MO_GOT = 8,
982
983 /// MO_NC - Indicates whether the linker is expected to check the symbol
984 /// reference for overflow. For example in an ADRP/ADD pair of relocations
985 /// the ADRP usually does check, but not the ADD.
986 MO_NC = 0x10,
987
988 /// MO_TLS - Indicates that the operand being accessed is some kind of
989 /// thread-local symbol. On Darwin, only one type of thread-local access
990 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
991 /// referee will affect interpretation.
992 MO_TLS = 0x20
993 };
994} // end namespace ARM64II
995
996} // end namespace llvm
997
998#endif