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gerrit-public.fairphone.software / toolchain / llvm-project / 0125f2a6e4537576b5383bcac32e0278d184467a / . / llvm / test / CodeGen / R600 / store.ll
blob: f8c6f8414c030ebf273bfa2aa2a00d73b14790c3 [file] [log] [blame]
Tom Stellard754f80f2013-04-05 23:31:51 +0000[diff] [blame]1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s
Tom Stellard6aa0d552013-06-14 22:12:24 +0000[diff] [blame]2; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s
Tom Stellard754f80f2013-04-05 23:31:51 +0000[diff] [blame]3; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s
4
Tom Stellard5a6b0d82013-04-19 02:10:53 +0000[diff] [blame]5; floating-point store
6; EG-CHECK: @store_f32
Tom Stellard754f80f2013-04-05 23:31:51 +0000[diff] [blame]7; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1
Tom Stellard6aa0d552013-06-14 22:12:24 +0000[diff] [blame]8; CM-CHECK: @store_f32
9; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}}
Tom Stellard5a6b0d82013-04-19 02:10:53 +0000[diff] [blame]10; SI-CHECK: @store_f32
Tom Stellard754f80f2013-04-05 23:31:51 +0000[diff] [blame]11; SI-CHECK: BUFFER_STORE_DWORD
12
Tom Stellard5a6b0d82013-04-19 02:10:53 +0000[diff] [blame]13define void @store_f32(float addrspace(1)* %out, float %in) {
Tom Stellard754f80f2013-04-05 23:31:51 +0000[diff] [blame]14 store float %in, float addrspace(1)* %out
15 ret void
16}
Tom Stellard0125f2a2013-06-25 02:39:35 +0000[diff] [blame^]17
18; The stores in this function are combined by the optimizer to create a
19; 64-bit store with 32-bit alignment. This is legal for SI and the legalizer
20; should not try to split the 64-bit store back into 2 32-bit stores.
21;
22; Evergreen / Northern Islands don't support 64-bit stores yet, so there should
23; be two 32-bit stores.
24
25; EG-CHECK: @vecload2
26; EG-CHECK: RAT_WRITE_CACHELESS_32_eg
27; EG-CHECK: RAT_WRITE_CACHELESS_32_eg
28; CM-CHECK: @vecload2
29; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD
30; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD
31; SI-CHECK: @vecload2
32; SI-CHECK: BUFFER_STORE_DWORDX2
33define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
34entry:
35 %0 = load i32 addrspace(2)* %mem, align 4, !tbaa !5
36 %arrayidx1.i = getelementptr inbounds i32 addrspace(2)* %mem, i64 1
37 %1 = load i32 addrspace(2)* %arrayidx1.i, align 4, !tbaa !5
38 store i32 %0, i32 addrspace(1)* %out, align 4, !tbaa !5
39 %arrayidx1 = getelementptr inbounds i32 addrspace(1)* %out, i64 1
40 store i32 %1, i32 addrspace(1)* %arrayidx1, align 4, !tbaa !5
41 ret void
42}
43
44attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
45
46!5 = metadata !{metadata !"int", metadata !6}
47!6 = metadata !{metadata !"omnipotent char", metadata !7}
48!7 = metadata !{metadata !"Simple C/C++ TBAA"}