blob: f2486c65d3a2bb09a6bba54cc85fb8099b09c6ec [file] [log] [blame]
Edward O'Callaghan21d7e8a2009-11-22 14:23:33 +00001; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2
Evan Cheng2d59ee32010-11-12 20:32:20 +00002; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON
3; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
Bob Wilson0858c3a2011-04-19 18:11:57 +00004; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=A9
5; RUN: llc < %s -mtriple=arm-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s -check-prefix=HARD
David Goodwin3b9c52c2009-08-04 17:53:06 +00006
Evan Cheng2d59ee32010-11-12 20:32:20 +00007define float @t1(float %acc, float %a, float %b) {
David Goodwin3b9c52c2009-08-04 17:53:06 +00008entry:
Stephen Lind24ab202013-07-14 06:24:09 +00009; VFP2-LABEL: t1:
Evan Cheng2d59ee32010-11-12 20:32:20 +000010; VFP2: vmla.f32
11
Stephen Lind24ab202013-07-14 06:24:09 +000012; NEON-LABEL: t1:
Evan Cheng2d59ee32010-11-12 20:32:20 +000013; NEON: vmla.f32
14
Stephen Lind24ab202013-07-14 06:24:09 +000015; A8-LABEL: t1:
Evan Cheng2d59ee32010-11-12 20:32:20 +000016; A8: vmul.f32
17; A8: vadd.f32
David Goodwin3b9c52c2009-08-04 17:53:06 +000018 %0 = fmul float %a, %b
19 %1 = fadd float %acc, %0
20 ret float %1
21}
22
Evan Cheng2d59ee32010-11-12 20:32:20 +000023define double @t2(double %acc, double %a, double %b) {
24entry:
Stephen Lind24ab202013-07-14 06:24:09 +000025; VFP2-LABEL: t2:
Evan Cheng2d59ee32010-11-12 20:32:20 +000026; VFP2: vmla.f64
Edward O'Callaghan21d7e8a2009-11-22 14:23:33 +000027
Stephen Lind24ab202013-07-14 06:24:09 +000028; NEON-LABEL: t2:
Evan Cheng2d59ee32010-11-12 20:32:20 +000029; NEON: vmla.f64
Edward O'Callaghan21d7e8a2009-11-22 14:23:33 +000030
Stephen Lind24ab202013-07-14 06:24:09 +000031; A8-LABEL: t2:
Evan Cheng2d59ee32010-11-12 20:32:20 +000032; A8: vmul.f64
33; A8: vadd.f64
34 %0 = fmul double %a, %b
35 %1 = fadd double %acc, %0
36 ret double %1
37}
38
39define float @t3(float %acc, float %a, float %b) {
40entry:
Stephen Lind24ab202013-07-14 06:24:09 +000041; VFP2-LABEL: t3:
Evan Cheng2d59ee32010-11-12 20:32:20 +000042; VFP2: vmla.f32
43
Stephen Lind24ab202013-07-14 06:24:09 +000044; NEON-LABEL: t3:
Evan Cheng2d59ee32010-11-12 20:32:20 +000045; NEON: vmla.f32
46
Stephen Lind24ab202013-07-14 06:24:09 +000047; A8-LABEL: t3:
Evan Cheng2d59ee32010-11-12 20:32:20 +000048; A8: vmul.f32
49; A8: vadd.f32
50 %0 = fmul float %a, %b
51 %1 = fadd float %0, %acc
52 ret float %1
53}
Bob Wilson0858c3a2011-04-19 18:11:57 +000054
55; It's possible to make use of fp vmla / vmls on Cortex-A9.
56; rdar://8659675
57define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, float* %P1, float* %P2) {
58entry:
Stephen Lind24ab202013-07-14 06:24:09 +000059; A8-LABEL: t4:
Bob Wilson0858c3a2011-04-19 18:11:57 +000060; A8: vmul.f32
61; A8: vmul.f32
62; A8: vadd.f32
63; A8: vadd.f32
64
65; Two vmla with now RAW hazard
Stephen Lind24ab202013-07-14 06:24:09 +000066; A9-LABEL: t4:
Bob Wilson0858c3a2011-04-19 18:11:57 +000067; A9: vmla.f32
68; A9: vmla.f32
69
Stephen Lind24ab202013-07-14 06:24:09 +000070; HARD-LABEL: t4:
Bob Wilson0858c3a2011-04-19 18:11:57 +000071; HARD: vmla.f32 s0, s1, s2
72; HARD: vmla.f32 s3, s1, s4
73 %0 = fmul float %a, %b
74 %1 = fadd float %acc1, %0
75 %2 = fmul float %a, %c
76 %3 = fadd float %acc2, %2
77 store float %1, float* %P1
78 store float %3, float* %P2
79 ret void
80}
81
82define float @t5(float %a, float %b, float %c, float %d, float %e) {
83entry:
Stephen Lind24ab202013-07-14 06:24:09 +000084; A8-LABEL: t5:
Bob Wilson0858c3a2011-04-19 18:11:57 +000085; A8: vmul.f32
86; A8: vmul.f32
87; A8: vadd.f32
88; A8: vadd.f32
89
Stephen Lind24ab202013-07-14 06:24:09 +000090; A9-LABEL: t5:
Bob Wilson0858c3a2011-04-19 18:11:57 +000091; A9: vmla.f32
92; A9: vmul.f32
93; A9: vadd.f32
94
Stephen Lind24ab202013-07-14 06:24:09 +000095; HARD-LABEL: t5:
Bob Wilson0858c3a2011-04-19 18:11:57 +000096; HARD: vmla.f32 s4, s0, s1
97; HARD: vmul.f32 s0, s2, s3
98; HARD: vadd.f32 s0, s4, s0
99 %0 = fmul float %a, %b
100 %1 = fadd float %e, %0
101 %2 = fmul float %c, %d
102 %3 = fadd float %1, %2
103 ret float %3
104}