| Krzysztof Parzyszek | 046090d | 2018-03-12 14:01:28 +0000 | [diff] [blame^] | 1 | ; RUN: llc -march=hexagon -mno-pairing -mno-compound < %s |
| 2 | ; REQUIRES: asserts |
| 3 | |
| 4 | ; Test that the SWP doesn't assert when generating new phis. In this example, a |
| 5 | ; phi references another phi and phi as well as the phi loop value are all |
| 6 | ; defined in different stages. |
| 7 | ; v3 = stage 2 |
| 8 | ; v2 = phi(vb, v3) stage 1 |
| 9 | ; v1 = phi(va, v2) stage 0 |
| 10 | |
| 11 | ; Function Attrs: nounwind |
| 12 | define void @f0() #0 { |
| 13 | b0: |
| 14 | br label %b1 |
| 15 | |
| 16 | b1: ; preds = %b1, %b0 |
| 17 | br i1 undef, label %b2, label %b1 |
| 18 | |
| 19 | b2: ; preds = %b1 |
| 20 | br label %b3 |
| 21 | |
| 22 | b3: ; preds = %b3, %b2 |
| 23 | br i1 undef, label %b3, label %b4 |
| 24 | |
| 25 | b4: ; preds = %b4, %b3 |
| 26 | %v0 = phi i32 [ %v17, %b4 ], [ undef, %b3 ] |
| 27 | %v1 = phi i64 [ %v13, %b4 ], [ undef, %b3 ] |
| 28 | %v2 = phi i32 [ %v19, %b4 ], [ undef, %b3 ] |
| 29 | %v3 = phi i32 [ %v4, %b4 ], [ undef, %b3 ] |
| 30 | %v4 = phi i32 [ %v14, %b4 ], [ undef, %b3 ] |
| 31 | %v5 = phi i32 [ %v18, %b4 ], [ undef, %b3 ] |
| 32 | %v6 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v3, i32 %v3) |
| 33 | %v7 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v0, i32 undef) |
| 34 | %v8 = tail call i64 @llvm.hexagon.S2.valignib(i64 %v7, i64 undef, i32 2) |
| 35 | %v9 = inttoptr i32 %v5 to i16* |
| 36 | %v10 = load i16, i16* %v9, align 2, !tbaa !0 |
| 37 | %v11 = sext i16 %v10 to i32 |
| 38 | %v12 = add nsw i32 %v5, -8 |
| 39 | %v13 = tail call i64 @llvm.hexagon.M2.vdmacs.s0(i64 %v1, i64 %v6, i64 %v8) |
| 40 | %v14 = tail call i32 @llvm.hexagon.A2.combine.ll(i32 %v11, i32 %v0) |
| 41 | %v15 = inttoptr i32 %v12 to i16* |
| 42 | %v16 = load i16, i16* %v15, align 2, !tbaa !0 |
| 43 | %v17 = sext i16 %v16 to i32 |
| 44 | %v18 = add nsw i32 %v5, -16 |
| 45 | %v19 = add nsw i32 %v2, 1 |
| 46 | %v20 = icmp eq i32 %v19, 0 |
| 47 | br i1 %v20, label %b5, label %b4 |
| 48 | |
| 49 | b5: ; preds = %b4 |
| 50 | %v21 = phi i64 [ %v13, %b4 ] |
| 51 | unreachable |
| 52 | } |
| 53 | |
| 54 | ; Function Attrs: nounwind readnone |
| 55 | declare i32 @llvm.hexagon.A2.combine.ll(i32, i32) #1 |
| 56 | |
| 57 | ; Function Attrs: nounwind readnone |
| 58 | declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 |
| 59 | |
| 60 | ; Function Attrs: nounwind readnone |
| 61 | declare i64 @llvm.hexagon.M2.vdmacs.s0(i64, i64, i64) #1 |
| 62 | |
| 63 | ; Function Attrs: nounwind readnone |
| 64 | declare i64 @llvm.hexagon.S2.valignib(i64, i64, i32) #1 |
| 65 | |
| 66 | attributes #0 = { nounwind "target-cpu"="hexagonv60" } |
| 67 | attributes #1 = { nounwind readnone } |
| 68 | |
| 69 | !0 = !{!1, !1, i64 0} |
| 70 | !1 = !{!"short", !2, i64 0} |
| 71 | !2 = !{!"omnipotent char", !3, i64 0} |
| 72 | !3 = !{!"Simple C/C++ TBAA"} |