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Krzysztof Parzyszek04c07962016-08-04 17:56:19 +00001; RUN: llc -march=hexagon < %s | FileCheck %s
2
3; Make sure we don't generate zxtb to transfer a predicate register into
4; a general purpose register.
5
6; CHECK: r0 = p0
7; CHECK-NOT: zxtb(p
8
9target triple = "hexagon"
10
11; Function Attrs: nounwind
12define i32 @fred() local_unnamed_addr #0 {
13entry:
14 %0 = tail call i32 @llvm.hexagon.C4.and.and(i32 undef, i32 undef, i32 undef)
15 ret i32 %0
16}
17
18declare i32 @llvm.hexagon.C4.and.and(i32, i32, i32) #1
19
20attributes #0 = { nounwind "target-cpu"="hexagonv5" }
21attributes #1 = { nounwind readnone }