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gerrit-public.fairphone.software / toolchain / llvm-project / 061d1ea5da88ccb6ded3b573e4d7325a6ea83069 / . / llvm / lib / Target / Mips / Mips64InstrInfo.td
blob: 494ba87b401dd134213570bd74e5eed7e2b25a94 [file] [log] [blame]
Akira Hatanaka7d7ee0c2011-09-24 01:40:18 +0000[diff] [blame]1//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes Mips64 instructions.
11//
12//===----------------------------------------------------------------------===//
Akira Hatanakac1179672011-09-28 17:50:27 +0000[diff] [blame]13
14//===----------------------------------------------------------------------===//
Akira Hatanaka7769a772011-09-30 02:08:54 +0000[diff] [blame]15// Mips Operand, Complex Patterns and Transformations Definitions.
16//===----------------------------------------------------------------------===//
17
18// Instruction operand types
Akira Hatanaka61e256a2011-09-30 03:18:46 +0000[diff] [blame]19def shamt_64 : Operand<i64>;
Akira Hatanaka7769a772011-09-30 02:08:54 +0000[diff] [blame]20
21// Unsigned Operand
22def uimm16_64 : Operand<i64> {
23 let PrintMethod = "printUnsignedImm";
24}
25
Akira Hatanaka61e256a2011-09-30 03:18:46 +0000[diff] [blame]26// Transformation Function - get Imm - 32.
27def Subtract32 : SDNodeXForm<imm, [{
Akira Hatanaka4a04a562011-12-07 20:10:24 +0000[diff] [blame]28 return getImm(N, (unsigned)N->getZExtValue() - 32);
Akira Hatanaka61e256a2011-09-30 03:18:46 +0000[diff] [blame]29}]>;
30
Akira Hatanaka2a232d82011-12-19 19:44:09 +0000[diff] [blame]31// shamt must fit in 6 bits.
32def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
Akira Hatanaka61e256a2011-09-30 03:18:46 +0000[diff] [blame]33
Akira Hatanaka7769a772011-09-30 02:08:54 +0000[diff] [blame]34//===----------------------------------------------------------------------===//
Akira Hatanaka36036412011-09-29 20:37:56 +0000[diff] [blame]35// Instructions specific format
36//===----------------------------------------------------------------------===//
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]37let DecoderNamespace = "Mips64" in {
Akira Hatanaka61e256a2011-09-30 03:18:46 +0000[diff] [blame]38
Akira Hatanakab1527b72012-12-20 04:20:09 +0000[diff] [blame]39multiclass Atomic2Ops64<PatFrag Op> {
Craig Toppera8c5ec02013-01-07 05:45:56 +0000[diff] [blame]40 def NAME : Atomic2Ops<Op, CPU64Regs, CPURegs>,
41 Requires<[NotN64, HasStdEnc]>;
42 def _P8 : Atomic2Ops<Op, CPU64Regs, CPU64Regs>,
43 Requires<[IsN64, HasStdEnc]> {
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]44 let isCodeGenOnly = 1;
45 }
Akira Hatanaka21cbc252011-11-11 04:14:30 +0000[diff] [blame]46}
47
Akira Hatanakab1527b72012-12-20 04:20:09 +0000[diff] [blame]48multiclass AtomicCmpSwap64<PatFrag Op> {
Craig Toppera8c5ec02013-01-07 05:45:56 +0000[diff] [blame]49 def NAME : AtomicCmpSwap<Op, CPU64Regs, CPURegs>,
50 Requires<[NotN64, HasStdEnc]>;
51 def _P8 : AtomicCmpSwap<Op, CPU64Regs, CPU64Regs>,
52 Requires<[IsN64, HasStdEnc]> {
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]53 let isCodeGenOnly = 1;
54 }
Akira Hatanaka21cbc252011-11-11 04:14:30 +0000[diff] [blame]55}
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]56}
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000[diff] [blame]57let usesCustomInserter = 1, Predicates = [HasStdEnc],
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]58 DecoderNamespace = "Mips64" in {
Akira Hatanakab1527b72012-12-20 04:20:09 +0000[diff] [blame]59 defm ATOMIC_LOAD_ADD_I64 : Atomic2Ops64<atomic_load_add_64>;
60 defm ATOMIC_LOAD_SUB_I64 : Atomic2Ops64<atomic_load_sub_64>;
61 defm ATOMIC_LOAD_AND_I64 : Atomic2Ops64<atomic_load_and_64>;
62 defm ATOMIC_LOAD_OR_I64 : Atomic2Ops64<atomic_load_or_64>;
63 defm ATOMIC_LOAD_XOR_I64 : Atomic2Ops64<atomic_load_xor_64>;
64 defm ATOMIC_LOAD_NAND_I64 : Atomic2Ops64<atomic_load_nand_64>;
65 defm ATOMIC_SWAP_I64 : Atomic2Ops64<atomic_swap_64>;
66 defm ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap64<atomic_cmp_swap_64>;
Akira Hatanaka21cbc252011-11-11 04:14:30 +0000[diff] [blame]67}
68
Akira Hatanaka36036412011-09-29 20:37:56 +0000[diff] [blame]69//===----------------------------------------------------------------------===//
70// Instruction definition
71//===----------------------------------------------------------------------===//
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]72let DecoderNamespace = "Mips64" in {
Akira Hatanaka7769a772011-09-30 02:08:54 +0000[diff] [blame]73/// Arithmetic Instructions (ALU Immediate)
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]74def DADDi : ArithLogicI<"daddi", simm16_64, CPU64RegsOpnd>, ADDI_FM<0x18>;
75def DADDiu : ArithLogicI<"daddiu", simm16_64, CPU64RegsOpnd, immSExt16, add>,
Akira Hatanakaab1b715b2012-12-20 03:40:03 +0000[diff] [blame]76 ADDI_FM<0x19>, IsAsCheapAsAMove;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]77def DANDi : ArithLogicI<"andi", uimm16_64, CPU64RegsOpnd, immZExt16, and>,
Akira Hatanakaab1b715b2012-12-20 03:40:03 +0000[diff] [blame]78 ADDI_FM<0xc>;
Akira Hatanakae7f1acc2012-12-20 04:27:52 +0000[diff] [blame]79def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, CPU64Regs>,
80 SLTI_FM<0xa>;
81def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, CPU64Regs>,
82 SLTI_FM<0xb>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]83def ORi64 : ArithLogicI<"ori", uimm16_64, CPU64RegsOpnd, immZExt16, or>,
Akira Hatanakaab1b715b2012-12-20 03:40:03 +0000[diff] [blame]84 ADDI_FM<0xd>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]85def XORi64 : ArithLogicI<"xori", uimm16_64, CPU64RegsOpnd, immZExt16, xor>,
Akira Hatanakaab1b715b2012-12-20 03:40:03 +0000[diff] [blame]86 ADDI_FM<0xe>;
Akira Hatanakae738efc2012-12-21 22:46:07 +0000[diff] [blame]87def LUi64 : LoadUpper<"lui", CPU64Regs, uimm16_64>, LUI_FM;
Akira Hatanaka7769a772011-09-30 02:08:54 +0000[diff] [blame]88
Akira Hatanaka36036412011-09-29 20:37:56 +0000[diff] [blame]89/// Arithmetic Instructions (3-Operand, R-Type)
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]90def DADD : ArithLogicR<"dadd", CPU64RegsOpnd>, ADD_FM<0, 0x2c>;
91def DADDu : ArithLogicR<"daddu", CPU64RegsOpnd, 1, IIAlu, add>,
92 ADD_FM<0, 0x2d>;
93def DSUBu : ArithLogicR<"dsubu", CPU64RegsOpnd, 0, IIAlu, sub>,
94 ADD_FM<0, 0x2f>;
Akira Hatanakae7f1acc2012-12-20 04:27:52 +0000[diff] [blame]95def SLT64 : SetCC_R<"slt", setlt, CPU64Regs>, ADD_FM<0, 0x2a>;
96def SLTu64 : SetCC_R<"sltu", setult, CPU64Regs>, ADD_FM<0, 0x2b>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]97def AND64 : ArithLogicR<"and", CPU64RegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>;
98def OR64 : ArithLogicR<"or", CPU64RegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>;
99def XOR64 : ArithLogicR<"xor", CPU64RegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
100def NOR64 : LogicNOR<"nor", CPU64RegsOpnd>, ADD_FM<0, 0x27>;
Akira Hatanaka61e256a2011-09-30 03:18:46 +0000[diff] [blame]101
102/// Shift Instructions
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]103def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>,
Akira Hatanakaf412e752013-01-04 19:25:46 +0000[diff] [blame]104 SRA_FM<0x38, 0>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]105def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>,
Akira Hatanakaf412e752013-01-04 19:25:46 +0000[diff] [blame]106 SRA_FM<0x3a, 0>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]107def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>,
Akira Hatanakaf412e752013-01-04 19:25:46 +0000[diff] [blame]108 SRA_FM<0x3b, 0>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]109def DSLLV : shift_rotate_reg<"dsllv", CPU64RegsOpnd, shl>, SRLV_FM<0x14, 0>;
110def DSRLV : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>;
111def DSRAV : shift_rotate_reg<"dsrav", CPU64RegsOpnd, sra>, SRLV_FM<0x17, 0>;
112def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>;
113def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>;
114def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>;
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]115}
Akira Hatanaka7ba8a8d2011-09-30 18:51:46 +0000[diff] [blame]116// Rotate Instructions
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000[diff] [blame]117let Predicates = [HasMips64r2, HasStdEnc],
Akira Hatanakacdf4fd82012-05-22 03:10:09 +0000[diff] [blame]118 DecoderNamespace = "Mips64" in {
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]119 def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]120 SRA_FM<0x3a, 1>;
121 def DROTRV : shift_rotate_reg<"drotrv", CPU64RegsOpnd, rotr>,
122 SRLV_FM<0x16, 1>;
Akira Hatanaka7ba8a8d2011-09-30 18:51:46 +0000[diff] [blame]123}
124
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]125let DecoderNamespace = "Mips64" in {
Akira Hatanakabe68f3c2011-10-11 00:27:28 +0000[diff] [blame]126/// Load and Store Instructions
Jia Liuf54f60f2012-02-28 07:46:26 +0000[diff] [blame]127/// aligned
Akira Hatanakaf412e752013-01-04 19:25:46 +0000[diff] [blame]128defm LB64 : LoadM<"lb", CPU64Regs, sextloadi8>, LW_FM<0x20>;
129defm LBu64 : LoadM<"lbu", CPU64Regs, zextloadi8>, LW_FM<0x24>;
130defm LH64 : LoadM<"lh", CPU64Regs, sextloadi16>, LW_FM<0x21>;
131defm LHu64 : LoadM<"lhu", CPU64Regs, zextloadi16>, LW_FM<0x25>;
132defm LW64 : LoadM<"lw", CPU64Regs, sextloadi32>, LW_FM<0x23>;
133defm LWu64 : LoadM<"lwu", CPU64Regs, zextloadi32>, LW_FM<0x27>;
134defm SB64 : StoreM<"sb", CPU64Regs, truncstorei8>, LW_FM<0x28>;
135defm SH64 : StoreM<"sh", CPU64Regs, truncstorei16>, LW_FM<0x29>;
136defm SW64 : StoreM<"sw", CPU64Regs, truncstorei32>, LW_FM<0x2b>;
137defm LD : LoadM<"ld", CPU64Regs, load>, LW_FM<0x37>;
138defm SD : StoreM<"sd", CPU64Regs, store>, LW_FM<0x3f>;
Akira Hatanakabe68f3c2011-10-11 00:27:28 +0000[diff] [blame]139
Akira Hatanakaf11571d2012-06-02 00:04:19 +0000[diff] [blame]140/// load/store left/right
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]141defm LWL64 : LoadLeftRightM<"lwl", MipsLWL, CPU64Regs>, LW_FM<0x22>;
142defm LWR64 : LoadLeftRightM<"lwr", MipsLWR, CPU64Regs>, LW_FM<0x26>;
143defm SWL64 : StoreLeftRightM<"swl", MipsSWL, CPU64Regs>, LW_FM<0x2a>;
144defm SWR64 : StoreLeftRightM<"swr", MipsSWR, CPU64Regs>, LW_FM<0x2e>;
145
Akira Hatanakae1826d72012-12-21 23:01:24 +0000[diff] [blame]146defm LDL : LoadLeftRightM<"ldl", MipsLDL, CPU64Regs>, LW_FM<0x1a>;
147defm LDR : LoadLeftRightM<"ldr", MipsLDR, CPU64Regs>, LW_FM<0x1b>;
148defm SDL : StoreLeftRightM<"sdl", MipsSDL, CPU64Regs>, LW_FM<0x2c>;
149defm SDR : StoreLeftRightM<"sdr", MipsSDR, CPU64Regs>, LW_FM<0x2d>;
Akira Hatanakaf11571d2012-06-02 00:04:19 +0000[diff] [blame]150
Akira Hatanaka21cbc252011-11-11 04:14:30 +0000[diff] [blame]151/// Load-linked, Store-conditional
Akira Hatanakae1826d72012-12-21 23:01:24 +0000[diff] [blame]152let Predicates = [NotN64, HasStdEnc] in {
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]153 def LLD : LLBase<"lld", CPU64RegsOpnd, mem>, LW_FM<0x34>;
154 def SCD : SCBase<"scd", CPU64RegsOpnd, mem>, LW_FM<0x3c>;
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]155}
Akira Hatanakae1826d72012-12-21 23:01:24 +0000[diff] [blame]156
157let Predicates = [IsN64, HasStdEnc], isCodeGenOnly = 1 in {
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]158 def LLD_P8 : LLBase<"lld", CPU64RegsOpnd, mem64>, LW_FM<0x34>;
159 def SCD_P8 : SCBase<"scd", CPU64RegsOpnd, mem64>, LW_FM<0x3c>;
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]160}
Akira Hatanaka21cbc252011-11-11 04:14:30 +0000[diff] [blame]161
Akira Hatanaka4b6ac982011-10-11 18:49:17 +0000[diff] [blame]162/// Jump and Branch Instructions
Akira Hatanakaa1580422012-12-21 23:03:50 +0000[diff] [blame]163def JR64 : IndirectBranch<CPU64Regs>, MTLO_FM<8>;
Akira Hatanakaf71ffd22012-12-20 04:10:13 +0000[diff] [blame]164def BEQ64 : CBranch<"beq", seteq, CPU64Regs>, BEQ_FM<4>;
165def BNE64 : CBranch<"bne", setne, CPU64Regs>, BEQ_FM<5>;
Akira Hatanakac0ea0bb2012-12-20 04:13:23 +0000[diff] [blame]166def BGEZ64 : CBranchZero<"bgez", setge, CPU64Regs>, BGEZ_FM<1, 1>;
167def BGTZ64 : CBranchZero<"bgtz", setgt, CPU64Regs>, BGEZ_FM<7, 0>;
168def BLEZ64 : CBranchZero<"blez", setle, CPU64Regs>, BGEZ_FM<6, 0>;
169def BLTZ64 : CBranchZero<"bltz", setlt, CPU64Regs>, BGEZ_FM<1, 0>;
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]170}
171let DecoderNamespace = "Mips64" in
Akira Hatanakaa1580422012-12-21 23:03:50 +0000[diff] [blame]172def JALR64 : JumpLinkReg<"jalr", CPU64Regs>, JALR_FM;
Akira Hatanaka061d1ea2013-02-07 19:48:00 +0000[diff] [blame^]173def JALR64Pseudo : JumpLinkRegPseudo<CPU64Regs, JALR64, RA_64>;
Akira Hatanakaa1580422012-12-21 23:03:50 +0000[diff] [blame]174def TAILCALL64_R : JumpFR<CPU64Regs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
Akira Hatanakab89a4bf2012-01-04 03:02:47 +0000[diff] [blame]175
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]176let DecoderNamespace = "Mips64" in {
Akira Hatanakaa279d9b2011-10-03 20:01:11 +0000[diff] [blame]177/// Multiply and Divide Instructions.
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]178def DMULT : Mult<"dmult", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
179 MULT_FM<0, 0x1c>;
180def DMULTu : Mult<"dmultu", IIImul, CPU64RegsOpnd, [HI64, LO64]>,
181 MULT_FM<0, 0x1d>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]182def DSDIV : Div<MipsDivRem, "ddiv", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>,
Akira Hatanakabeea8a32012-12-21 23:17:36 +0000[diff] [blame]183 MULT_FM<0, 0x1e>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]184def DUDIV : Div<MipsDivRemU, "ddivu", IIIdiv, CPU64RegsOpnd, [HI64, LO64]>,
Akira Hatanakabeea8a32012-12-21 23:17:36 +0000[diff] [blame]185 MULT_FM<0, 0x1f>;
Akira Hatanakaa279d9b2011-10-03 20:01:11 +0000[diff] [blame]186
Akira Hatanakab14c6e42012-12-21 22:39:17 +0000[diff] [blame]187def MTHI64 : MoveToLOHI<"mthi", CPU64Regs, [HI64]>, MTLO_FM<0x11>;
188def MTLO64 : MoveToLOHI<"mtlo", CPU64Regs, [LO64]>, MTLO_FM<0x13>;
189def MFHI64 : MoveFromLOHI<"mfhi", CPU64Regs, [HI64]>, MFLO_FM<0x10>;
190def MFLO64 : MoveFromLOHI<"mflo", CPU64Regs, [LO64]>, MFLO_FM<0x12>;
Akira Hatanakacdcc7452011-10-03 19:28:44 +0000[diff] [blame]191
Akira Hatanaka9f7ec152012-01-24 21:41:09 +0000[diff] [blame]192/// Sign Ext In Register Instructions.
Akira Hatanaka6ac2fc42012-12-21 23:21:32 +0000[diff] [blame]193def SEB64 : SignExtInReg<"seb", i8, CPU64Regs>, SEB_FM<0x10, 0x20>;
194def SEH64 : SignExtInReg<"seh", i16, CPU64Regs>, SEB_FM<0x18, 0x20>;
Akira Hatanaka9f7ec152012-01-24 21:41:09 +0000[diff] [blame]195
Akira Hatanaka48a72ca2011-10-03 21:16:50 +0000[diff] [blame]196/// Count Leading
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]197def DCLZ : CountLeading0<"dclz", CPU64RegsOpnd>, CLO_FM<0x24>;
198def DCLO : CountLeading1<"dclo", CPU64RegsOpnd>, CLO_FM<0x25>;
Akira Hatanaka48a72ca2011-10-03 21:16:50 +0000[diff] [blame]199
Akira Hatanaka4706ac92011-12-20 23:56:43 +0000[diff] [blame]200/// Double Word Swap Bytes/HalfWords
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]201def DSBH : SubwordSwap<"dsbh", CPU64RegsOpnd>, SEB_FM<2, 0x24>;
202def DSHD : SubwordSwap<"dshd", CPU64RegsOpnd>, SEB_FM<5, 0x24>;
Akira Hatanaka4706ac92011-12-20 23:56:43 +0000[diff] [blame]203
Akira Hatanaka6ac2fc42012-12-21 23:21:32 +0000[diff] [blame]204def LEA_ADDiu64 : EffectiveAddress<"daddiu", CPU64Regs, mem_ea_64>, LW_FM<0x19>;
205
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]206}
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]207let DecoderNamespace = "Mips64" in {
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]208def RDHWR64 : ReadHardware<CPU64Regs, HW64RegsOpnd>, RDHWR_FM;
Akira Hatanaka4350c182011-12-07 23:31:26 +0000[diff] [blame]209
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]210def DEXT : ExtBase<"dext", CPU64RegsOpnd>, EXT_FM<3>;
Jack Cartercd6b0e12012-08-28 20:07:41 +0000[diff] [blame]211let Pattern = []<dag> in {
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]212 def DEXTU : ExtBase<"dextu", CPU64RegsOpnd>, EXT_FM<2>;
213 def DEXTM : ExtBase<"dextm", CPU64RegsOpnd>, EXT_FM<1>;
Jack Cartercd6b0e12012-08-28 20:07:41 +0000[diff] [blame]214}
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]215def DINS : InsBase<"dins", CPU64RegsOpnd>, EXT_FM<7>;
Jack Carterb3f3b172012-08-31 18:06:48 +0000[diff] [blame]216let Pattern = []<dag> in {
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]217 def DINSU : InsBase<"dinsu", CPU64RegsOpnd>, EXT_FM<6>;
218 def DINSM : InsBase<"dinsm", CPU64RegsOpnd>, EXT_FM<5>;
Jack Carterb3f3b172012-08-31 18:06:48 +0000[diff] [blame]219}
Akira Hatanaka20cee2e2011-12-05 21:26:34 +0000[diff] [blame]220
Jack Carterf4946cf2012-08-07 00:35:22 +0000[diff] [blame]221let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
Jack Carter120a30a2012-08-09 19:43:18 +0000[diff] [blame]222 def DSLL64_32 : FR<0x00, 0x3c, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
Jack Carterf4946cf2012-08-07 00:35:22 +0000[diff] [blame]223 "dsll\t$rd, $rt, 32", [], IIAlu>;
224 def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt),
225 "sll\t$rd, $rt, 0", [], IIAlu>;
226 def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt),
227 "sll\t$rd, $rt, 0", [], IIAlu>;
228}
Akira Hatanaka71928e62012-04-17 18:03:21 +0000[diff] [blame]229}
Akira Hatanaka7ba8a8d2011-09-30 18:51:46 +0000[diff] [blame]230//===----------------------------------------------------------------------===//
231// Arbitrary patterns that map to one or more instructions
232//===----------------------------------------------------------------------===//
233
Akira Hatanakaf93b3f42011-11-14 19:06:14 +0000[diff] [blame]234// extended loads
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000[diff] [blame]235let Predicates = [NotN64, HasStdEnc] in {
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]236 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
237 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
Akira Hatanaka3e7ba762012-09-15 01:52:08 +0000[diff] [blame]238 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
239 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
Akira Hatanakaf93b3f42011-11-14 19:06:14 +0000[diff] [blame]240}
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000[diff] [blame]241let Predicates = [IsN64, HasStdEnc] in {
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]242 def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64_P8 addr:$src)>;
243 def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64_P8 addr:$src)>;
Akira Hatanaka3e7ba762012-09-15 01:52:08 +0000[diff] [blame]244 def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64_P8 addr:$src)>;
245 def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64_P8 addr:$src)>;
Akira Hatanakaf93b3f42011-11-14 19:06:14 +0000[diff] [blame]246}
Akira Hatanaka09b23eb2011-10-11 00:55:05 +0000[diff] [blame]247
248// hi/lo relocs
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]249def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
250def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
251def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
252def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
253def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
Akira Hatanakabb6e74a2012-11-21 20:40:38 +0000[diff] [blame]254def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
Akira Hatanaka7b8547c2011-11-16 22:39:56 +0000[diff] [blame]255
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]256def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
257def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
258def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
259def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
260def : MipsPat<(MipsLo tglobaltlsaddr:$in),
261 (DADDiu ZERO_64, tglobaltlsaddr:$in)>;
Akira Hatanakabb6e74a2012-11-21 20:40:38 +0000[diff] [blame]262def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
Akira Hatanaka7b8547c2011-11-16 22:39:56 +0000[diff] [blame]263
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]264def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaladdr:$lo)),
265 (DADDiu CPU64Regs:$hi, tglobaladdr:$lo)>;
266def : MipsPat<(add CPU64Regs:$hi, (MipsLo tblockaddress:$lo)),
267 (DADDiu CPU64Regs:$hi, tblockaddress:$lo)>;
268def : MipsPat<(add CPU64Regs:$hi, (MipsLo tjumptable:$lo)),
269 (DADDiu CPU64Regs:$hi, tjumptable:$lo)>;
270def : MipsPat<(add CPU64Regs:$hi, (MipsLo tconstpool:$lo)),
271 (DADDiu CPU64Regs:$hi, tconstpool:$lo)>;
272def : MipsPat<(add CPU64Regs:$hi, (MipsLo tglobaltlsaddr:$lo)),
273 (DADDiu CPU64Regs:$hi, tglobaltlsaddr:$lo)>;
Akira Hatanakaf75add62011-10-11 18:53:46 +0000[diff] [blame]274
Akira Hatanakab049aef2012-02-24 22:34:47 +0000[diff] [blame]275def : WrapperPat<tglobaladdr, DADDiu, CPU64Regs>;
276def : WrapperPat<tconstpool, DADDiu, CPU64Regs>;
277def : WrapperPat<texternalsym, DADDiu, CPU64Regs>;
278def : WrapperPat<tblockaddress, DADDiu, CPU64Regs>;
279def : WrapperPat<tjumptable, DADDiu, CPU64Regs>;
280def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
Akira Hatanakab2e05cb2011-12-07 22:11:43 +0000[diff] [blame]281
Akira Hatanaka7148bce2011-10-11 19:09:09 +0000[diff] [blame]282defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
283 ZERO_64>;
284
Akira Hatanakaf75add62011-10-11 18:53:46 +0000[diff] [blame]285// setcc patterns
Akira Hatanaka453ac882011-10-11 21:48:01 +0000[diff] [blame]286defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
Akira Hatanaka46a79942011-10-11 21:40:01 +0000[diff] [blame]287defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
288defm : SetgtPats<CPU64Regs, SLT64, SLTu64>;
289defm : SetgePats<CPU64Regs, SLT64, SLTu64>;
290defm : SetgeImmPats<CPU64Regs, SLTi64, SLTiu64>;
Akira Hatanakad5c13292011-11-07 18:57:41 +0000[diff] [blame]291
292// truncate
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]293def : MipsPat<(i32 (trunc CPU64Regs:$src)),
294 (SLL (EXTRACT_SUBREG CPU64Regs:$src, sub_32), 0)>,
Akira Hatanaka97e179f2012-12-07 03:06:09 +0000[diff] [blame]295 Requires<[IsN64, HasStdEnc]>;
Jia Liuf54f60f2012-02-28 07:46:26 +0000[diff] [blame]296
Akira Hatanakaae378af2011-12-07 23:14:41 +0000[diff] [blame]297// 32-to-64-bit extension
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]298def : MipsPat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
299def : MipsPat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>;
300def : MipsPat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>;
Akira Hatanaka4e210692011-12-20 22:06:20 +0000[diff] [blame]301
Akira Hatanaka494fdf12011-12-20 22:40:40 +0000[diff] [blame]302// Sign extend in register
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]303def : MipsPat<(i64 (sext_inreg CPU64Regs:$src, i32)),
304 (SLL64_64 CPU64Regs:$src)>;
Akira Hatanaka494fdf12011-12-20 22:40:40 +0000[diff] [blame]305
Akira Hatanakad8ab16b2012-06-14 21:03:23 +0000[diff] [blame]306// bswap MipsPattern
307def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
David Chisnall37051252012-10-09 16:27:43 +0000[diff] [blame]308
309//===----------------------------------------------------------------------===//
310// Instruction aliases
311//===----------------------------------------------------------------------===//
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]312def : InstAlias<"move $dst, $src",
313 (DADDu CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 1>,
314 Requires<[HasMips64]>;
315def : InstAlias<"move $dst, $src",
316 (OR64 CPU64RegsOpnd:$dst, CPU64RegsOpnd:$src, ZERO_64), 0>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]317 Requires<[HasMips64]>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]318def : InstAlias<"and $rs, $rt, $imm",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]319 (DANDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
320 1>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]321 Requires<[HasMips64]>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]322def : InstAlias<"slt $rs, $rt, $imm",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]323 (SLTi64 CPURegsOpnd:$rs, CPU64Regs:$rt, simm16_64:$imm), 1>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]324 Requires<[HasMips64]>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]325def : InstAlias<"xor $rs, $rt, $imm",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]326 (XORi64 CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, uimm16_64:$imm),
327 1>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]328 Requires<[HasMips64]>;
329def : InstAlias<"not $rt, $rs",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]330 (NOR64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rs, ZERO_64), 1>,
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]331 Requires<[HasMips64]>;
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]332def : InstAlias<"j $rs", (JR64 CPU64Regs:$rs), 0>, Requires<[HasMips64]>;
Akira Hatanaka061d1ea2013-02-07 19:48:00 +0000[diff] [blame^]333def : InstAlias<"jalr $rs", (JALR64 RA_64, CPU64Regs:$rs)>,
334 Requires<[HasMips64]>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]335def : InstAlias<"daddu $rs, $rt, $imm",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]336 (DADDiu CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
337 1>;
Jack Carter873c7242013-01-12 01:03:14 +0000[diff] [blame]338def : InstAlias<"dadd $rs, $rt, $imm",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]339 (DADDi CPU64RegsOpnd:$rs, CPU64RegsOpnd:$rt, simm16_64:$imm),
340 1>;
David Chisnall6a00ab42012-10-11 10:21:34 +0000[diff] [blame]341
342/// Move between CPU and coprocessor registers
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]343
David Chisnall6a00ab42012-10-11 10:21:34 +0000[diff] [blame]344let DecoderNamespace = "Mips64" in {
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]345def DMFC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
346 (ins CPU64RegsOpnd:$rd, uimm16:$sel),
Akira Hatanakae36e2f62013-01-04 19:13:49 +0000[diff] [blame]347 "dmfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 1>;
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]348def DMTC0_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
349 (ins CPU64RegsOpnd:$rt),
Akira Hatanakae36e2f62013-01-04 19:13:49 +0000[diff] [blame]350 "dmtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 5>;
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]351def DMFC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rt),
352 (ins CPU64RegsOpnd:$rd, uimm16:$sel),
Akira Hatanakae36e2f62013-01-04 19:13:49 +0000[diff] [blame]353 "dmfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 1>;
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]354def DMTC2_3OP64 : MFC3OP<(outs CPU64RegsOpnd:$rd, uimm16:$sel),
355 (ins CPU64RegsOpnd:$rt),
Akira Hatanakae36e2f62013-01-04 19:13:49 +0000[diff] [blame]356 "dmtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 5>;
David Chisnall6a00ab42012-10-11 10:21:34 +0000[diff] [blame]357}
Jack Carter86c2c562013-01-18 20:15:06 +0000[diff] [blame]358
David Chisnall6a00ab42012-10-11 10:21:34 +0000[diff] [blame]359// Two operand (implicit 0 selector) versions:
Akira Hatanakae067e5a2013-01-04 19:38:05 +0000[diff] [blame]360def : InstAlias<"dmfc0 $rt, $rd",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]361 (DMFC0_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>;
Akira Hatanakae067e5a2013-01-04 19:38:05 +0000[diff] [blame]362def : InstAlias<"dmtc0 $rt, $rd",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]363 (DMTC0_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>;
Akira Hatanakae067e5a2013-01-04 19:38:05 +0000[diff] [blame]364def : InstAlias<"dmfc2 $rt, $rd",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]365 (DMFC2_3OP64 CPU64RegsOpnd:$rt, CPU64RegsOpnd:$rd, 0), 0>;
Akira Hatanakae067e5a2013-01-04 19:38:05 +0000[diff] [blame]366def : InstAlias<"dmtc2 $rt, $rd",
Jack Carter9c1a0272013-02-05 08:32:10 +0000[diff] [blame]367 (DMTC2_3OP64 CPU64RegsOpnd:$rd, 0, CPU64RegsOpnd:$rt), 0>;
David Chisnall6a00ab42012-10-11 10:21:34 +0000[diff] [blame]368