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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for R600InstrInfo
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef R600INSTRUCTIONINFO_H_
16#define R600INSTRUCTIONINFO_H_
17
Tom Stellard75aadc22012-12-11 21:25:42 +000018#include "AMDGPUInstrInfo.h"
Chandler Carruthbe810232013-01-02 10:22:59 +000019#include "AMDIL.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000020#include "R600Defines.h"
21#include "R600RegisterInfo.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000022#include <map>
23
24namespace llvm {
25
26 class AMDGPUTargetMachine;
27 class DFAPacketizer;
28 class ScheduleDAG;
29 class MachineFunction;
30 class MachineInstr;
31 class MachineInstrBuilder;
32
33 class R600InstrInfo : public AMDGPUInstrInfo {
34 private:
35 const R600RegisterInfo RI;
Vincent Lejeunec2991642013-04-30 00:13:39 +000036 const AMDGPUSubtarget &ST;
Tom Stellard75aadc22012-12-11 21:25:42 +000037
38 int getBranchInstr(const MachineOperand &op) const;
39
40 public:
41 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
42
43 const R600RegisterInfo &getRegisterInfo() const;
44 virtual void copyPhysReg(MachineBasicBlock &MBB,
45 MachineBasicBlock::iterator MI, DebugLoc DL,
46 unsigned DestReg, unsigned SrcReg,
47 bool KillSrc) const;
48
49 bool isTrig(const MachineInstr &MI) const;
50 bool isPlaceHolderOpcode(unsigned opcode) const;
51 bool isReductionOp(unsigned opcode) const;
52 bool isCubeOp(unsigned opcode) const;
53
54 /// \returns true if this \p Opcode represents an ALU instruction.
55 bool isALUInstr(unsigned Opcode) const;
56
Vincent Lejeune076c0b22013-04-30 00:14:17 +000057 bool isTransOnly(unsigned Opcode) const;
58 bool isTransOnly(const MachineInstr *MI) const;
59
Vincent Lejeunec2991642013-04-30 00:13:39 +000060 bool usesVertexCache(unsigned Opcode) const;
61 bool usesVertexCache(const MachineInstr *MI) const;
62 bool usesTextureCache(unsigned Opcode) const;
63 bool usesTextureCache(const MachineInstr *MI) const;
64
Vincent Lejeune0a22bc42013-03-14 15:50:45 +000065 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
66 bool canBundle(const std::vector<MachineInstr *> &) const;
67
Tom Stellard75aadc22012-12-11 21:25:42 +000068 /// \breif Vector instructions are instructions that must fill all
69 /// instruction slots within an instruction group.
70 bool isVector(const MachineInstr &MI) const;
71
72 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
73 int64_t Imm) const;
74
75 virtual unsigned getIEQOpcode() const;
76 virtual bool isMov(unsigned Opcode) const;
77
78 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
79 const ScheduleDAG *DAG) const;
80
81 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
82
83 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
84 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
85
86 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
87
88 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
89
90 bool isPredicated(const MachineInstr *MI) const;
91
92 bool isPredicable(MachineInstr *MI) const;
93
94 bool
95 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
96 const BranchProbability &Probability) const;
97
98 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
99 unsigned ExtraPredCycles,
100 const BranchProbability &Probability) const ;
101
102 bool
103 isProfitableToIfCvt(MachineBasicBlock &TMBB,
104 unsigned NumTCycles, unsigned ExtraTCycles,
105 MachineBasicBlock &FMBB,
106 unsigned NumFCycles, unsigned ExtraFCycles,
107 const BranchProbability &Probability) const;
108
109 bool DefinesPredicate(MachineInstr *MI,
110 std::vector<MachineOperand> &Pred) const;
111
112 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
113 const SmallVectorImpl<MachineOperand> &Pred2) const;
114
115 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
116 MachineBasicBlock &FMBB) const;
117
118 bool PredicateInstruction(MachineInstr *MI,
119 const SmallVectorImpl<MachineOperand> &Pred) const;
120
121 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
122 const MachineInstr *MI,
123 unsigned *PredCost = 0) const;
124
125 virtual int getInstrLatency(const InstrItineraryData *ItinData,
126 SDNode *Node) const { return 1;}
127
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000128 /// \returns a list of all the registers that may be accesed using indirect
129 /// addressing.
130 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
131
132 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
133
134 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
135
136
137 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
138 unsigned Channel) const;
139
140 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
141 unsigned SourceReg) const;
142
143 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
144
145 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
146 MachineBasicBlock::iterator I,
147 unsigned ValueReg, unsigned Address,
148 unsigned OffsetReg) const;
149
150 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
151 MachineBasicBlock::iterator I,
152 unsigned ValueReg, unsigned Address,
153 unsigned OffsetReg) const;
154
155 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
156
Vincent Lejeune80031d9f2013-04-03 16:49:34 +0000157 unsigned getMaxAlusPerClause() const;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000158
159 ///buildDefaultInstruction - This function returns a MachineInstr with
160 /// all the instruction modifiers initialized to their default values.
Tom Stellard75aadc22012-12-11 21:25:42 +0000161 /// You can use this function to avoid manually specifying each instruction
162 /// modifier operand when building a new instruction.
163 ///
164 /// \returns a MachineInstr with all the instruction modifiers initialized
165 /// to their default values.
166 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
167 MachineBasicBlock::iterator I,
168 unsigned Opcode,
169 unsigned DstReg,
170 unsigned Src0Reg,
171 unsigned Src1Reg = 0) const;
172
173 MachineInstr *buildMovImm(MachineBasicBlock &BB,
174 MachineBasicBlock::iterator I,
175 unsigned DstReg,
176 uint64_t Imm) const;
177
178 /// \brief Get the index of Op in the MachineInstr.
179 ///
180 /// \returns -1 if the Instruction does not contain the specified \p Op.
181 int getOperandIdx(const MachineInstr &MI, R600Operands::Ops Op) const;
182
183 /// \brief Get the index of \p Op for the given Opcode.
184 ///
185 /// \returns -1 if the Instruction does not contain the specified \p Op.
186 int getOperandIdx(unsigned Opcode, R600Operands::Ops Op) const;
187
188 /// \brief Helper function for setting instruction flag values.
189 void setImmOperand(MachineInstr *MI, R600Operands::Ops Op, int64_t Imm) const;
190
191 /// \returns true if this instruction has an operand for storing target flags.
192 bool hasFlagOperand(const MachineInstr &MI) const;
193
194 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
195 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
196
197 ///\brief Determine if the specified \p Flag is set on this \p Operand.
198 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
199
200 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
201 /// \param Flag The flag being set.
202 ///
203 /// \returns the operand containing the flags for this instruction.
204 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
205 unsigned Flag = 0) const;
206
207 /// \brief Clear the specified flag on the instruction.
208 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
209};
210
211} // End llvm namespace
212
213#endif // R600INSTRINFO_H_