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Simon Atanasyan07ce7d8f2012-06-28 18:23:16 +00001// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm -o %t %s
2// RUN: not grep __builtin %t
3
4typedef int q31;
5typedef int i32;
6typedef unsigned int ui32;
7typedef long long a64;
8
9typedef signed char v4i8 __attribute__ ((vector_size(4)));
10typedef short v2q15 __attribute__ ((vector_size(4)));
11
12void foo() {
13 v2q15 v2q15_r, v2q15_a, v2q15_b, v2q15_c;
14 v4i8 v4i8_r, v4i8_a, v4i8_b, v4i8_c;
15 q31 q31_r, q31_a, q31_b, q31_c;
16 i32 i32_r, i32_a, i32_b, i32_c;
17 ui32 ui32_r, ui32_a, ui32_b, ui32_c;
18 a64 a64_r, a64_a, a64_b;
19
20 // MIPS DSP Rev 1
21
22 v4i8_a = (v4i8) {1, 2, 3, 0xFF};
23 v4i8_b = (v4i8) {2, 4, 6, 8};
24 v4i8_r = __builtin_mips_addu_qb(v4i8_a, v4i8_b);
25 v4i8_r = __builtin_mips_addu_s_qb(v4i8_a, v4i8_b);
26 v4i8_r = __builtin_mips_subu_qb(v4i8_a, v4i8_b);
27 v4i8_r = __builtin_mips_subu_s_qb(v4i8_a, v4i8_b);
28
29 v2q15_a = (v2q15) {0x0000, 0x8000};
30 v2q15_b = (v2q15) {0x8000, 0x8000};
31 v2q15_r = __builtin_mips_addq_ph(v2q15_a, v2q15_b);
32 v2q15_r = __builtin_mips_addq_s_ph(v2q15_a, v2q15_b);
33 v2q15_r = __builtin_mips_subq_ph(v2q15_a, v2q15_b);
34 v2q15_r = __builtin_mips_subq_s_ph(v2q15_a, v2q15_b);
35
36 a64_a = 0x12345678;
37 i32_b = 0x80000000;
38 i32_c = 0x11112222;
39 a64_r = __builtin_mips_madd(a64_a, i32_b, i32_c);
40 a64_a = 0x12345678;
41 ui32_b = 0x80000000;
42 ui32_c = 0x11112222;
43 a64_r = __builtin_mips_maddu(a64_a, ui32_b, ui32_c);
44 a64_a = 0x12345678;
45 i32_b = 0x80000000;
46 i32_c = 0x11112222;
47 a64_r = __builtin_mips_msub(a64_a, i32_b, i32_c);
48 a64_a = 0x12345678;
49 ui32_b = 0x80000000;
50 ui32_c = 0x11112222;
51 a64_r = __builtin_mips_msubu(a64_a, ui32_b, ui32_c);
52
53 q31_a = 0x12345678;
54 q31_b = 0x7FFFFFFF;
55 q31_r = __builtin_mips_addq_s_w(q31_a, q31_b);
56 q31_r = __builtin_mips_subq_s_w(q31_a, q31_b);
57
58 i32_a = 0xFFFFFFFF;
59 i32_b = 1;
60 i32_r = __builtin_mips_addsc(i32_a, i32_b);
61 i32_a = 0;
62 i32_b = 1;
63 i32_r = __builtin_mips_addwc(i32_a, i32_b);
64
65 i32_a = 20;
66 i32_b = 0x1402;
67 i32_r = __builtin_mips_modsub(i32_a, i32_b);
68
69 v4i8_a = (v4i8) {1, 2, 3, 4};
70 i32_r = __builtin_mips_raddu_w_qb(v4i8_a);
71
72 v2q15_a = (v2q15) {0xFFFF, 0x8000};
73 v2q15_r = __builtin_mips_absq_s_ph(v2q15_a);
74 q31_a = 0x80000000;
75 q31_r = __builtin_mips_absq_s_w(q31_a);
76
77 v2q15_a = (v2q15) {0x1234, 0x5678};
78 v2q15_b = (v2q15) {0x1111, 0x2222};
79 v4i8_r = __builtin_mips_precrq_qb_ph(v2q15_a, v2q15_b);
80
81 v2q15_a = (v2q15) {0x7F79, 0xFFFF};
82 v2q15_b = (v2q15) {0x7F81, 0x2000};
83 v4i8_r = __builtin_mips_precrqu_s_qb_ph(v2q15_a, v2q15_b);
84 q31_a = 0x12345678;
85 q31_b = 0x11112222;
86 v2q15_r = __builtin_mips_precrq_ph_w(q31_a, q31_b);
87 q31_a = 0x7000FFFF;
88 q31_b = 0x80000000;
89 v2q15_r = __builtin_mips_precrq_rs_ph_w(q31_a, q31_b);
90 v2q15_a = (v2q15) {0x1234, 0x5678};
91 q31_r = __builtin_mips_preceq_w_phl(v2q15_a);
92 q31_r = __builtin_mips_preceq_w_phr(v2q15_a);
93 v4i8_a = (v4i8) {0x12, 0x34, 0x56, 0x78};
94 v2q15_r = __builtin_mips_precequ_ph_qbl(v4i8_a);
95 v2q15_r = __builtin_mips_precequ_ph_qbr(v4i8_a);
96 v2q15_r = __builtin_mips_precequ_ph_qbla(v4i8_a);
97 v2q15_r = __builtin_mips_precequ_ph_qbra(v4i8_a);
98 v2q15_r = __builtin_mips_preceu_ph_qbl(v4i8_a);
99 v2q15_r = __builtin_mips_preceu_ph_qbr(v4i8_a);
100 v2q15_r = __builtin_mips_preceu_ph_qbla(v4i8_a);
101 v2q15_r = __builtin_mips_preceu_ph_qbra(v4i8_a);
102
103 v4i8_a = (v4i8) {1, 2, 3, 4};
104 v4i8_r = __builtin_mips_shll_qb(v4i8_a, 2);
105 v4i8_a = (v4i8) {128, 64, 32, 16};
106 v4i8_r = __builtin_mips_shrl_qb(v4i8_a, 2);
107 v2q15_a = (v2q15) {0x0001, 0x8000};
108 v2q15_r = __builtin_mips_shll_ph(v2q15_a, 2);
109 v2q15_r = __builtin_mips_shll_s_ph(v2q15_a, 2);
110 v2q15_a = (v2q15) {0x7FFF, 0x8000};
111 v2q15_r = __builtin_mips_shra_ph(v2q15_a, 2);
112 v2q15_r = __builtin_mips_shra_r_ph(v2q15_a, 2);
113 q31_a = 0x70000000;
114 q31_r = __builtin_mips_shll_s_w(q31_a, 2);
115 q31_a = 0x7FFFFFFF;
116 q31_r = __builtin_mips_shra_r_w(q31_a, 2);
117 a64_a = 0x1234567887654321LL;
118 a64_r = __builtin_mips_shilo(a64_a, -8);
119
120 v4i8_a = (v4i8) {0x1, 0x3, 0x5, 0x7};
121 v2q15_b = (v2q15) {0x1234, 0x5678};
122 v2q15_r = __builtin_mips_muleu_s_ph_qbl(v4i8_a, v2q15_b);
123 v2q15_r = __builtin_mips_muleu_s_ph_qbr(v4i8_a, v2q15_b);
124 v2q15_a = (v2q15) {0x7FFF, 0x8000};
125 v2q15_b = (v2q15) {0x7FFF, 0x8000};
126 v2q15_r = __builtin_mips_mulq_rs_ph(v2q15_a, v2q15_b);
127 v2q15_a = (v2q15) {0x1234, 0x8000};
128 v2q15_b = (v2q15) {0x5678, 0x8000};
129 q31_r = __builtin_mips_muleq_s_w_phl(v2q15_a, v2q15_b);
130 q31_r = __builtin_mips_muleq_s_w_phr(v2q15_a, v2q15_b);
131 a64_a = 0;
132 v2q15_a = (v2q15) {0x0001, 0x8000};
133 v2q15_b = (v2q15) {0x0002, 0x8000};
134 a64_r = __builtin_mips_mulsaq_s_w_ph(a64_a, v2q15_b, v2q15_c);
135 a64_a = 0;
136 v2q15_b = (v2q15) {0x0001, 0x8000};
137 v2q15_c = (v2q15) {0x0002, 0x8000};
138 a64_r = __builtin_mips_maq_s_w_phl(a64_a, v2q15_b, v2q15_c);
139 a64_r = __builtin_mips_maq_s_w_phr(a64_a, v2q15_b, v2q15_c);
140 a64_a = 0x7FFFFFF0;
141 a64_r = __builtin_mips_maq_sa_w_phl(a64_a, v2q15_b, v2q15_c);
142 a64_r = __builtin_mips_maq_sa_w_phr(a64_a, v2q15_b, v2q15_c);
143 i32_a = 0x80000000;
144 i32_b = 0x11112222;
145 a64_r = __builtin_mips_mult(i32_a, i32_b);
146 ui32_a = 0x80000000;
147 ui32_b = 0x11112222;
148 a64_r = __builtin_mips_multu(ui32_a, ui32_b);
149
150 a64_a = 0;
151 v4i8_b = (v4i8) {1, 2, 3, 4};
152 v4i8_c = (v4i8) {4, 5, 6, 7};
153 a64_r = __builtin_mips_dpau_h_qbl(a64_a, v4i8_b, v4i8_c);
154 a64_r = __builtin_mips_dpau_h_qbr(a64_a, v4i8_b, v4i8_c);
155 a64_r = __builtin_mips_dpsu_h_qbl(a64_a, v4i8_b, v4i8_c);
156 a64_r = __builtin_mips_dpsu_h_qbr(a64_a, v4i8_b, v4i8_c);
157 a64_a = 0;
158 v2q15_b = (v2q15) {0x0001, 0x8000};
159 v2q15_c = (v2q15) {0x0002, 0x8000};
160 a64_r = __builtin_mips_dpaq_s_w_ph(a64_a, v2q15_b, v2q15_c);
161 a64_r = __builtin_mips_dpsq_s_w_ph(a64_a, v2q15_b, v2q15_c);
162 a64_a = 0;
163 q31_b = 0x80000000;
164 q31_c = 0x80000000;
165 a64_r = __builtin_mips_dpaq_sa_l_w(a64_a, q31_b, q31_c);
166 a64_r = __builtin_mips_dpsq_sa_l_w(a64_a, q31_b, q31_c);
167
168 v4i8_a = (v4i8) {1, 4, 10, 8};
169 v4i8_b = (v4i8) {1, 2, 100, 8};
170 __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b);
171 __builtin_mips_cmpu_lt_qb(v4i8_a, v4i8_b);
172 __builtin_mips_cmpu_le_qb(v4i8_a, v4i8_b);
173 i32_r = __builtin_mips_cmpgu_eq_qb(v4i8_a, v4i8_b);
174 i32_r = __builtin_mips_cmpgu_lt_qb(v4i8_a, v4i8_b);
175 i32_r = __builtin_mips_cmpgu_le_qb(v4i8_a, v4i8_b);
176 v2q15_a = (v2q15) {0x1111, 0x1234};
177 v2q15_b = (v2q15) {0x4444, 0x1234};
178 __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b);
179 __builtin_mips_cmp_lt_ph(v2q15_a, v2q15_b);
180 __builtin_mips_cmp_le_ph(v2q15_a, v2q15_b);
181
182 a64_a = 0xFFFFF81230000000LL;
183 i32_r = __builtin_mips_extr_s_h(a64_a, 4);
184 a64_a = 0x8123456712345678LL;
185 i32_r = __builtin_mips_extr_w(a64_a, 31);
186 i32_r = __builtin_mips_extr_rs_w(a64_a, 31);
187 i32_r = __builtin_mips_extr_r_w(a64_a, 31);
188 a64_a = 0x1234567887654321LL;
189 i32_r = __builtin_mips_extp(a64_a, 3);
190 a64_a = 0x123456789ABCDEF0LL;
191 i32_r = __builtin_mips_extpdp(a64_a, 7);
192
193 __builtin_mips_wrdsp(2052, 3);
194 i32_r = __builtin_mips_rddsp(3);
195 i32_a = 0xFFFFFFFF;
196 i32_b = 0x12345678;
197 __builtin_mips_wrdsp((16<<7) + 4, 3);
198 i32_r = __builtin_mips_insv(i32_a, i32_b);
199 i32_a = 0x1234;
200 i32_r = __builtin_mips_bitrev(i32_a);
201 v2q15_a = (v2q15) {0x1111, 0x2222};
202 v2q15_b = (v2q15) {0x3333, 0x4444};
203 v2q15_r = __builtin_mips_packrl_ph(v2q15_a, v2q15_b);
204 i32_a = 100;
205 v4i8_r = __builtin_mips_repl_qb(i32_a);
206 i32_a = 0x1234;
207 v2q15_r = __builtin_mips_repl_ph(i32_a);
208 v4i8_a = (v4i8) {1, 4, 10, 8};
209 v4i8_b = (v4i8) {1, 2, 100, 8};
210 __builtin_mips_cmpu_eq_qb(v4i8_a, v4i8_b);
211 v4i8_r = __builtin_mips_pick_qb(v4i8_a, v4i8_b);
212 v2q15_a = (v2q15) {0x1111, 0x1234};
213 v2q15_b = (v2q15) {0x4444, 0x1234};
214 __builtin_mips_cmp_eq_ph(v2q15_a, v2q15_b);
215 v2q15_r = __builtin_mips_pick_ph(v2q15_a, v2q15_b);
216 a64_a = 0x1234567887654321LL;
217 i32_b = 0x11112222;
218 __builtin_mips_wrdsp(0, 1);
219 a64_r = __builtin_mips_mthlip(a64_a, i32_b);
220 i32_r = __builtin_mips_bposge32();
221 char array_a[100];
222 i32_r = __builtin_mips_lbux(array_a, 20);
223 short array_b[100];
224 i32_r = __builtin_mips_lhx(array_b, 20);
225 int array_c[100];
226 i32_r = __builtin_mips_lwx(array_c, 20);
227}