| Simon Dardis | 0a47edb | 2017-04-04 11:28:53 +0000 | [diff] [blame^] | 1 | # RUN: llc -march=mipsel -mcpu=mips32r6 -start-after=block-placement %s -o - | FileCheck %s |
| 2 | |
| 3 | # Check that empty blocks in the cfg don't cause the mips hazard scheduler to |
| 4 | # crash and that the nop is inserted correctly. |
| 5 | |
| 6 | # CHECK: blezc |
| 7 | # CHECK: nop |
| 8 | # CHECK: # BB#1: |
| 9 | # CHECK: .insn |
| 10 | # CHECK: # BB#2: |
| 11 | # CHECK: .insn |
| 12 | # CHECK: # BB#3: |
| 13 | # CHECK: jal |
| 14 | |
| 15 | --- | |
| 16 | ; ModuleID = '<stdin>' |
| 17 | source_filename = "<stdin>" |
| 18 | target datalayout = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64" |
| 19 | |
| 20 | declare i32 @k() |
| 21 | |
| 22 | declare void @f(i32) |
| 23 | |
| 24 | define void @l5() { |
| 25 | entry: |
| 26 | %call = tail call i32 @k() |
| 27 | %cmp = icmp sgt i32 %call, 0 |
| 28 | br i1 %cmp, label %if.then, label %if.end |
| 29 | |
| 30 | if.then: ; preds = %entry |
| 31 | tail call void @f(i32 signext 2) |
| 32 | br label %if.end |
| 33 | |
| 34 | if.end: ; preds = %if.then, %entry |
| 35 | ret void |
| 36 | } |
| 37 | |
| 38 | --- |
| 39 | name: l5 |
| 40 | alignment: 2 |
| 41 | exposesReturnsTwice: false |
| 42 | noVRegs: true |
| 43 | legalized: false |
| 44 | regBankSelected: false |
| 45 | selected: false |
| 46 | tracksRegLiveness: true |
| 47 | frameInfo: |
| 48 | isFrameAddressTaken: false |
| 49 | isReturnAddressTaken: false |
| 50 | hasStackMap: false |
| 51 | hasPatchPoint: false |
| 52 | stackSize: 24 |
| 53 | offsetAdjustment: 0 |
| 54 | maxAlignment: 4 |
| 55 | adjustsStack: true |
| 56 | hasCalls: true |
| 57 | maxCallFrameSize: 16 |
| 58 | hasOpaqueSPAdjustment: false |
| 59 | hasVAStart: false |
| 60 | hasMustTailInVarArgFunc: false |
| 61 | stack: |
| 62 | - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '%ra' } |
| 63 | body: | |
| 64 | bb.0.entry: |
| 65 | successors: %bb.1.if.then(0x50000000), %bb.4.if.end(0x30000000) |
| 66 | liveins: %ra |
| 67 | |
| 68 | %sp = ADDiu %sp, -24 |
| 69 | CFI_INSTRUCTION def_cfa_offset 24 |
| 70 | SW killed %ra, %sp, 20 :: (store 4 into %stack.0) |
| 71 | CFI_INSTRUCTION offset %ra_64, -4 |
| 72 | JAL @k, csr_o32_fp64, implicit-def dead %ra, implicit-def %sp, implicit-def %v0 |
| 73 | BLEZ %v0, %bb.4.if.end, implicit-def %at |
| 74 | |
| 75 | bb.1.if.then: |
| 76 | successors: %bb.2.if.then(0x80000000) |
| 77 | |
| 78 | bb.2.if.then: |
| 79 | successors: %bb.3.if.then(0x80000000) |
| 80 | |
| 81 | bb.3.if.then: |
| 82 | successors: %bb.4.if.end(0x80000000) |
| 83 | |
| 84 | %a0 = ADDiu %zero, 2 |
| 85 | JAL @f, csr_o32_fp64, implicit-def dead %ra, implicit killed %a0, implicit-def %sp |
| 86 | |
| 87 | bb.4.if.end: |
| 88 | %ra = LW %sp, 20 :: (load 4 from %stack.0) |
| 89 | %sp = ADDiu %sp, 24 |
| 90 | PseudoReturn undef %ra |
| 91 | |
| 92 | ... |