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gerrit-public.fairphone.software / toolchain / llvm-project / 0fa6041625f2b1e263dde8829e265c34dfd79483 / . / llvm / test / CodeGen / Mips / fcmp.ll
blob: 27246fe20bb217547fb4c07e0bb6bd41a51e8f13 [file] [log] [blame]
Daniel Sanders0fa60412014-06-12 13:39:06 +0000[diff] [blame^]1; RUN: llc < %s -march=mipsel -mcpu=mips32 | FileCheck %s -check-prefix=ALL -check-prefix=32-C
2; RUN: llc < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL -check-prefix=32-C
3; RUN: llc < %s -march=mipsel -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL -check-prefix=32-CMP
4; RUN: llc < %s -march=mips64el -mcpu=mips4 | FileCheck %s -check-prefix=ALL -check-prefix=64-C
5; RUN: llc < %s -march=mips64el -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=64-C
6; RUN: llc < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL -check-prefix=64-C
7; RUN: llc < %s -march=mips64el -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL -check-prefix=64-CMP
8
9define i32 @false_f32(float %a, float %b) nounwind {
10; ALL-LABEL: false_f32:
11; ALL: addiu $2, $zero, 0
12
13 %1 = fcmp false float %a, %b
14 %2 = zext i1 %1 to i32
15 ret i32 %2
16}
17
18define i32 @oeq_f32(float %a, float %b) nounwind {
19; ALL-LABEL: oeq_f32:
20
21; 32-C-DAG: addiu $[[T0:2]], $zero, 0
22; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
23; 32-C-DAG: c.eq.s $f12, $f14
24; 32-C-DAG: movt $[[T0]], $1, $fcc0
25
26; 64-C-DAG: addiu $[[T0:2]], $zero, 0
27; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
28; 64-C-DAG: c.eq.s $f12, $f13
29; 64-C-DAG: movt $[[T0]], $1, $fcc0
30
31; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
32; 32-CMP-DAG: mfc1 $2, $[[T0]]
33
34; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
35; 64-CMP-DAG: mfc1 $2, $[[T0]]
36
37 %1 = fcmp oeq float %a, %b
38 %2 = zext i1 %1 to i32
39 ret i32 %2
40}
41
42define i32 @ogt_f32(float %a, float %b) nounwind {
43; ALL-LABEL: ogt_f32:
44
45; 32-C-DAG: addiu $[[T0:2]], $zero, 0
46; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
47; 32-C-DAG: c.ule.s $f12, $f14
48; 32-C-DAG: movf $[[T0]], $1, $fcc0
49
50; 64-C-DAG: addiu $[[T0:2]], $zero, 0
51; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
52; 64-C-DAG: c.ule.s $f12, $f13
53; 64-C-DAG: movf $[[T0]], $1, $fcc0
54
55; 32-CMP-DAG: cmp.olt.s $[[T0:f[0-9]+]], $f14, $f12
56; 32-CMP-DAG: mfc1 $2, $[[T0]]
57
58; 64-CMP-DAG: cmp.olt.s $[[T0:f[0-9]+]], $f13, $f12
59; 64-CMP-DAG: mfc1 $2, $[[T0]]
60
61 %1 = fcmp ogt float %a, %b
62 %2 = zext i1 %1 to i32
63 ret i32 %2
64}
65
66define i32 @oge_f32(float %a, float %b) nounwind {
67; ALL-LABEL: oge_f32:
68
69; 32-C-DAG: addiu $[[T0:2]], $zero, 0
70; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
71; 32-C-DAG: c.ult.s $f12, $f14
72; 32-C-DAG: movf $[[T0]], $1, $fcc0
73
74; 64-C-DAG: addiu $[[T0:2]], $zero, 0
75; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
76; 64-C-DAG: c.ult.s $f12, $f13
77; 64-C-DAG: movf $[[T0]], $1, $fcc0
78
79; 32-CMP-DAG: cmp.ole.s $[[T0:f[0-9]+]], $f14, $f12
80; 32-CMP-DAG: mfc1 $2, $[[T0]]
81
82; 64-CMP-DAG: cmp.ole.s $[[T0:f[0-9]+]], $f13, $f12
83; 64-CMP-DAG: mfc1 $2, $[[T0]]
84
85 %1 = fcmp oge float %a, %b
86 %2 = zext i1 %1 to i32
87 ret i32 %2
88}
89
90define i32 @olt_f32(float %a, float %b) nounwind {
91; ALL-LABEL: olt_f32:
92
93; 32-C-DAG: addiu $[[T0:2]], $zero, 0
94; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
95; 32-C-DAG: c.olt.s $f12, $f14
96; 32-C-DAG: movt $[[T0]], $1, $fcc0
97
98; 64-C-DAG: addiu $[[T0:2]], $zero, 0
99; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
100; 64-C-DAG: c.olt.s $f12, $f13
101; 64-C-DAG: movt $[[T0]], $1, $fcc0
102
103; 32-CMP-DAG: cmp.olt.s $[[T0:f[0-9]+]], $f12, $f14
104; 32-CMP-DAG: mfc1 $2, $[[T0]]
105
106; 64-CMP-DAG: cmp.olt.s $[[T0:f[0-9]+]], $f12, $f13
107; 64-CMP-DAG: mfc1 $2, $[[T0]]
108
109 %1 = fcmp olt float %a, %b
110 %2 = zext i1 %1 to i32
111 ret i32 %2
112}
113
114define i32 @ole_f32(float %a, float %b) nounwind {
115; ALL-LABEL: ole_f32:
116
117; 32-C-DAG: addiu $[[T0:2]], $zero, 0
118; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
119; 32-C-DAG: c.ole.s $f12, $f14
120; 32-C-DAG: movt $[[T0]], $1, $fcc0
121
122; 64-C-DAG: addiu $[[T0:2]], $zero, 0
123; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
124; 64-C-DAG: c.ole.s $f12, $f13
125; 64-C-DAG: movt $[[T0]], $1, $fcc0
126
127; 32-CMP-DAG: cmp.ole.s $[[T0:f[0-9]+]], $f12, $f14
128; 32-CMP-DAG: mfc1 $2, $[[T0]]
129
130; 64-CMP-DAG: cmp.ole.s $[[T0:f[0-9]+]], $f12, $f13
131; 64-CMP-DAG: mfc1 $2, $[[T0]]
132
133 %1 = fcmp ole float %a, %b
134 %2 = zext i1 %1 to i32
135 ret i32 %2
136}
137
138define i32 @one_f32(float %a, float %b) nounwind {
139; ALL-LABEL: one_f32:
140
141; 32-C-DAG: addiu $[[T0:2]], $zero, 0
142; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
143; 32-C-DAG: c.ueq.s $f12, $f14
144; 32-C-DAG: movf $[[T0]], $1, $fcc0
145
146; 64-C-DAG: addiu $[[T0:2]], $zero, 0
147; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
148; 64-C-DAG: c.ueq.s $f12, $f13
149; 64-C-DAG: movf $[[T0]], $1, $fcc0
150
151; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
152; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
153; 32-CMP-DAG: not $2, $[[T1]]
154
155; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
156; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
157; 64-CMP-DAG: not $2, $[[T1]]
158
159 %1 = fcmp one float %a, %b
160 %2 = zext i1 %1 to i32
161 ret i32 %2
162}
163
164define i32 @ord_f32(float %a, float %b) nounwind {
165; ALL-LABEL: ord_f32:
166
167; 32-C-DAG: addiu $[[T0:2]], $zero, 0
168; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
169; 32-C-DAG: c.un.s $f12, $f14
170; 32-C-DAG: movf $[[T0]], $1, $fcc0
171
172; 64-C-DAG: addiu $[[T0:2]], $zero, 0
173; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
174; 64-C-DAG: c.un.s $f12, $f13
175; 64-C-DAG: movf $[[T0]], $1, $fcc0
176
177; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
178; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
179; 32-CMP-DAG: not $2, $[[T1]]
180
181; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
182; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
183; 64-CMP-DAG: not $2, $[[T1]]
184
185 %1 = fcmp ord float %a, %b
186 %2 = zext i1 %1 to i32
187 ret i32 %2
188}
189
190define i32 @ueq_f32(float %a, float %b) nounwind {
191; ALL-LABEL: ueq_f32:
192
193; 32-C-DAG: addiu $[[T0:2]], $zero, 0
194; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
195; 32-C-DAG: c.ueq.s $f12, $f14
196; 32-C-DAG: movt $[[T0]], $1, $fcc0
197
198; 64-C-DAG: addiu $[[T0:2]], $zero, 0
199; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
200; 64-C-DAG: c.ueq.s $f12, $f13
201; 64-C-DAG: movt $[[T0]], $1, $fcc0
202
203; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
204; 32-CMP-DAG: mfc1 $2, $[[T0]]
205
206; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
207; 64-CMP-DAG: mfc1 $2, $[[T0]]
208
209 %1 = fcmp ueq float %a, %b
210 %2 = zext i1 %1 to i32
211 ret i32 %2
212}
213
214define i32 @ugt_f32(float %a, float %b) nounwind {
215; ALL-LABEL: ugt_f32:
216
217; 32-C-DAG: addiu $[[T0:2]], $zero, 0
218; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
219; 32-C-DAG: c.ole.s $f12, $f14
220; 32-C-DAG: movf $[[T0]], $1, $fcc0
221
222; 64-C-DAG: addiu $[[T0:2]], $zero, 0
223; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
224; 64-C-DAG: c.ole.s $f12, $f13
225; 64-C-DAG: movf $[[T0]], $1, $fcc0
226
227; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
228; 32-CMP-DAG: mfc1 $2, $[[T0]]
229
230; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
231; 64-CMP-DAG: mfc1 $2, $[[T0]]
232
233 %1 = fcmp ugt float %a, %b
234 %2 = zext i1 %1 to i32
235 ret i32 %2
236}
237
238define i32 @uge_f32(float %a, float %b) nounwind {
239; ALL-LABEL: uge_f32:
240
241; 32-C-DAG: addiu $[[T0:2]], $zero, 0
242; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
243; 32-C-DAG: c.olt.s $f12, $f14
244; 32-C-DAG: movf $[[T0]], $1, $fcc0
245
246; 64-C-DAG: addiu $[[T0:2]], $zero, 0
247; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
248; 64-C-DAG: c.olt.s $f12, $f13
249; 64-C-DAG: movf $[[T0]], $1, $fcc0
250
251; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
252; 32-CMP-DAG: mfc1 $2, $[[T0]]
253
254; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
255; 64-CMP-DAG: mfc1 $2, $[[T0]]
256
257 %1 = fcmp uge float %a, %b
258 %2 = zext i1 %1 to i32
259 ret i32 %2
260}
261
262define i32 @ult_f32(float %a, float %b) nounwind {
263; ALL-LABEL: ult_f32:
264
265; 32-C-DAG: addiu $[[T0:2]], $zero, 0
266; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
267; 32-C-DAG: c.ult.s $f12, $f14
268; 32-C-DAG: movt $[[T0]], $1, $fcc0
269
270; 64-C-DAG: addiu $[[T0:2]], $zero, 0
271; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
272; 64-C-DAG: c.ult.s $f12, $f13
273; 64-C-DAG: movt $[[T0]], $1, $fcc0
274
275; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
276; 32-CMP-DAG: mfc1 $2, $[[T0]]
277
278; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
279; 64-CMP-DAG: mfc1 $2, $[[T0]]
280
281 %1 = fcmp ult float %a, %b
282 %2 = zext i1 %1 to i32
283 ret i32 %2
284}
285
286define i32 @ule_f32(float %a, float %b) nounwind {
287; ALL-LABEL: ule_f32:
288
289; 32-C-DAG: addiu $[[T0:2]], $zero, 0
290; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
291; 32-C-DAG: c.ule.s $f12, $f14
292; 32-C-DAG: movt $[[T0]], $1, $fcc0
293
294; 64-C-DAG: addiu $[[T0:2]], $zero, 0
295; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
296; 64-C-DAG: c.ule.s $f12, $f13
297; 64-C-DAG: movt $[[T0]], $1, $fcc0
298
299; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
300; 32-CMP-DAG: mfc1 $2, $[[T0]]
301
302; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
303; 64-CMP-DAG: mfc1 $2, $[[T0]]
304
305 %1 = fcmp ule float %a, %b
306 %2 = zext i1 %1 to i32
307 ret i32 %2
308}
309
310define i32 @une_f32(float %a, float %b) nounwind {
311; ALL-LABEL: une_f32:
312
313; 32-C-DAG: addiu $[[T0:2]], $zero, 0
314; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
315; 32-C-DAG: c.eq.s $f12, $f14
316; 32-C-DAG: movf $[[T0]], $1, $fcc0
317
318; 64-C-DAG: addiu $[[T0:2]], $zero, 0
319; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
320; 64-C-DAG: c.eq.s $f12, $f13
321; 64-C-DAG: movf $[[T0]], $1, $fcc0
322
323; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
324; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
325; 32-CMP-DAG: not $2, $[[T1]]
326
327; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
328; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
329; 64-CMP-DAG: not $2, $[[T1]]
330
331 %1 = fcmp une float %a, %b
332 %2 = zext i1 %1 to i32
333 ret i32 %2
334}
335
336define i32 @uno_f32(float %a, float %b) nounwind {
337; ALL-LABEL: uno_f32:
338
339; 32-C-DAG: addiu $[[T0:2]], $zero, 0
340; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
341; 32-C-DAG: c.un.s $f12, $f14
342; 32-C-DAG: movt $[[T0]], $1, $fcc0
343
344; 64-C-DAG: addiu $[[T0:2]], $zero, 0
345; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
346; 64-C-DAG: c.un.s $f12, $f13
347; 64-C-DAG: movt $[[T0]], $1, $fcc0
348
349; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
350; 32-CMP-DAG: mfc1 $2, $[[T0]]
351
352; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
353; 64-CMP-DAG: mfc1 $2, $[[T0]]
354
355 %1 = fcmp uno float %a, %b
356 %2 = zext i1 %1 to i32
357 ret i32 %2
358}
359
360define i32 @true_f32(float %a, float %b) nounwind {
361; ALL-LABEL: true_f32:
362; ALL: addiu $2, $zero, 1
363
364 %1 = fcmp true float %a, %b
365 %2 = zext i1 %1 to i32
366 ret i32 %2
367}
368
369define i32 @false_f64(double %a, double %b) nounwind {
370; ALL-LABEL: false_f64:
371; ALL: addiu $2, $zero, 0
372
373 %1 = fcmp false double %a, %b
374 %2 = zext i1 %1 to i32
375 ret i32 %2
376}
377
378define i32 @oeq_f64(double %a, double %b) nounwind {
379; ALL-LABEL: oeq_f64:
380
381; 32-C-DAG: addiu $[[T0:2]], $zero, 0
382; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
383; 32-C-DAG: c.eq.d $f12, $f14
384; 32-C-DAG: movt $[[T0]], $1, $fcc0
385
386; 64-C-DAG: addiu $[[T0:2]], $zero, 0
387; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
388; 64-C-DAG: c.eq.d $f12, $f13
389; 64-C-DAG: movt $[[T0]], $1, $fcc0
390
391; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
392; 32-CMP-DAG: mfc1 $2, $[[T0]]
393
394; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
395; 64-CMP-DAG: mfc1 $2, $[[T0]]
396
397 %1 = fcmp oeq double %a, %b
398 %2 = zext i1 %1 to i32
399 ret i32 %2
400}
401
402define i32 @ogt_f64(double %a, double %b) nounwind {
403; ALL-LABEL: ogt_f64:
404
405; 32-C-DAG: addiu $[[T0:2]], $zero, 0
406; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
407; 32-C-DAG: c.ule.d $f12, $f14
408; 32-C-DAG: movf $[[T0]], $1, $fcc0
409
410; 64-C-DAG: addiu $[[T0:2]], $zero, 0
411; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
412; 64-C-DAG: c.ule.d $f12, $f13
413; 64-C-DAG: movf $[[T0]], $1, $fcc0
414
415; 32-CMP-DAG: cmp.olt.d $[[T0:f[0-9]+]], $f14, $f12
416; 32-CMP-DAG: mfc1 $2, $[[T0]]
417
418; 64-CMP-DAG: cmp.olt.d $[[T0:f[0-9]+]], $f13, $f12
419; 64-CMP-DAG: mfc1 $2, $[[T0]]
420
421 %1 = fcmp ogt double %a, %b
422 %2 = zext i1 %1 to i32
423 ret i32 %2
424}
425
426define i32 @oge_f64(double %a, double %b) nounwind {
427; ALL-LABEL: oge_f64:
428
429; 32-C-DAG: addiu $[[T0:2]], $zero, 0
430; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
431; 32-C-DAG: c.ult.d $f12, $f14
432; 32-C-DAG: movf $[[T0]], $1, $fcc0
433
434; 64-C-DAG: addiu $[[T0:2]], $zero, 0
435; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
436; 64-C-DAG: c.ult.d $f12, $f13
437; 64-C-DAG: movf $[[T0]], $1, $fcc0
438
439; 32-CMP-DAG: cmp.ole.d $[[T0:f[0-9]+]], $f14, $f12
440; 32-CMP-DAG: mfc1 $2, $[[T0]]
441
442; 64-CMP-DAG: cmp.ole.d $[[T0:f[0-9]+]], $f13, $f12
443; 64-CMP-DAG: mfc1 $2, $[[T0]]
444
445 %1 = fcmp oge double %a, %b
446 %2 = zext i1 %1 to i32
447 ret i32 %2
448}
449
450define i32 @olt_f64(double %a, double %b) nounwind {
451; ALL-LABEL: olt_f64:
452
453; 32-C-DAG: addiu $[[T0:2]], $zero, 0
454; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
455; 32-C-DAG: c.olt.d $f12, $f14
456; 32-C-DAG: movt $[[T0]], $1, $fcc0
457
458; 64-C-DAG: addiu $[[T0:2]], $zero, 0
459; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
460; 64-C-DAG: c.olt.d $f12, $f13
461; 64-C-DAG: movt $[[T0]], $1, $fcc0
462
463; 32-CMP-DAG: cmp.olt.d $[[T0:f[0-9]+]], $f12, $f14
464; 32-CMP-DAG: mfc1 $2, $[[T0]]
465
466; 64-CMP-DAG: cmp.olt.d $[[T0:f[0-9]+]], $f12, $f13
467; 64-CMP-DAG: mfc1 $2, $[[T0]]
468
469 %1 = fcmp olt double %a, %b
470 %2 = zext i1 %1 to i32
471 ret i32 %2
472}
473
474define i32 @ole_f64(double %a, double %b) nounwind {
475; ALL-LABEL: ole_f64:
476
477; 32-C-DAG: addiu $[[T0:2]], $zero, 0
478; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
479; 32-C-DAG: c.ole.d $f12, $f14
480; 32-C-DAG: movt $[[T0]], $1, $fcc0
481
482; 64-C-DAG: addiu $[[T0:2]], $zero, 0
483; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
484; 64-C-DAG: c.ole.d $f12, $f13
485; 64-C-DAG: movt $[[T0]], $1, $fcc0
486
487; 32-CMP-DAG: cmp.ole.d $[[T0:f[0-9]+]], $f12, $f14
488; 32-CMP-DAG: mfc1 $2, $[[T0]]
489
490; 64-CMP-DAG: cmp.ole.d $[[T0:f[0-9]+]], $f12, $f13
491; 64-CMP-DAG: mfc1 $2, $[[T0]]
492
493 %1 = fcmp ole double %a, %b
494 %2 = zext i1 %1 to i32
495 ret i32 %2
496}
497
498define i32 @one_f64(double %a, double %b) nounwind {
499; ALL-LABEL: one_f64:
500
501; 32-C-DAG: addiu $[[T0:2]], $zero, 0
502; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
503; 32-C-DAG: c.ueq.d $f12, $f14
504; 32-C-DAG: movf $[[T0]], $1, $fcc0
505
506; 64-C-DAG: addiu $[[T0:2]], $zero, 0
507; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
508; 64-C-DAG: c.ueq.d $f12, $f13
509; 64-C-DAG: movf $[[T0]], $1, $fcc0
510
511; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
512; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
513; 32-CMP-DAG: not $2, $[[T1]]
514
515; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
516; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
517; 64-CMP-DAG: not $2, $[[T1]]
518
519 %1 = fcmp one double %a, %b
520 %2 = zext i1 %1 to i32
521 ret i32 %2
522}
523
524define i32 @ord_f64(double %a, double %b) nounwind {
525; ALL-LABEL: ord_f64:
526
527; 32-C-DAG: addiu $[[T0:2]], $zero, 0
528; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
529; 32-C-DAG: c.un.d $f12, $f14
530; 32-C-DAG: movf $[[T0]], $1, $fcc0
531
532; 64-C-DAG: addiu $[[T0:2]], $zero, 0
533; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
534; 64-C-DAG: c.un.d $f12, $f13
535; 64-C-DAG: movf $[[T0]], $1, $fcc0
536
537; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
538; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
539; 32-CMP-DAG: not $2, $[[T1]]
540
541; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
542; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
543; 64-CMP-DAG: not $2, $[[T1]]
544
545 %1 = fcmp ord double %a, %b
546 %2 = zext i1 %1 to i32
547 ret i32 %2
548}
549
550define i32 @ueq_f64(double %a, double %b) nounwind {
551; ALL-LABEL: ueq_f64:
552
553; 32-C-DAG: addiu $[[T0:2]], $zero, 0
554; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
555; 32-C-DAG: c.ueq.d $f12, $f14
556; 32-C-DAG: movt $[[T0]], $1, $fcc0
557
558; 64-C-DAG: addiu $[[T0:2]], $zero, 0
559; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
560; 64-C-DAG: c.ueq.d $f12, $f13
561; 64-C-DAG: movt $[[T0]], $1, $fcc0
562
563; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
564; 32-CMP-DAG: mfc1 $2, $[[T0]]
565
566; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
567; 64-CMP-DAG: mfc1 $2, $[[T0]]
568
569 %1 = fcmp ueq double %a, %b
570 %2 = zext i1 %1 to i32
571 ret i32 %2
572}
573
574define i32 @ugt_f64(double %a, double %b) nounwind {
575; ALL-LABEL: ugt_f64:
576
577; 32-C-DAG: addiu $[[T0:2]], $zero, 0
578; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
579; 32-C-DAG: c.ole.d $f12, $f14
580; 32-C-DAG: movf $[[T0]], $1, $fcc0
581
582; 64-C-DAG: addiu $[[T0:2]], $zero, 0
583; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
584; 64-C-DAG: c.ole.d $f12, $f13
585; 64-C-DAG: movf $[[T0]], $1, $fcc0
586
587; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
588; 32-CMP-DAG: mfc1 $2, $[[T0]]
589
590; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
591; 64-CMP-DAG: mfc1 $2, $[[T0]]
592
593 %1 = fcmp ugt double %a, %b
594 %2 = zext i1 %1 to i32
595 ret i32 %2
596}
597
598define i32 @uge_f64(double %a, double %b) nounwind {
599; ALL-LABEL: uge_f64:
600
601; 32-C-DAG: addiu $[[T0:2]], $zero, 0
602; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
603; 32-C-DAG: c.olt.d $f12, $f14
604; 32-C-DAG: movf $[[T0]], $1, $fcc0
605
606; 64-C-DAG: addiu $[[T0:2]], $zero, 0
607; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
608; 64-C-DAG: c.olt.d $f12, $f13
609; 64-C-DAG: movf $[[T0]], $1, $fcc0
610
611; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
612; 32-CMP-DAG: mfc1 $2, $[[T0]]
613
614; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
615; 64-CMP-DAG: mfc1 $2, $[[T0]]
616
617 %1 = fcmp uge double %a, %b
618 %2 = zext i1 %1 to i32
619 ret i32 %2
620}
621
622define i32 @ult_f64(double %a, double %b) nounwind {
623; ALL-LABEL: ult_f64:
624
625; 32-C-DAG: addiu $[[T0:2]], $zero, 0
626; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
627; 32-C-DAG: c.ult.d $f12, $f14
628; 32-C-DAG: movt $[[T0]], $1, $fcc0
629
630; 64-C-DAG: addiu $[[T0:2]], $zero, 0
631; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
632; 64-C-DAG: c.ult.d $f12, $f13
633; 64-C-DAG: movt $[[T0]], $1, $fcc0
634
635; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
636; 32-CMP-DAG: mfc1 $2, $[[T0]]
637
638; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
639; 64-CMP-DAG: mfc1 $2, $[[T0]]
640
641 %1 = fcmp ult double %a, %b
642 %2 = zext i1 %1 to i32
643 ret i32 %2
644}
645
646define i32 @ule_f64(double %a, double %b) nounwind {
647; ALL-LABEL: ule_f64:
648
649; 32-C-DAG: addiu $[[T0:2]], $zero, 0
650; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
651; 32-C-DAG: c.ule.d $f12, $f14
652; 32-C-DAG: movt $[[T0]], $1, $fcc0
653
654; 64-C-DAG: addiu $[[T0:2]], $zero, 0
655; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
656; 64-C-DAG: c.ule.d $f12, $f13
657; 64-C-DAG: movt $[[T0]], $1, $fcc0
658
659; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
660; 32-CMP-DAG: mfc1 $2, $[[T0]]
661
662; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
663; 64-CMP-DAG: mfc1 $2, $[[T0]]
664
665 %1 = fcmp ule double %a, %b
666 %2 = zext i1 %1 to i32
667 ret i32 %2
668}
669
670define i32 @une_f64(double %a, double %b) nounwind {
671; ALL-LABEL: une_f64:
672
673; 32-C-DAG: addiu $[[T0:2]], $zero, 0
674; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
675; 32-C-DAG: c.eq.d $f12, $f14
676; 32-C-DAG: movf $[[T0]], $1, $fcc0
677
678; 64-C-DAG: addiu $[[T0:2]], $zero, 0
679; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
680; 64-C-DAG: c.eq.d $f12, $f13
681; 64-C-DAG: movf $[[T0]], $1, $fcc0
682
683; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
684; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
685; 32-CMP-DAG: not $2, $[[T1]]
686
687; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
688; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
689; 64-CMP-DAG: not $2, $[[T1]]
690
691 %1 = fcmp une double %a, %b
692 %2 = zext i1 %1 to i32
693 ret i32 %2
694}
695
696define i32 @uno_f64(double %a, double %b) nounwind {
697; ALL-LABEL: uno_f64:
698
699; 32-C-DAG: addiu $[[T0:2]], $zero, 0
700; 32-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
701; 32-C-DAG: c.un.d $f12, $f14
702; 32-C-DAG: movt $[[T0]], $1, $fcc0
703
704; 64-C-DAG: addiu $[[T0:2]], $zero, 0
705; 64-C-DAG: addiu $[[T1:[0-9]+]], $zero, 1
706; 64-C-DAG: c.un.d $f12, $f13
707; 64-C-DAG: movt $[[T0]], $1, $fcc0
708
709; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
710; 32-CMP-DAG: mfc1 $2, $[[T0]]
711
712; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
713; 64-CMP-DAG: mfc1 $2, $[[T0]]
714
715 %1 = fcmp uno double %a, %b
716 %2 = zext i1 %1 to i32
717 ret i32 %2
718}
719
720define i32 @true_f64(double %a, double %b) nounwind {
721; ALL-LABEL: true_f64:
722; ALL: addiu $2, $zero, 1
723
724 %1 = fcmp true double %a, %b
725 %2 = zext i1 %1 to i32
726 ret i32 %2
727}