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gerrit-public.fairphone.software / toolchain / llvm-project / 108e98ec32ba61a19965611206633cd2ebb0d6ba / . / llvm / lib / Target / WebAssembly / WebAssemblyInstrSIMD.td
blob: 28262fbcaf67cfca087c815358a58c9876996a31 [file] [log] [blame]
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]1// WebAssemblyInstrSIMD.td - WebAssembly SIMD codegen support -*- tablegen -*-//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
JF Bastien5ca0bac2015-07-10 18:23:10 +0000[diff] [blame]9///
10/// \file
Adrian Prantl5f8f34e42018-05-01 15:54:18 +0000[diff] [blame]11/// WebAssembly SIMD operand code-gen constructs.
JF Bastien5ca0bac2015-07-10 18:23:10 +0000[diff] [blame]12///
Dan Gohman10e730a2015-06-29 23:51:55 +0000[diff] [blame]13//===----------------------------------------------------------------------===//
14
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]15// Instructions requiring HasSIMD128 and the simd128 prefix byte
16multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
17 list<dag> pattern_r, string asmstr_r = "",
18 string asmstr_s = "", bits<32> simdop = -1> {
19 defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
20 !or(0xfd00, !and(0xff, simdop))>,
21 Requires<[HasSIMD128]>;
22}
23
24multiclass SIMD_ARGUMENT<ValueType vt> {
25 let hasSideEffects = 1, Uses = [ARGUMENTS], isCodeGenOnly = 1 in
26 defm ARGUMENT_#vt : SIMD_I<(outs V128:$res), (ins i32imm:$argno),
27 (outs), (ins i32imm:$argno),
28 [(set (vt V128:$res),
29 (WebAssemblyargument timm:$argno))]>;
30}
31
32defm "": SIMD_ARGUMENT<v16i8>;
33defm "": SIMD_ARGUMENT<v8i16>;
34defm "": SIMD_ARGUMENT<v4i32>;
35defm "": SIMD_ARGUMENT<v2i64>;
36defm "": SIMD_ARGUMENT<v4f32>;
37defm "": SIMD_ARGUMENT<v2f64>;
38
39// Constrained immediate argument types
Thomas Lively22442922018-08-21 21:03:18 +0000[diff] [blame]40foreach SIZE = [8, 16] in
41def ImmI#SIZE : ImmLeaf<i32, "return (Imm & ((1UL << "#SIZE#") - 1)) == Imm;">;
Heejin Ahna0fd9c32018-08-14 18:53:27 +0000[diff] [blame]42foreach SIZE = [2, 4, 8, 16, 32] in
43def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
Derek Schuff51ed1312018-08-07 21:24:01 +0000[diff] [blame]44
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]45//===----------------------------------------------------------------------===//
46// Constructing SIMD values
47//===----------------------------------------------------------------------===//
Thomas Lively9075cd62018-10-03 00:19:39 +0000[diff] [blame]48
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]49// Constant: v128.const
Thomas Lively22442922018-08-21 21:03:18 +0000[diff] [blame]50multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
Thomas Lively65825cd2018-09-13 02:50:57 +0000[diff] [blame]51 let isMoveImm = 1, isReMaterializable = 1 in
Thomas Lively22442922018-08-21 21:03:18 +0000[diff] [blame]52 defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
53 [(set V128:$dst, (vec_t pat))],
54 "v128.const\t$dst, "#args,
55 "v128.const\t"#args, 0>;
56}
Thomas Lively123c3bb2018-08-23 00:43:47 +0000[diff] [blame]57
58let Defs = [ARGUMENTS] in {
Thomas Lively22442922018-08-21 21:03:18 +0000[diff] [blame]59defm "" : ConstVec<v16i8,
60 (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
61 vec_i8imm_op:$i2, vec_i8imm_op:$i3,
62 vec_i8imm_op:$i4, vec_i8imm_op:$i5,
63 vec_i8imm_op:$i6, vec_i8imm_op:$i7,
64 vec_i8imm_op:$i8, vec_i8imm_op:$i9,
65 vec_i8imm_op:$iA, vec_i8imm_op:$iB,
66 vec_i8imm_op:$iC, vec_i8imm_op:$iD,
67 vec_i8imm_op:$iE, vec_i8imm_op:$iF),
68 (build_vector ImmI8:$i0, ImmI8:$i1, ImmI8:$i2, ImmI8:$i3,
69 ImmI8:$i4, ImmI8:$i5, ImmI8:$i6, ImmI8:$i7,
70 ImmI8:$i8, ImmI8:$i9, ImmI8:$iA, ImmI8:$iB,
71 ImmI8:$iC, ImmI8:$iD, ImmI8:$iE, ImmI8:$iF),
72 !strconcat("$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7, ",
73 "$i8, $i9, $iA, $iB, $iC, $iD, $iE, $iF")>;
74defm "" : ConstVec<v8i16,
75 (ins vec_i16imm_op:$i0, vec_i16imm_op:$i1,
76 vec_i16imm_op:$i2, vec_i16imm_op:$i3,
77 vec_i16imm_op:$i4, vec_i16imm_op:$i5,
78 vec_i16imm_op:$i6, vec_i16imm_op:$i7),
79 (build_vector
80 ImmI16:$i0, ImmI16:$i1, ImmI16:$i2, ImmI16:$i3,
81 ImmI16:$i4, ImmI16:$i5, ImmI16:$i6, ImmI16:$i7),
82 "$i0, $i1, $i2, $i3, $i4, $i5, $i6, $i7">;
83defm "" : ConstVec<v4i32,
84 (ins vec_i32imm_op:$i0, vec_i32imm_op:$i1,
85 vec_i32imm_op:$i2, vec_i32imm_op:$i3),
86 (build_vector (i32 imm:$i0), (i32 imm:$i1),
87 (i32 imm:$i2), (i32 imm:$i3)),
88 "$i0, $i1, $i2, $i3">;
89defm "" : ConstVec<v2i64,
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]90 (ins vec_i64imm_op:$i0, vec_i64imm_op:$i1),
91 (build_vector (i64 imm:$i0), (i64 imm:$i1)),
92 "$i0, $i1">;
Thomas Lively22442922018-08-21 21:03:18 +0000[diff] [blame]93defm "" : ConstVec<v4f32,
94 (ins f32imm_op:$i0, f32imm_op:$i1,
95 f32imm_op:$i2, f32imm_op:$i3),
96 (build_vector (f32 fpimm:$i0), (f32 fpimm:$i1),
97 (f32 fpimm:$i2), (f32 fpimm:$i3)),
98 "$i0, $i1, $i2, $i3">;
99defm "" : ConstVec<v2f64,
100 (ins f64imm_op:$i0, f64imm_op:$i1),
101 (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)),
102 "$i0, $i1">;
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]103} // Defs = [ARGUMENTS]
Thomas Livelyc1742572018-08-23 00:48:37 +0000[diff] [blame]104
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]105// Create vector with identical lanes: splat
106def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>;
107def splat4 : PatFrag<(ops node:$x), (build_vector
108 node:$x, node:$x, node:$x, node:$x)>;
109def splat8 : PatFrag<(ops node:$x), (build_vector
110 node:$x, node:$x, node:$x, node:$x,
111 node:$x, node:$x, node:$x, node:$x)>;
112def splat16 : PatFrag<(ops node:$x), (build_vector
113 node:$x, node:$x, node:$x, node:$x,
114 node:$x, node:$x, node:$x, node:$x,
115 node:$x, node:$x, node:$x, node:$x,
116 node:$x, node:$x, node:$x, node:$x)>;
117
118multiclass Splat<ValueType vec_t, string vec, WebAssemblyRegClass reg_t,
119 PatFrag splat_pat, bits<32> simdop> {
120 // Prefer splats over v128.const for const splats (65 is lowest that works)
121 let AddedComplexity = 65 in
122 defm SPLAT_#vec_t : SIMD_I<(outs V128:$dst), (ins reg_t:$x), (outs), (ins),
123 [(set (vec_t V128:$dst), (splat_pat reg_t:$x))],
124 vec#".splat\t$dst, $x", vec#".splat", simdop>;
125}
126
127defm "" : Splat<v16i8, "i8x16", I32, splat16, 3>;
128defm "" : Splat<v8i16, "i16x8", I32, splat8, 4>;
129defm "" : Splat<v4i32, "i32x4", I32, splat4, 5>;
130defm "" : Splat<v2i64, "i64x2", I64, splat2, 6>;
131defm "" : Splat<v4f32, "f32x4", F32, splat4, 7>;
132defm "" : Splat<v2f64, "f64x2", F64, splat2, 8>;
133
134//===----------------------------------------------------------------------===//
135// Accessing lanes
136//===----------------------------------------------------------------------===//
137
138// Extract lane as a scalar: extract_lane / extract_lane_s / extract_lane_u
139multiclass ExtractLane<ValueType vec_t, string vec, ImmLeaf imm_t,
140 WebAssemblyRegClass reg_t, bits<32> simdop,
141 string suffix = "", SDNode extract = vector_extract> {
142 defm EXTRACT_LANE_#vec_t#suffix :
143 SIMD_I<(outs reg_t:$dst), (ins V128:$vec, vec_i8imm_op:$idx),
144 (outs), (ins vec_i8imm_op:$idx),
145 [(set reg_t:$dst, (extract (vec_t V128:$vec), (i32 imm_t:$idx)))],
146 vec#".extract_lane"#suffix#"\t$dst, $vec, $idx",
147 vec#".extract_lane"#suffix#"\t$idx", simdop>;
148}
149
150multiclass ExtractPat<ValueType lane_t, int mask> {
151 def _s : PatFrag<(ops node:$vec, node:$idx),
152 (i32 (sext_inreg
153 (i32 (vector_extract
154 node:$vec,
155 node:$idx
156 )),
157 lane_t
158 ))>;
159 def _u : PatFrag<(ops node:$vec, node:$idx),
160 (i32 (and
161 (i32 (vector_extract
162 node:$vec,
163 node:$idx
164 )),
165 (i32 mask)
166 ))>;
167}
168
169defm extract_i8x16 : ExtractPat<i8, 0xff>;
170defm extract_i16x8 : ExtractPat<i16, 0xffff>;
171
172multiclass ExtractLaneExtended<string sign, bits<32> baseInst> {
173 defm "" : ExtractLane<v16i8, "i8x16", LaneIdx16, I32, baseInst, sign,
174 !cast<PatFrag>("extract_i8x16"#sign)>;
175 defm "" : ExtractLane<v8i16, "i16x8", LaneIdx8, I32, !add(baseInst, 2), sign,
176 !cast<PatFrag>("extract_i16x8"#sign)>;
Thomas Livelyd183d8c2018-08-30 21:36:48 +0000[diff] [blame]177}
178
Thomas Lively5222cb62018-08-15 18:15:18 +0000[diff] [blame]179defm "" : ExtractLaneExtended<"_s", 9>;
180defm "" : ExtractLaneExtended<"_u", 10>;
181defm "" : ExtractLane<v4i32, "i32x4", LaneIdx4, I32, 13>;
182defm "" : ExtractLane<v2i64, "i64x2", LaneIdx2, I64, 14>;
183defm "" : ExtractLane<v4f32, "f32x4", LaneIdx4, F32, 15>;
184defm "" : ExtractLane<v2f64, "f64x2", LaneIdx2, F64, 16>;
Thomas Livelyc1742572018-08-23 00:48:37 +0000[diff] [blame]185
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]186// Follow convention of making implicit expansions unsigned
187def : Pat<(i32 (vector_extract (v16i8 V128:$vec), (i32 LaneIdx16:$idx))),
188 (EXTRACT_LANE_v16i8_u V128:$vec, (i32 LaneIdx16:$idx))>;
189def : Pat<(i32 (vector_extract (v8i16 V128:$vec), (i32 LaneIdx8:$idx))),
190 (EXTRACT_LANE_v8i16_u V128:$vec, (i32 LaneIdx8:$idx))>;
191
192// Replace lane value: replace_lane
193multiclass ReplaceLane<ValueType vec_t, string vec, ImmLeaf imm_t,
194 WebAssemblyRegClass reg_t, ValueType lane_t,
195 bits<32> simdop> {
196 defm REPLACE_LANE_#vec_t :
197 SIMD_I<(outs V128:$dst), (ins V128:$vec, vec_i8imm_op:$idx, reg_t:$x),
198 (outs), (ins vec_i8imm_op:$idx),
199 [(set V128:$dst, (vector_insert
200 (vec_t V128:$vec), (lane_t reg_t:$x), (i32 imm_t:$idx)))],
201 vec#".replace_lane\t$dst, $vec, $idx, $x",
202 vec#".replace_lane\t$idx", simdop>;
203}
204
Thomas Lively123c3bb2018-08-23 00:43:47 +0000[diff] [blame]205defm "" : ReplaceLane<v16i8, "i8x16", LaneIdx16, I32, i32, 17>;
206defm "" : ReplaceLane<v8i16, "i16x8", LaneIdx8, I32, i32, 18>;
207defm "" : ReplaceLane<v4i32, "i32x4", LaneIdx4, I32, i32, 19>;
208defm "" : ReplaceLane<v2i64, "i64x2", LaneIdx2, I64, i64, 20>;
209defm "" : ReplaceLane<v4f32, "f32x4", LaneIdx4, F32, f32, 21>;
210defm "" : ReplaceLane<v2f64, "f64x2", LaneIdx2, F64, f64, 22>;
Thomas Livelyc1742572018-08-23 00:48:37 +0000[diff] [blame]211
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]212// Arbitrary other BUILD_VECTOR patterns
Thomas Lively2ee686d2018-08-22 23:06:27 +0000[diff] [blame]213def : Pat<(v16i8 (build_vector
214 (i32 I32:$x0), (i32 I32:$x1), (i32 I32:$x2), (i32 I32:$x3),
215 (i32 I32:$x4), (i32 I32:$x5), (i32 I32:$x6), (i32 I32:$x7),
216 (i32 I32:$x8), (i32 I32:$x9), (i32 I32:$x10), (i32 I32:$x11),
217 (i32 I32:$x12), (i32 I32:$x13), (i32 I32:$x14), (i32 I32:$x15)
218 )),
219 (v16i8 (REPLACE_LANE_v16i8
220 (v16i8 (REPLACE_LANE_v16i8
221 (v16i8 (REPLACE_LANE_v16i8
222 (v16i8 (REPLACE_LANE_v16i8
223 (v16i8 (REPLACE_LANE_v16i8
224 (v16i8 (REPLACE_LANE_v16i8
225 (v16i8 (REPLACE_LANE_v16i8
226 (v16i8 (REPLACE_LANE_v16i8
227 (v16i8 (REPLACE_LANE_v16i8
228 (v16i8 (REPLACE_LANE_v16i8
229 (v16i8 (REPLACE_LANE_v16i8
230 (v16i8 (REPLACE_LANE_v16i8
231 (v16i8 (REPLACE_LANE_v16i8
232 (v16i8 (REPLACE_LANE_v16i8
233 (v16i8 (REPLACE_LANE_v16i8
234 (v16i8 (SPLAT_v16i8 (i32 I32:$x0))),
235 1, I32:$x1
236 )),
237 2, I32:$x2
238 )),
239 3, I32:$x3
240 )),
241 4, I32:$x4
242 )),
243 5, I32:$x5
244 )),
245 6, I32:$x6
246 )),
247 7, I32:$x7
248 )),
249 8, I32:$x8
250 )),
251 9, I32:$x9
252 )),
253 10, I32:$x10
254 )),
255 11, I32:$x11
256 )),
257 12, I32:$x12
258 )),
259 13, I32:$x13
260 )),
261 14, I32:$x14
262 )),
263 15, I32:$x15
264 ))>;
265def : Pat<(v8i16 (build_vector
266 (i32 I32:$x0), (i32 I32:$x1), (i32 I32:$x2), (i32 I32:$x3),
267 (i32 I32:$x4), (i32 I32:$x5), (i32 I32:$x6), (i32 I32:$x7)
268 )),
269 (v8i16 (REPLACE_LANE_v8i16
270 (v8i16 (REPLACE_LANE_v8i16
271 (v8i16 (REPLACE_LANE_v8i16
272 (v8i16 (REPLACE_LANE_v8i16
273 (v8i16 (REPLACE_LANE_v8i16
274 (v8i16 (REPLACE_LANE_v8i16
275 (v8i16 (REPLACE_LANE_v8i16
276 (v8i16 (SPLAT_v8i16 (i32 I32:$x0))),
277 1, I32:$x1
278 )),
279 2, I32:$x2
280 )),
281 3, I32:$x3
282 )),
283 4, I32:$x4
284 )),
285 5, I32:$x5
286 )),
287 6, I32:$x6
288 )),
289 7, I32:$x7
290 ))>;
291def : Pat<(v4i32 (build_vector
292 (i32 I32:$x0), (i32 I32:$x1), (i32 I32:$x2), (i32 I32:$x3)
293 )),
294 (v4i32 (REPLACE_LANE_v4i32
295 (v4i32 (REPLACE_LANE_v4i32
296 (v4i32 (REPLACE_LANE_v4i32
297 (v4i32 (SPLAT_v4i32 (i32 I32:$x0))),
298 1, I32:$x1
299 )),
300 2, I32:$x2
301 )),
302 3, I32:$x3
303 ))>;
304def : Pat<(v2i64 (build_vector (i64 I64:$x0), (i64 I64:$x1))),
305 (v2i64 (REPLACE_LANE_v2i64
306 (v2i64 (SPLAT_v2i64 (i64 I64:$x0))), 1, I64:$x1))>;
307def : Pat<(v4f32 (build_vector
308 (f32 F32:$x0), (f32 F32:$x1), (f32 F32:$x2), (f32 F32:$x3)
309 )),
310 (v4f32 (REPLACE_LANE_v4f32
311 (v4f32 (REPLACE_LANE_v4f32
312 (v4f32 (REPLACE_LANE_v4f32
313 (v4f32 (SPLAT_v4f32 (f32 F32:$x0))),
314 1, F32:$x1
315 )),
316 2, F32:$x2
317 )),
318 3, F32:$x3
319 ))>;
320def : Pat<(v2f64 (build_vector (f64 F64:$x0), (f64 F64:$x1))),
321 (v2f64 (REPLACE_LANE_v2f64
322 (v2f64 (SPLAT_v2f64 (f64 F64:$x0))), 1, F64:$x1))>;
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]323
324// Shuffle lanes: shuffle
325defm SHUFFLE_v16i8 :
326 SIMD_I<(outs V128:$dst),
327 (ins V128:$x, V128:$y,
328 vec_i8imm_op:$m0, vec_i8imm_op:$m1,
329 vec_i8imm_op:$m2, vec_i8imm_op:$m3,
330 vec_i8imm_op:$m4, vec_i8imm_op:$m5,
331 vec_i8imm_op:$m6, vec_i8imm_op:$m7,
332 vec_i8imm_op:$m8, vec_i8imm_op:$m9,
333 vec_i8imm_op:$mA, vec_i8imm_op:$mB,
334 vec_i8imm_op:$mC, vec_i8imm_op:$mD,
335 vec_i8imm_op:$mE, vec_i8imm_op:$mF),
336 (outs),
337 (ins
338 vec_i8imm_op:$m0, vec_i8imm_op:$m1,
339 vec_i8imm_op:$m2, vec_i8imm_op:$m3,
340 vec_i8imm_op:$m4, vec_i8imm_op:$m5,
341 vec_i8imm_op:$m6, vec_i8imm_op:$m7,
342 vec_i8imm_op:$m8, vec_i8imm_op:$m9,
343 vec_i8imm_op:$mA, vec_i8imm_op:$mB,
344 vec_i8imm_op:$mC, vec_i8imm_op:$mD,
345 vec_i8imm_op:$mE, vec_i8imm_op:$mF),
346 [],
347 "v8x16.shuffle\t$dst, $x, $y, "#
348 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
349 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
350 "v8x16.shuffle\t"#
351 "$m0, $m1, $m2, $m3, $m4, $m5, $m6, $m7, "#
352 "$m8, $m9, $mA, $mB, $mC, $mD, $mE, $mF",
353 23>;
354
355// Shuffles after custom lowering
356def wasm_shuffle_t : SDTypeProfile<1, 18, []>;
357def wasm_shuffle : SDNode<"WebAssemblyISD::SHUFFLE", wasm_shuffle_t>;
358foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
359def : Pat<(v16i8 (wasm_shuffle (vec_t V128:$x), (vec_t V128:$y),
360 (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
361 (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
362 (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
363 (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
364 (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
365 (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
366 (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
367 (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF))),
368 (v16i8 (SHUFFLE_v16i8 (vec_t V128:$x), (vec_t V128:$y),
369 (i32 LaneIdx32:$m0), (i32 LaneIdx32:$m1),
370 (i32 LaneIdx32:$m2), (i32 LaneIdx32:$m3),
371 (i32 LaneIdx32:$m4), (i32 LaneIdx32:$m5),
372 (i32 LaneIdx32:$m6), (i32 LaneIdx32:$m7),
373 (i32 LaneIdx32:$m8), (i32 LaneIdx32:$m9),
374 (i32 LaneIdx32:$mA), (i32 LaneIdx32:$mB),
375 (i32 LaneIdx32:$mC), (i32 LaneIdx32:$mD),
376 (i32 LaneIdx32:$mE), (i32 LaneIdx32:$mF)))>;
377}
378
379//===----------------------------------------------------------------------===//
380// Integer arithmetic
381//===----------------------------------------------------------------------===//
382
383multiclass SIMDBinary<ValueType vec_t, string vec, SDNode node, string name,
384 bits<32> simdop> {
385 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs),
386 (outs), (ins),
387 [(set (vec_t V128:$dst), (node V128:$lhs, V128:$rhs))],
388 vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name,
389 simdop>;
390}
391
392multiclass SIMDBinaryIntNoI64x2<SDNode node, string name, bits<32> baseInst> {
393 defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>;
394 defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 1)>;
395 defm "" : SIMDBinary<v4i32, "i32x4", node, name, !add(baseInst, 2)>;
396}
397
398multiclass SIMDBinaryInt<SDNode node, string name, bits<32> baseInst> {
399 defm "" : SIMDBinaryIntNoI64x2<node, name, baseInst>;
400 defm "" : SIMDBinary<v2i64, "i64x2", node, name, !add(baseInst, 3)>;
401}
402
Thomas Lively108e98e2018-10-10 01:09:09 +0000[diff] [blame^]403// Integer vector negation
404def ivneg : PatFrag<(ops node:$in), (sub immAllZerosV, node:$in)>;
405
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]406// Integer addition: add
407let isCommutable = 1 in
408defm ADD : SIMDBinaryInt<add, "add", 24>;
409
410// Integer subtraction: sub
411defm SUB : SIMDBinaryInt<sub, "sub", 28>;
412
413// Integer multiplication: mul
414defm MUL : SIMDBinaryIntNoI64x2<mul, "mul", 32>;
415
416// Integer negation: neg
Thomas Lively108e98e2018-10-10 01:09:09 +0000[diff] [blame^]417multiclass SIMDNeg<ValueType vec_t, string vec, SDNode neg, bits<32> simdop> {
418 defm NEG_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
419 [(set (vec_t V128:$dst),
420 (vec_t (neg (vec_t V128:$vec)))
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]421 )],
422 vec#".neg\t$dst, $vec", vec#".neg", simdop>;
423}
424
Thomas Lively108e98e2018-10-10 01:09:09 +0000[diff] [blame^]425defm "" : SIMDNeg<v16i8, "i8x16", ivneg, 36>;
426defm "" : SIMDNeg<v8i16, "i16x8", ivneg, 37>;
427defm "" : SIMDNeg<v4i32, "i32x4", ivneg, 38>;
428defm "" : SIMDNeg<v2i64, "i64x2", ivneg, 39>;
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]429
430//===----------------------------------------------------------------------===//
431// Saturating integer arithmetic
432//===----------------------------------------------------------------------===//
433
434multiclass SIMDBinarySat<SDNode node, string name, bits<32> baseInst> {
435 defm "" : SIMDBinary<v16i8, "i8x16", node, name, baseInst>;
436 defm "" : SIMDBinary<v8i16, "i16x8", node, name, !add(baseInst, 2)>;
437}
438
439def wasm_saturate_t : SDTypeProfile<1, 2,
440 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>]
441>;
442def wasm_add_sat_s : SDNode<"WebAssemblyISD::ADD_SAT_S", wasm_saturate_t>;
443def wasm_add_sat_u : SDNode<"WebAssemblyISD::ADD_SAT_U", wasm_saturate_t>;
444def wasm_sub_sat_s : SDNode<"WebAssemblyISD::SUB_SAT_S", wasm_saturate_t>;
445def wasm_sub_sat_u : SDNode<"WebAssemblyISD::SUB_SAT_U", wasm_saturate_t>;
446
447// Saturating integer addition: add_saturate_s / add_saturate_u
448let isCommutable = 1 in {
449defm ADD_SAT_S : SIMDBinarySat<wasm_add_sat_s, "add_saturate_s", 40>;
450defm ADD_SAT_U : SIMDBinarySat<wasm_add_sat_u, "add_saturate_u", 41>;
451} // isCommutable = 1
452
453// Saturating integer subtraction: sub_saturate_s / sub_saturate_u
454defm SUB_SAT_S : SIMDBinarySat<wasm_sub_sat_s, "sub_saturate_s", 44>;
455defm SUB_SAT_U : SIMDBinarySat<wasm_sub_sat_u, "sub_saturate_u", 45>;
456
457//===----------------------------------------------------------------------===//
458// Bit shifts
459//===----------------------------------------------------------------------===//
460
461multiclass SIMDShift<ValueType vec_t, string vec, SDNode node, dag shift_vec,
462 string name, bits<32> simdop> {
463 defm _#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec, I32:$x),
464 (outs), (ins),
465 [(set (vec_t V128:$dst),
466 (node V128:$vec, (vec_t shift_vec)))],
467 vec#"."#name#"\t$dst, $vec, $x", vec#"."#name, simdop>;
468}
469
470multiclass SIMDShiftInt<SDNode node, string name, bits<32> baseInst, int skip> {
471 defm "" : SIMDShift<v16i8, "i8x16", node, (splat16 I32:$x), name, baseInst>;
472 defm "" : SIMDShift<v8i16, "i16x8", node, (splat8 I32:$x), name,
473 !add(baseInst, !if(skip, 2, 1))>;
474 defm "" : SIMDShift<v4i32, "i32x4", node, (splat4 I32:$x), name,
475 !add(baseInst, !if(skip, 4, 2))>;
476 defm "" : SIMDShift<v2i64, "i64x2", node, (splat2 (i64 (zext I32:$x))),
477 name, !add(baseInst, !if(skip, 6, 3))>;
478}
479
480// Left shift by scalar: shl
481defm SHL : SIMDShiftInt<shl, "shl", 48, 0>;
482
483// Right shift by scalar: shr_s / shr_u
484defm SHR_S : SIMDShiftInt<sra, "shr_s", 52, 1>;
485defm SHR_U : SIMDShiftInt<srl, "shr_u", 53, 1>;
486
487// Truncate i64 shift operands to i32s
488foreach shifts = [[shl, SHL_v2i64], [sra, SHR_S_v2i64], [srl, SHR_U_v2i64]] in
489def : Pat<(v2i64 (shifts[0] (v2i64 V128:$vec), (v2i64 (splat2 I64:$x)))),
490 (v2i64 (shifts[1] (v2i64 V128:$vec), (I32_WRAP_I64 I64:$x)))>;
491
492//===----------------------------------------------------------------------===//
493// Bitwise operations
494//===----------------------------------------------------------------------===//
495
496multiclass SIMDBitwise<SDNode node, string name, bits<32> simdop> {
497 defm "" : SIMDBinary<v16i8, "v128", node, name, simdop>;
498 defm "" : SIMDBinary<v8i16, "v128", node, name, simdop>;
499 defm "" : SIMDBinary<v4i32, "v128", node, name, simdop>;
500 defm "" : SIMDBinary<v2i64, "v128", node, name, simdop>;
501}
502
503// Bitwise logic: v128.and / v128.or / v128.xor
504let isCommutable = 1 in {
505defm AND : SIMDBitwise<and, "and", 60>;
506defm OR : SIMDBitwise<or, "or", 61>;
507defm XOR : SIMDBitwise<xor, "xor", 62>;
508} // isCommutable = 1
509
510// Bitwise logic: v128.not
511multiclass SIMDNot<ValueType vec_t, PatFrag splat_pat, ValueType lane_t> {
512 defm NOT_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec),
513 (outs), (ins),
514 [(set
515 (vec_t V128:$dst),
516 (vec_t (xor
517 (vec_t V128:$vec),
518 (vec_t (splat_pat (lane_t -1)))
519 ))
520 )],
521 "v128.not\t$dst, $vec", "v128.not", 63>;
522}
523
524defm "" : SIMDNot<v16i8, splat16, i32>;
525defm "" : SIMDNot<v8i16, splat8, i32>;
526defm "" : SIMDNot<v4i32, splat4, i32>;
527defm "" : SIMDNot<v2i64, splat2, i64>;
528
529// Bitwise select: v128.bitselect
530def wasm_bitselect_t : SDTypeProfile<1, 3,
531 [SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>]
532>;
533def wasm_bitselect : SDNode<"WebAssemblyISD::BITSELECT", wasm_bitselect_t>;
534
535multiclass Bitselect<ValueType vec_t> {
536 defm BITSELECT_#vec_t :
537 SIMD_I<(outs V128:$dst), (ins V128:$v1, V128:$v2, V128:$c), (outs), (ins),
538 [(set (vec_t V128:$dst),
539 (vec_t (wasm_bitselect
540 (vec_t V128:$c), (vec_t V128:$v1), (vec_t V128:$v2)
541 ))
542 )],
543 "v128.bitselect\t$dst, $v1, $v2, $c", "v128.bitselect", 64>;
544}
545
546foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
547defm "" : Bitselect<vec_t>;
548
549// Bitselect is equivalent to (c & v1) | (~c & v2)
550foreach vec_t = [v16i8, v8i16, v4i32, v2i64] in
551 def : Pat<(vec_t (or (and (vec_t V128:$c), (vec_t V128:$v1)),
552 (and (vnot V128:$c), (vec_t V128:$v2)))),
553 (!cast<Instruction>("BITSELECT_"#vec_t)
554 V128:$v1, V128:$v2, V128:$c)>;
555
556//===----------------------------------------------------------------------===//
557// Boolean horizontal reductions
558//===----------------------------------------------------------------------===//
559
560multiclass SIMDReduceVec<ValueType vec_t, string vec, string name, SDNode op,
561 bits<32> simdop> {
562 defm _#vec_t : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
563 [(set I32:$dst, (i32 (op (vec_t V128:$vec))))],
564 vec#"."#name#"\t$dst, $vec", vec#"."#name, simdop>;
565}
566
567multiclass SIMDReduce<string name, SDNode op, bits<32> baseInst> {
568 defm "" : SIMDReduceVec<v16i8, "i8x16", name, op, baseInst>;
569 defm "" : SIMDReduceVec<v8i16, "i16x8", name, op, !add(baseInst, 1)>;
570 defm "" : SIMDReduceVec<v4i32, "i32x4", name, op, !add(baseInst, 2)>;
571 defm "" : SIMDReduceVec<v2i64, "i64x2", name, op, !add(baseInst, 3)>;
572}
573
574def wasm_reduce_t : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVec<1>]>;
575
576// Any lane true: any_true
577def wasm_anytrue : SDNode<"WebAssemblyISD::ANYTRUE", wasm_reduce_t>;
578defm ANYTRUE : SIMDReduce<"any_true", wasm_anytrue, 65>;
579
580// All lanes true: all_true
581def wasm_alltrue : SDNode<"WebAssemblyISD::ALLTRUE", wasm_reduce_t>;
582defm ALLTRUE : SIMDReduce<"all_true", wasm_alltrue, 69>;
583
584//===----------------------------------------------------------------------===//
585// Comparisons
586//===----------------------------------------------------------------------===//
587
588multiclass SIMDCondition<ValueType vec_t, ValueType out_t, string vec,
589 string name, CondCode cond, bits<32> simdop> {
590 defm _#vec_t :
591 SIMD_I<(outs V128:$dst), (ins V128:$lhs, V128:$rhs), (outs), (ins),
592 [(set (out_t V128:$dst),
593 (setcc (vec_t V128:$lhs), (vec_t V128:$rhs), cond))],
594 vec#"."#name#"\t$dst, $lhs, $rhs", vec#"."#name, simdop>;
595}
596
597multiclass SIMDConditionInt<string name, CondCode cond, bits<32> baseInst,
598 int step = 1> {
599 defm "" : SIMDCondition<v16i8, v16i8, "i8x16", name, cond, baseInst>;
600 defm "" : SIMDCondition<v8i16, v8i16, "i16x8", name, cond,
601 !add(baseInst, step)>;
602 defm "" : SIMDCondition<v4i32, v4i32, "i32x4", name, cond,
603 !add(!add(baseInst, step), step)>;
604}
605
606multiclass SIMDConditionFP<string name, CondCode cond, bits<32> baseInst> {
607 defm "" : SIMDCondition<v4f32, v4i32, "f32x4", name, cond, baseInst>;
608 defm "" : SIMDCondition<v2f64, v2i64, "f64x2", name, cond,
609 !add(baseInst, 1)>;
610}
611
612// Equality: eq
613let isCommutable = 1 in {
614defm EQ : SIMDConditionInt<"eq", SETEQ, 73>;
615defm EQ : SIMDConditionFP<"eq", SETOEQ, 77>;
616} // isCommutable = 1
617
618// Non-equality: ne
619let isCommutable = 1 in {
620defm NE : SIMDConditionInt<"ne", SETNE, 79>;
621defm NE : SIMDConditionFP<"ne", SETUNE, 83>;
622} // isCommutable = 1
623
624// Less than: lt_s / lt_u / lt
625defm LT_S : SIMDConditionInt<"lt_s", SETLT, 85, 2>;
626defm LT_U : SIMDConditionInt<"lt_u", SETULT, 86, 2>;
627defm LT : SIMDConditionFP<"lt", SETOLT, 93>;
628
629// Less than or equal: le_s / le_u / le
630defm LE_S : SIMDConditionInt<"le_s", SETLE, 95, 2>;
631defm LE_U : SIMDConditionInt<"le_u", SETULE, 96, 2>;
632defm LE : SIMDConditionFP<"le", SETOLE, 103>;
633
634// Greater than: gt_s / gt_u / gt
635defm GT_S : SIMDConditionInt<"gt_s", SETGT, 105, 2>;
636defm GT_U : SIMDConditionInt<"gt_u", SETUGT, 106, 2>;
637defm GT : SIMDConditionFP<"gt", SETOGT, 113>;
638
639// Greater than or equal: ge_s / ge_u / ge
640defm GE_S : SIMDConditionInt<"ge_s", SETGE, 115, 2>;
641defm GE_U : SIMDConditionInt<"ge_u", SETUGE, 116, 2>;
642defm GE : SIMDConditionFP<"ge", SETOGE, 123>;
643
644// Lower float comparisons that don't care about NaN to standard WebAssembly
645// float comparisons. These instructions are generated in the target-independent
646// expansion of unordered comparisons and ordered ne.
647def : Pat<(v4i32 (seteq (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
648 (v4i32 (EQ_v4f32 (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>;
649def : Pat<(v4i32 (setne (v4f32 V128:$lhs), (v4f32 V128:$rhs))),
650 (v4i32 (NE_v4f32 (v4f32 V128:$lhs), (v4f32 V128:$rhs)))>;
651def : Pat<(v2i64 (seteq (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
652 (v2i64 (EQ_v2f64 (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>;
653def : Pat<(v2i64 (setne (v2f64 V128:$lhs), (v2f64 V128:$rhs))),
654 (v2i64 (NE_v2f64 (v2f64 V128:$lhs), (v2f64 V128:$rhs)))>;
655
656//===----------------------------------------------------------------------===//
657// Load and store
658//===----------------------------------------------------------------------===//
659
660// Load: v128.load
661multiclass SIMDLoad<ValueType vec_t> {
662 let mayLoad = 1 in
663 defm LOAD_#vec_t :
664 SIMD_I<(outs V128:$dst), (ins P2Align:$align, offset32_op:$off, I32:$addr),
665 (outs), (ins P2Align:$align, offset32_op:$off), [],
666 "v128.load\t$dst, ${off}(${addr})$align",
667 "v128.load\t$off$align", 1>;
668}
669
670foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
671defm "" : SIMDLoad<vec_t>;
672
673// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
674def : LoadPatNoOffset<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
675def : LoadPatImmOff<vec_t, load, regPlusImm, !cast<NI>("LOAD_"#vec_t)>;
676def : LoadPatImmOff<vec_t, load, or_is_add, !cast<NI>("LOAD_"#vec_t)>;
677def : LoadPatGlobalAddr<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
678def : LoadPatExternalSym<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
679def : LoadPatOffsetOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
680def : LoadPatGlobalAddrOffOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
681def : LoadPatExternSymOffOnly<vec_t, load, !cast<NI>("LOAD_"#vec_t)>;
682}
683
684// Store: v128.store
685multiclass SIMDStore<ValueType vec_t> {
686 let mayStore = 1 in
687 defm STORE_#vec_t :
688 SIMD_I<(outs), (ins P2Align:$align, offset32_op:$off, I32:$addr, V128:$vec),
689 (outs), (ins P2Align:$align, offset32_op:$off), [],
690 "v128.store\t${off}(${addr})$align, $vec",
691 "v128.store\t$off$align", 2>;
692}
693
694foreach vec_t = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in {
695defm "" : SIMDStore<vec_t>;
696
697// Def load and store patterns from WebAssemblyInstrMemory.td for vector types
698def : StorePatNoOffset<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
699def : StorePatImmOff<vec_t, store, regPlusImm, !cast<NI>("STORE_"#vec_t)>;
700def : StorePatImmOff<vec_t, store, or_is_add, !cast<NI>("STORE_"#vec_t)>;
701def : StorePatGlobalAddr<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
702def : StorePatExternalSym<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
703def : StorePatOffsetOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
704def : StorePatGlobalAddrOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
705def : StorePatExternSymOffOnly<vec_t, store, !cast<NI>("STORE_"#vec_t)>;
706}
707
708//===----------------------------------------------------------------------===//
709// Floating-point sign bit operations
710//===----------------------------------------------------------------------===//
711
712// Negation: neg
Thomas Lively108e98e2018-10-10 01:09:09 +0000[diff] [blame^]713defm "" : SIMDNeg<v4f32, "f32x4", fneg, 125>;
714defm "" : SIMDNeg<v2f64, "f64x2", fneg, 126>;
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]715
716// Absolute value: abs
717multiclass SIMDAbs<ValueType vec_t, string vec, bits<32> simdop> {
718 defm ABS_#vec_t : SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
719 [(set (vec_t V128:$dst), (vec_t (fabs V128:$vec)))],
720 vec#".abs\t$dst, $vec", vec#".abs", simdop>;
721}
722
723defm "" : SIMDAbs<v4f32, "f32x4", 127>;
724defm "" : SIMDAbs<v2f64, "f64x2", 128>;
725
726//===----------------------------------------------------------------------===//
727// Floating-point min and max
728//===----------------------------------------------------------------------===//
729
730// NaN-propagating minimum: min
731// TODO
732
733// NaN-propagating maximum: max
734// TODO
735
736//===----------------------------------------------------------------------===//
737// Floating-point arithmetic
738//===----------------------------------------------------------------------===//
739
740multiclass SIMDBinaryFP<SDNode node, string name, bits<32> baseInst> {
741 defm "" : SIMDBinary<v4f32, "f32x4", node, name, baseInst>;
742 defm "" : SIMDBinary<v2f64, "f64x2", node, name, !add(baseInst, 1)>;
743}
744
745// Addition: add
746let isCommutable = 1 in
747defm ADD : SIMDBinaryFP<fadd, "add", 133>;
748
749// Subtraction: sub
750defm SUB : SIMDBinaryFP<fsub, "sub", 135>;
751
752// Division: div
753defm DIV : SIMDBinaryFP<fdiv, "div", 137>;
754
755// Multiplication: mul
756let isCommutable = 1 in
757defm MUL : SIMDBinaryFP<fmul, "mul", 139>;
758
759// Square root: sqrt
760multiclass SIMDSqrt<ValueType vec_t, string vec, bits<32> simdop> {
761 defm SQRT_#vec_t :
762 SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
763 [(set (vec_t V128:$dst), (vec_t (fsqrt V128:$vec)))],
764 vec#".sqrt\t$dst, $vec", vec#".sqrt", simdop>;
765}
766
767defm "" : SIMDSqrt<v4f32, "f32x4", 141>;
768defm "" : SIMDSqrt<v2f64, "f64x2", 142>;
769
770//===----------------------------------------------------------------------===//
771// Conversions
772//===----------------------------------------------------------------------===//
773
774multiclass SIMDConvert<ValueType vec_t, ValueType arg_t, SDNode op,
775 string name, bits<32> simdop> {
776 defm op#_#vec_t#_#arg_t :
777 SIMD_I<(outs V128:$dst), (ins V128:$vec), (outs), (ins),
778 [(set (vec_t V128:$dst), (vec_t (op (arg_t V128:$vec))))],
779 name#"\t$dst, $vec", name, simdop>;
780}
781
Heejin Ahn5d900952018-10-10 01:04:02 +0000[diff] [blame]782// Integer to floating point: convert_s / convert_u
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]783defm "" : SIMDConvert<v4f32, v4i32, sint_to_fp, "f32x4.convert_s/i32x4", 143>;
784defm "" : SIMDConvert<v4f32, v4i32, uint_to_fp, "f32x4.convert_u/i32x4", 144>;
785defm "" : SIMDConvert<v2f64, v2i64, sint_to_fp, "f64x2.convert_s/i64x2", 145>;
786defm "" : SIMDConvert<v2f64, v2i64, uint_to_fp, "f64x2.convert_u/i64x2", 146>;
787
Heejin Ahn5d900952018-10-10 01:04:02 +0000[diff] [blame]788// Floating point to integer with saturation: trunc_sat_s / trunc_sat_u
Heejin Ahnd9a6de32018-10-09 22:23:39 +0000[diff] [blame]789defm "" : SIMDConvert<v4i32, v4f32, fp_to_sint, "i32x4.trunc_sat_s/f32x4", 147>;
790defm "" : SIMDConvert<v4i32, v4f32, fp_to_uint, "i32x4.trunc_sat_u/f32x4", 148>;
791defm "" : SIMDConvert<v2i64, v2f64, fp_to_sint, "i64x2.trunc_sat_s/f64x2", 149>;
792defm "" : SIMDConvert<v2i64, v2f64, fp_to_uint, "i64x2.trunc_sat_u/f64x2", 150>;
793
794// Bitcasts are nops
795// Matching bitcast t1 to t1 causes strange errors, so avoid repeating types
796foreach t1 = [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64] in
797foreach t2 = !foldl(
798 []<ValueType>, [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
799 acc, cur, !if(!eq(!cast<string>(t1), !cast<string>(cur)),
800 acc, !listconcat(acc, [cur])
801 )
802) in
803def : Pat<(t1 (bitconvert (t2 V128:$v))), (t1 V128:$v)>;