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gerrit-public.fairphone.software / toolchain / llvm-project / 11049f8f07330c30c689d54ed91d63909b360cf2 / . / llvm / test / CodeGen / PowerPC / select-i1-vs-i1.ll
blob: a8f1ef1dd284dc355afc41aca216c3370d471c50 [file] [log] [blame]
Ehsan Amiria538b0f2016-08-03 18:17:35 +0000[diff] [blame]1; RUN: llc -verify-machineinstrs < %s | FileCheck %s
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]2target datalayout = "E-m:e-i64:64-n32:64"
3target triple = "powerpc64-unknown-linux-gnu"
4
5; FIXME: We should check the operands to the cr* logical operation itself, but
6; unfortunately, FileCheck does not yet understand how to do arithmetic, so we
7; can't do so without introducing a register-allocation dependency.
8
9define signext i32 @testi32slt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
10entry:
11 %cmp1 = icmp eq i32 %c3, %c4
12 %cmp3tmp = icmp eq i32 %c1, %c2
13 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
14 %cond = select i1 %cmp3, i32 %a1, i32 %a2
15 ret i32 %cond
16
17; CHECK-LABEL: @testi32slt
18; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
19; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
20; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
21; CHECK: isel 3, 7, 8, [[REG1]]
22; CHECK: blr
23}
24
25define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
26entry:
27 %cmp1 = icmp eq i32 %c3, %c4
28 %cmp3tmp = icmp eq i32 %c1, %c2
29 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
30 %cond = select i1 %cmp3, i32 %a1, i32 %a2
31 ret i32 %cond
32
33; CHECK-LABEL: @testi32ult
34; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
35; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
36; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
37; CHECK: isel 3, 7, 8, [[REG1]]
38; CHECK: blr
39}
40
41define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
42entry:
43 %cmp1 = icmp eq i32 %c3, %c4
44 %cmp3tmp = icmp eq i32 %c1, %c2
45 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
46 %cond = select i1 %cmp3, i32 %a1, i32 %a2
47 ret i32 %cond
48
49; CHECK-LABEL: @testi32sle
50; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
51; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
52; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
53; CHECK: isel 3, 7, 8, [[REG1]]
54; CHECK: blr
55}
56
57define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
58entry:
59 %cmp1 = icmp eq i32 %c3, %c4
60 %cmp3tmp = icmp eq i32 %c1, %c2
61 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
62 %cond = select i1 %cmp3, i32 %a1, i32 %a2
63 ret i32 %cond
64
65; CHECK-LABEL: @testi32ule
66; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
67; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
68; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
69; CHECK: isel 3, 7, 8, [[REG1]]
70; CHECK: blr
71}
72
73define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
74entry:
75 %cmp1 = icmp eq i32 %c3, %c4
76 %cmp3tmp = icmp eq i32 %c1, %c2
77 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
78 %cond = select i1 %cmp3, i32 %a1, i32 %a2
79 ret i32 %cond
80
81; CHECK-LABEL: @testi32eq
82; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
83; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
84; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
85; CHECK: isel 3, 7, 8, [[REG1]]
86; CHECK: blr
87}
88
89define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
90entry:
91 %cmp1 = icmp eq i32 %c3, %c4
92 %cmp3tmp = icmp eq i32 %c1, %c2
93 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
94 %cond = select i1 %cmp3, i32 %a1, i32 %a2
95 ret i32 %cond
96
97; CHECK-LABEL: @testi32sge
98; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
99; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
100; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
101; CHECK: isel 3, 7, 8, [[REG1]]
102; CHECK: blr
103}
104
105define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
106entry:
107 %cmp1 = icmp eq i32 %c3, %c4
108 %cmp3tmp = icmp eq i32 %c1, %c2
109 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
110 %cond = select i1 %cmp3, i32 %a1, i32 %a2
111 ret i32 %cond
112
113; CHECK-LABEL: @testi32uge
114; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
115; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
116; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
117; CHECK: isel 3, 7, 8, [[REG1]]
118; CHECK: blr
119}
120
121define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
122entry:
123 %cmp1 = icmp eq i32 %c3, %c4
124 %cmp3tmp = icmp eq i32 %c1, %c2
125 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
126 %cond = select i1 %cmp3, i32 %a1, i32 %a2
127 ret i32 %cond
128
129; CHECK-LABEL: @testi32sgt
130; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
131; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
132; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
133; CHECK: isel 3, 7, 8, [[REG1]]
134; CHECK: blr
135}
136
137define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
138entry:
139 %cmp1 = icmp eq i32 %c3, %c4
140 %cmp3tmp = icmp eq i32 %c1, %c2
141 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
142 %cond = select i1 %cmp3, i32 %a1, i32 %a2
143 ret i32 %cond
144
145; CHECK-LABEL: @testi32ugt
146; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
147; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
148; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
149; CHECK: isel 3, 7, 8, [[REG1]]
150; CHECK: blr
151}
152
153define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
154entry:
155 %cmp1 = icmp eq i32 %c3, %c4
156 %cmp3tmp = icmp eq i32 %c1, %c2
157 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
158 %cond = select i1 %cmp3, i32 %a1, i32 %a2
159 ret i32 %cond
160
161; CHECK-LABEL: @testi32ne
162; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6
163; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
164; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
165; CHECK: isel 3, 7, 8, [[REG1]]
166; CHECK: blr
167}
168
169define i64 @testi64slt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
170entry:
171 %cmp1 = icmp eq i64 %c3, %c4
172 %cmp3tmp = icmp eq i64 %c1, %c2
173 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
174 %cond = select i1 %cmp3, i64 %a1, i64 %a2
175 ret i64 %cond
176
177; CHECK-LABEL: @testi64slt
178; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
179; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
180; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
181; CHECK: isel 3, 7, 8, [[REG1]]
182; CHECK: blr
183}
184
185define i64 @testi64ult(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
186entry:
187 %cmp1 = icmp eq i64 %c3, %c4
188 %cmp3tmp = icmp eq i64 %c1, %c2
189 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
190 %cond = select i1 %cmp3, i64 %a1, i64 %a2
191 ret i64 %cond
192
193; CHECK-LABEL: @testi64ult
194; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
195; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
196; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
197; CHECK: isel 3, 7, 8, [[REG1]]
198; CHECK: blr
199}
200
201define i64 @testi64sle(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
202entry:
203 %cmp1 = icmp eq i64 %c3, %c4
204 %cmp3tmp = icmp eq i64 %c1, %c2
205 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
206 %cond = select i1 %cmp3, i64 %a1, i64 %a2
207 ret i64 %cond
208
209; CHECK-LABEL: @testi64sle
210; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
211; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
212; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
213; CHECK: isel 3, 7, 8, [[REG1]]
214; CHECK: blr
215}
216
217define i64 @testi64ule(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
218entry:
219 %cmp1 = icmp eq i64 %c3, %c4
220 %cmp3tmp = icmp eq i64 %c1, %c2
221 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
222 %cond = select i1 %cmp3, i64 %a1, i64 %a2
223 ret i64 %cond
224
225; CHECK-LABEL: @testi64ule
226; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
227; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
228; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
229; CHECK: isel 3, 7, 8, [[REG1]]
230; CHECK: blr
231}
232
233define i64 @testi64eq(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
234entry:
235 %cmp1 = icmp eq i64 %c3, %c4
236 %cmp3tmp = icmp eq i64 %c1, %c2
237 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
238 %cond = select i1 %cmp3, i64 %a1, i64 %a2
239 ret i64 %cond
240
241; CHECK-LABEL: @testi64eq
242; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
243; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
244; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
245; CHECK: isel 3, 7, 8, [[REG1]]
246; CHECK: blr
247}
248
249define i64 @testi64sge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
250entry:
251 %cmp1 = icmp eq i64 %c3, %c4
252 %cmp3tmp = icmp eq i64 %c1, %c2
253 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
254 %cond = select i1 %cmp3, i64 %a1, i64 %a2
255 ret i64 %cond
256
257; CHECK-LABEL: @testi64sge
258; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
259; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
260; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
261; CHECK: isel 3, 7, 8, [[REG1]]
262; CHECK: blr
263}
264
265define i64 @testi64uge(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
266entry:
267 %cmp1 = icmp eq i64 %c3, %c4
268 %cmp3tmp = icmp eq i64 %c1, %c2
269 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
270 %cond = select i1 %cmp3, i64 %a1, i64 %a2
271 ret i64 %cond
272
273; CHECK-LABEL: @testi64uge
274; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
275; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
276; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
277; CHECK: isel 3, 7, 8, [[REG1]]
278; CHECK: blr
279}
280
281define i64 @testi64sgt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
282entry:
283 %cmp1 = icmp eq i64 %c3, %c4
284 %cmp3tmp = icmp eq i64 %c1, %c2
285 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
286 %cond = select i1 %cmp3, i64 %a1, i64 %a2
287 ret i64 %cond
288
289; CHECK-LABEL: @testi64sgt
290; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
291; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
292; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
293; CHECK: isel 3, 7, 8, [[REG1]]
294; CHECK: blr
295}
296
297define i64 @testi64ugt(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
298entry:
299 %cmp1 = icmp eq i64 %c3, %c4
300 %cmp3tmp = icmp eq i64 %c1, %c2
301 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
302 %cond = select i1 %cmp3, i64 %a1, i64 %a2
303 ret i64 %cond
304
305; CHECK-LABEL: @testi64ugt
306; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
307; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
308; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
309; CHECK: isel 3, 7, 8, [[REG1]]
310; CHECK: blr
311}
312
313define i64 @testi64ne(i64 %c1, i64 %c2, i64 %c3, i64 %c4, i64 %a1, i64 %a2) #0 {
314entry:
315 %cmp1 = icmp eq i64 %c3, %c4
316 %cmp3tmp = icmp eq i64 %c1, %c2
317 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
318 %cond = select i1 %cmp3, i64 %a1, i64 %a2
319 ret i64 %cond
320
321; CHECK-LABEL: @testi64ne
322; CHECK-DAG: cmpd {{([0-9]+, )?}}5, 6
323; CHECK-DAG: cmpd {{([0-9]+, )?}}3, 4
324; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
325; CHECK: isel 3, 7, 8, [[REG1]]
326; CHECK: blr
327}
328
329define float @testfloatslt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
330entry:
331 %cmp1 = fcmp oeq float %c3, %c4
332 %cmp3tmp = fcmp oeq float %c1, %c2
333 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
334 %cond = select i1 %cmp3, float %a1, float %a2
335 ret float %cond
336
337; CHECK-LABEL: @testfloatslt
338; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
339; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
340; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
341; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
342; CHECK: fmr 5, 6
343; CHECK: .LBB[[BB]]:
344; CHECK: fmr 1, 5
345; CHECK: blr
346}
347
348define float @testfloatult(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
349entry:
350 %cmp1 = fcmp oeq float %c3, %c4
351 %cmp3tmp = fcmp oeq float %c1, %c2
352 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
353 %cond = select i1 %cmp3, float %a1, float %a2
354 ret float %cond
355
356; CHECK-LABEL: @testfloatult
357; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
358; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
359; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
360; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
361; CHECK: fmr 5, 6
362; CHECK: .LBB[[BB]]:
363; CHECK: fmr 1, 5
364; CHECK: blr
365}
366
367define float @testfloatsle(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
368entry:
369 %cmp1 = fcmp oeq float %c3, %c4
370 %cmp3tmp = fcmp oeq float %c1, %c2
371 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
372 %cond = select i1 %cmp3, float %a1, float %a2
373 ret float %cond
374
375; CHECK-LABEL: @testfloatsle
376; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
377; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
378; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
379; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
380; CHECK: fmr 5, 6
381; CHECK: .LBB[[BB]]:
382; CHECK: fmr 1, 5
383; CHECK: blr
384}
385
386define float @testfloatule(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
387entry:
388 %cmp1 = fcmp oeq float %c3, %c4
389 %cmp3tmp = fcmp oeq float %c1, %c2
390 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
391 %cond = select i1 %cmp3, float %a1, float %a2
392 ret float %cond
393
394; CHECK-LABEL: @testfloatule
395; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
396; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
397; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
398; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
399; CHECK: fmr 5, 6
400; CHECK: .LBB[[BB]]:
401; CHECK: fmr 1, 5
402; CHECK: blr
403}
404
405define float @testfloateq(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
406entry:
407 %cmp1 = fcmp oeq float %c3, %c4
408 %cmp3tmp = fcmp oeq float %c1, %c2
409 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
410 %cond = select i1 %cmp3, float %a1, float %a2
411 ret float %cond
412
413; CHECK-LABEL: @testfloateq
414; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
415; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
416; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
417; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
418; CHECK: fmr 5, 6
419; CHECK: .LBB[[BB]]:
420; CHECK: fmr 1, 5
421; CHECK: blr
422}
423
424define float @testfloatsge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
425entry:
426 %cmp1 = fcmp oeq float %c3, %c4
427 %cmp3tmp = fcmp oeq float %c1, %c2
428 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
429 %cond = select i1 %cmp3, float %a1, float %a2
430 ret float %cond
431
432; CHECK-LABEL: @testfloatsge
433; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
434; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
435; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
436; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
437; CHECK: fmr 5, 6
438; CHECK: .LBB[[BB]]:
439; CHECK: fmr 1, 5
440; CHECK: blr
441}
442
443define float @testfloatuge(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
444entry:
445 %cmp1 = fcmp oeq float %c3, %c4
446 %cmp3tmp = fcmp oeq float %c1, %c2
447 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
448 %cond = select i1 %cmp3, float %a1, float %a2
449 ret float %cond
450
451; CHECK-LABEL: @testfloatuge
452; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
453; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
454; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
455; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
456; CHECK: fmr 5, 6
457; CHECK: .LBB[[BB]]:
458; CHECK: fmr 1, 5
459; CHECK: blr
460}
461
462define float @testfloatsgt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
463entry:
464 %cmp1 = fcmp oeq float %c3, %c4
465 %cmp3tmp = fcmp oeq float %c1, %c2
466 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
467 %cond = select i1 %cmp3, float %a1, float %a2
468 ret float %cond
469
470; CHECK-LABEL: @testfloatsgt
471; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
472; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
473; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
474; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
475; CHECK: fmr 5, 6
476; CHECK: .LBB[[BB]]:
477; CHECK: fmr 1, 5
478; CHECK: blr
479}
480
481define float @testfloatugt(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
482entry:
483 %cmp1 = fcmp oeq float %c3, %c4
484 %cmp3tmp = fcmp oeq float %c1, %c2
485 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
486 %cond = select i1 %cmp3, float %a1, float %a2
487 ret float %cond
488
489; CHECK-LABEL: @testfloatugt
490; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
491; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
492; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
493; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
494; CHECK: fmr 5, 6
495; CHECK: .LBB[[BB]]:
496; CHECK: fmr 1, 5
497; CHECK: blr
498}
499
500define float @testfloatne(float %c1, float %c2, float %c3, float %c4, float %a1, float %a2) #0 {
501entry:
502 %cmp1 = fcmp oeq float %c3, %c4
503 %cmp3tmp = fcmp oeq float %c1, %c2
504 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
505 %cond = select i1 %cmp3, float %a1, float %a2
506 ret float %cond
507
508; CHECK-LABEL: @testfloatne
509; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
510; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
511; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
512; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
513; CHECK: fmr 5, 6
514; CHECK: .LBB[[BB]]:
515; CHECK: fmr 1, 5
516; CHECK: blr
517}
518
519define double @testdoubleslt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
520entry:
521 %cmp1 = fcmp oeq double %c3, %c4
522 %cmp3tmp = fcmp oeq double %c1, %c2
523 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
524 %cond = select i1 %cmp3, double %a1, double %a2
525 ret double %cond
526
527; CHECK-LABEL: @testdoubleslt
528; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
529; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
530; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
531; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
532; CHECK: fmr 5, 6
533; CHECK: .LBB[[BB]]:
534; CHECK: fmr 1, 5
535; CHECK: blr
536}
537
538define double @testdoubleult(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
539entry:
540 %cmp1 = fcmp oeq double %c3, %c4
541 %cmp3tmp = fcmp oeq double %c1, %c2
542 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
543 %cond = select i1 %cmp3, double %a1, double %a2
544 ret double %cond
545
546; CHECK-LABEL: @testdoubleult
547; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
548; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
549; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
550; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
551; CHECK: fmr 5, 6
552; CHECK: .LBB[[BB]]:
553; CHECK: fmr 1, 5
554; CHECK: blr
555}
556
557define double @testdoublesle(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
558entry:
559 %cmp1 = fcmp oeq double %c3, %c4
560 %cmp3tmp = fcmp oeq double %c1, %c2
561 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
562 %cond = select i1 %cmp3, double %a1, double %a2
563 ret double %cond
564
565; CHECK-LABEL: @testdoublesle
566; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
567; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
568; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
569; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
570; CHECK: fmr 5, 6
571; CHECK: .LBB[[BB]]:
572; CHECK: fmr 1, 5
573; CHECK: blr
574}
575
576define double @testdoubleule(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
577entry:
578 %cmp1 = fcmp oeq double %c3, %c4
579 %cmp3tmp = fcmp oeq double %c1, %c2
580 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
581 %cond = select i1 %cmp3, double %a1, double %a2
582 ret double %cond
583
584; CHECK-LABEL: @testdoubleule
585; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
586; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
587; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
588; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
589; CHECK: fmr 5, 6
590; CHECK: .LBB[[BB]]:
591; CHECK: fmr 1, 5
592; CHECK: blr
593}
594
595define double @testdoubleeq(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
596entry:
597 %cmp1 = fcmp oeq double %c3, %c4
598 %cmp3tmp = fcmp oeq double %c1, %c2
599 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
600 %cond = select i1 %cmp3, double %a1, double %a2
601 ret double %cond
602
603; CHECK-LABEL: @testdoubleeq
604; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
605; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
606; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
607; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
608; CHECK: fmr 5, 6
609; CHECK: .LBB[[BB]]:
610; CHECK: fmr 1, 5
611; CHECK: blr
612}
613
614define double @testdoublesge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
615entry:
616 %cmp1 = fcmp oeq double %c3, %c4
617 %cmp3tmp = fcmp oeq double %c1, %c2
618 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
619 %cond = select i1 %cmp3, double %a1, double %a2
620 ret double %cond
621
622; CHECK-LABEL: @testdoublesge
623; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
624; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
625; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
626; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
627; CHECK: fmr 5, 6
628; CHECK: .LBB[[BB]]:
629; CHECK: fmr 1, 5
630; CHECK: blr
631}
632
633define double @testdoubleuge(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
634entry:
635 %cmp1 = fcmp oeq double %c3, %c4
636 %cmp3tmp = fcmp oeq double %c1, %c2
637 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
638 %cond = select i1 %cmp3, double %a1, double %a2
639 ret double %cond
640
641; CHECK-LABEL: @testdoubleuge
642; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
643; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
644; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
645; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
646; CHECK: fmr 5, 6
647; CHECK: .LBB[[BB]]:
648; CHECK: fmr 1, 5
649; CHECK: blr
650}
651
652define double @testdoublesgt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
653entry:
654 %cmp1 = fcmp oeq double %c3, %c4
655 %cmp3tmp = fcmp oeq double %c1, %c2
656 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
657 %cond = select i1 %cmp3, double %a1, double %a2
658 ret double %cond
659
660; CHECK-LABEL: @testdoublesgt
661; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
662; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
663; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
664; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
665; CHECK: fmr 5, 6
666; CHECK: .LBB[[BB]]:
667; CHECK: fmr 1, 5
668; CHECK: blr
669}
670
671define double @testdoubleugt(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
672entry:
673 %cmp1 = fcmp oeq double %c3, %c4
674 %cmp3tmp = fcmp oeq double %c1, %c2
675 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
676 %cond = select i1 %cmp3, double %a1, double %a2
677 ret double %cond
678
679; CHECK-LABEL: @testdoubleugt
680; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
681; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
682; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
683; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
684; CHECK: fmr 5, 6
685; CHECK: .LBB[[BB]]:
686; CHECK: fmr 1, 5
687; CHECK: blr
688}
689
690define double @testdoublene(double %c1, double %c2, double %c3, double %c4, double %a1, double %a2) #0 {
691entry:
692 %cmp1 = fcmp oeq double %c3, %c4
693 %cmp3tmp = fcmp oeq double %c1, %c2
694 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
695 %cond = select i1 %cmp3, double %a1, double %a2
696 ret double %cond
697
698; CHECK-LABEL: @testdoublene
699; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
700; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
701; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
702; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
703; CHECK: fmr 5, 6
704; CHECK: .LBB[[BB]]:
705; CHECK: fmr 1, 5
706; CHECK: blr
707}
708
709define <4 x float> @testv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
710entry:
711 %cmp1 = fcmp oeq float %c3, %c4
712 %cmp3tmp = fcmp oeq float %c1, %c2
713 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
714 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
715 ret <4 x float> %cond
716
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]717; CHECK-LABEL: @testv4floatslt
718; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
719; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
Nemanja Ivanovic11049f82016-10-04 06:59:23 +0000[diff] [blame^]720; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
721; CHECK: bclr 12, [[REG1]], 0
722; CHECK: vor 2, 3, 3
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]723; CHECK: blr
724}
725
726define <4 x float> @testv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
727entry:
728 %cmp1 = fcmp oeq float %c3, %c4
729 %cmp3tmp = fcmp oeq float %c1, %c2
730 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
731 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
732 ret <4 x float> %cond
733
734; CHECK-LABEL: @testv4floatult
735; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
736; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
Nemanja Ivanovic11049f82016-10-04 06:59:23 +0000[diff] [blame^]737; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
738; CHECK: bclr 12, [[REG1]], 0
739; CHECK: vor 2, 3, 3
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]740; CHECK: blr
741}
742
743define <4 x float> @testv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
744entry:
745 %cmp1 = fcmp oeq float %c3, %c4
746 %cmp3tmp = fcmp oeq float %c1, %c2
747 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
748 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
749 ret <4 x float> %cond
750
751; CHECK-LABEL: @testv4floatsle
752; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
753; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
Nemanja Ivanovic11049f82016-10-04 06:59:23 +0000[diff] [blame^]754; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
755; CHECK: bclr 12, [[REG1]], 0
756; CHECK: vor 2, 3, 3
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]757; CHECK: blr
758}
759
760define <4 x float> @testv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
761entry:
762 %cmp1 = fcmp oeq float %c3, %c4
763 %cmp3tmp = fcmp oeq float %c1, %c2
764 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
765 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
766 ret <4 x float> %cond
767
768; CHECK-LABEL: @testv4floatule
769; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
770; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
Nemanja Ivanovic11049f82016-10-04 06:59:23 +0000[diff] [blame^]771; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
772; CHECK: bclr 12, [[REG1]], 0
773; CHECK: vor 2, 3, 3
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]774; CHECK: blr
775}
776
777define <4 x float> @testv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
778entry:
779 %cmp1 = fcmp oeq float %c3, %c4
780 %cmp3tmp = fcmp oeq float %c1, %c2
781 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
782 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
783 ret <4 x float> %cond
784
785; CHECK-LABEL: @testv4floateq
786; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
787; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
Nemanja Ivanovic11049f82016-10-04 06:59:23 +0000[diff] [blame^]788; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
789; CHECK: bc 12, [[REG1]], .LBB[[BB1:[0-9_]+]]
790; CHECK: vor 3, 2, 2
791; CHECK: .LBB[[BB1]]
792; CHECK: vor 2, 3, 3
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]793; CHECK: blr
794}
795
796define <4 x float> @testv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
797entry:
798 %cmp1 = fcmp oeq float %c3, %c4
799 %cmp3tmp = fcmp oeq float %c1, %c2
800 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
801 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
802 ret <4 x float> %cond
803
804; CHECK-LABEL: @testv4floatsge
805; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
806; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
Nemanja Ivanovic11049f82016-10-04 06:59:23 +0000[diff] [blame^]807; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
808; CHECK: bclr 12, [[REG1]], 0
809; CHECK: vor 2, 3, 3
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]810; CHECK: blr
811}
812
813define <4 x float> @testv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
814entry:
815 %cmp1 = fcmp oeq float %c3, %c4
816 %cmp3tmp = fcmp oeq float %c1, %c2
817 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
818 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
819 ret <4 x float> %cond
820
821; CHECK-LABEL: @testv4floatuge
822; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
823; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
Nemanja Ivanovic11049f82016-10-04 06:59:23 +0000[diff] [blame^]824; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
825; CHECK: bclr 12, [[REG1]], 0
826; CHECK: vor 2, 3, 3
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]827; CHECK: blr
828}
829
830define <4 x float> @testv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
831entry:
832 %cmp1 = fcmp oeq float %c3, %c4
833 %cmp3tmp = fcmp oeq float %c1, %c2
834 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
835 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
836 ret <4 x float> %cond
837
838; CHECK-LABEL: @testv4floatsgt
839; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
840; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
Nemanja Ivanovic11049f82016-10-04 06:59:23 +0000[diff] [blame^]841; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
842; CHECK: bclr 12, [[REG1]], 0
843; CHECK: vor 2, 3, 3
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]844; CHECK: blr
845}
846
847define <4 x float> @testv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
848entry:
849 %cmp1 = fcmp oeq float %c3, %c4
850 %cmp3tmp = fcmp oeq float %c1, %c2
851 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
852 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
853 ret <4 x float> %cond
854
855; CHECK-LABEL: @testv4floatugt
856; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
857; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
Nemanja Ivanovic11049f82016-10-04 06:59:23 +0000[diff] [blame^]858; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
859; CHECK: bclr 12, [[REG1]], 0
860; CHECK: vor 2, 3, 3
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]861; CHECK: blr
862}
863
864define <4 x float> @testv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #0 {
865entry:
866 %cmp1 = fcmp oeq float %c3, %c4
867 %cmp3tmp = fcmp oeq float %c1, %c2
868 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
869 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
870 ret <4 x float> %cond
871
872; CHECK-LABEL: @testv4floatne
873; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
874; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
Nemanja Ivanovic11049f82016-10-04 06:59:23 +0000[diff] [blame^]875; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
876; CHECK: bclr 12, [[REG1]], 0
877; CHECK: vor 2, 3, 3
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]878; CHECK: blr
879}
880
881define ppc_fp128 @testppc_fp128eq(ppc_fp128 %c1, ppc_fp128 %c2, ppc_fp128 %c3, ppc_fp128 %c4, ppc_fp128 %a1, ppc_fp128 %a2) #0 {
882entry:
883 %cmp1 = fcmp oeq ppc_fp128 %c3, %c4
884 %cmp3tmp = fcmp oeq ppc_fp128 %c1, %c2
885 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
886 %cond = select i1 %cmp3, ppc_fp128 %a1, ppc_fp128 %a2
887 ret ppc_fp128 %cond
888
889; FIXME: Because of the way that the late SELECT_* pseudo-instruction expansion
890; works, we end up with two blocks with the same predicate. These could be
891; combined.
892
893; CHECK-LABEL: @testppc_fp128eq
894; CHECK-DAG: fcmpu {{[0-9]+}}, 6, 8
895; CHECK-DAG: fcmpu {{[0-9]+}}, 5, 7
896; CHECK-DAG: fcmpu {{[0-9]+}}, 2, 4
897; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 3
898; CHECK: crand [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
899; CHECK: crand [[REG2:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
Ayman Musa0c2da882016-09-13 09:12:45 +0000[diff] [blame]900; CHECK: crxor [[REG3:[0-9]+]], [[REG2]], [[REG1]]
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]901; CHECK: bc 12, [[REG3]], .LBB[[BB1:[0-9_]+]]
Ayman Musa0c2da882016-09-13 09:12:45 +0000[diff] [blame]902; CHECK: fmr 11, 9
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]903; CHECK: .LBB[[BB1]]:
904; CHECK: bc 12, [[REG3]], .LBB[[BB2:[0-9_]+]]
Ayman Musa0c2da882016-09-13 09:12:45 +0000[diff] [blame]905; CHECK: fmr 12, 10
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]906; CHECK: .LBB[[BB2]]:
Ayman Musa0c2da882016-09-13 09:12:45 +0000[diff] [blame]907; CHECK-DAG: fmr 1, 11
908; CHECK-DAG: fmr 2, 12
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]909; CHECK: blr
910}
911
912define <2 x double> @testv2doubleslt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
913entry:
914 %cmp1 = fcmp oeq float %c3, %c4
915 %cmp3tmp = fcmp oeq float %c1, %c2
916 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
917 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
918 ret <2 x double> %cond
919
920; CHECK-LABEL: @testv2doubleslt
921; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
922; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
923; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
924; CHECK: bclr 12, [[REG1]], 0
925; CHECK: vor 2, 3, 3
926; CHECK: blr
927}
928
929define <2 x double> @testv2doubleult(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
930entry:
931 %cmp1 = fcmp oeq float %c3, %c4
932 %cmp3tmp = fcmp oeq float %c1, %c2
933 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
934 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
935 ret <2 x double> %cond
936
937; CHECK-LABEL: @testv2doubleult
938; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
939; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
940; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
941; CHECK: bclr 12, [[REG1]], 0
942; CHECK: vor 2, 3, 3
943; CHECK: blr
944}
945
946define <2 x double> @testv2doublesle(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
947entry:
948 %cmp1 = fcmp oeq float %c3, %c4
949 %cmp3tmp = fcmp oeq float %c1, %c2
950 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
951 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
952 ret <2 x double> %cond
953
954; CHECK-LABEL: @testv2doublesle
955; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
956; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
957; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
958; CHECK: bclr 12, [[REG1]], 0
959; CHECK: vor 2, 3, 3
960; CHECK: blr
961}
962
963define <2 x double> @testv2doubleule(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
964entry:
965 %cmp1 = fcmp oeq float %c3, %c4
966 %cmp3tmp = fcmp oeq float %c1, %c2
967 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
968 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
969 ret <2 x double> %cond
970
971; CHECK-LABEL: @testv2doubleule
972; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
973; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
974; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
975; CHECK: bclr 12, [[REG1]], 0
976; CHECK: vor 2, 3, 3
977; CHECK: blr
978}
979
980define <2 x double> @testv2doubleeq(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
981entry:
982 %cmp1 = fcmp oeq float %c3, %c4
983 %cmp3tmp = fcmp oeq float %c1, %c2
984 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
985 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
986 ret <2 x double> %cond
987
988; CHECK-LABEL: @testv2doubleeq
989; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
990; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
Ayman Musa0c2da882016-09-13 09:12:45 +0000[diff] [blame]991; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
992; CHECK: bc 12, [[REG1]], .LBB[[BB55:[0-9_]+]]
993; CHECK: vor 3, 2, 2
994; CHECK: .LBB[[BB55]]
Nemanja Ivanovic11049f82016-10-04 06:59:23 +0000[diff] [blame^]995; CHECK: vor 2, 3, 3
Hal Finkela2cdbce2015-08-30 22:12:50 +0000[diff] [blame]996; CHECK: blr
997}
998
999define <2 x double> @testv2doublesge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1000entry:
1001 %cmp1 = fcmp oeq float %c3, %c4
1002 %cmp3tmp = fcmp oeq float %c1, %c2
1003 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
1004 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1005 ret <2 x double> %cond
1006
1007; CHECK-LABEL: @testv2doublesge
1008; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1009; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1010; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1011; CHECK: bclr 12, [[REG1]], 0
1012; CHECK: vor 2, 3, 3
1013; CHECK: blr
1014}
1015
1016define <2 x double> @testv2doubleuge(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1017entry:
1018 %cmp1 = fcmp oeq float %c3, %c4
1019 %cmp3tmp = fcmp oeq float %c1, %c2
1020 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
1021 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1022 ret <2 x double> %cond
1023
1024; CHECK-LABEL: @testv2doubleuge
1025; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1026; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1027; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1028; CHECK: bclr 12, [[REG1]], 0
1029; CHECK: vor 2, 3, 3
1030; CHECK: blr
1031}
1032
1033define <2 x double> @testv2doublesgt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1034entry:
1035 %cmp1 = fcmp oeq float %c3, %c4
1036 %cmp3tmp = fcmp oeq float %c1, %c2
1037 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
1038 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1039 ret <2 x double> %cond
1040
1041; CHECK-LABEL: @testv2doublesgt
1042; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1043; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1044; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1045; CHECK: bclr 12, [[REG1]], 0
1046; CHECK: vor 2, 3, 3
1047; CHECK: blr
1048}
1049
1050define <2 x double> @testv2doubleugt(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1051entry:
1052 %cmp1 = fcmp oeq float %c3, %c4
1053 %cmp3tmp = fcmp oeq float %c1, %c2
1054 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
1055 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1056 ret <2 x double> %cond
1057
1058; CHECK-LABEL: @testv2doubleugt
1059; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1060; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1061; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1062; CHECK: bclr 12, [[REG1]], 0
1063; CHECK: vor 2, 3, 3
1064; CHECK: blr
1065}
1066
1067define <2 x double> @testv2doublene(float %c1, float %c2, float %c3, float %c4, <2 x double> %a1, <2 x double> %a2) #0 {
1068entry:
1069 %cmp1 = fcmp oeq float %c3, %c4
1070 %cmp3tmp = fcmp oeq float %c1, %c2
1071 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
1072 %cond = select i1 %cmp3, <2 x double> %a1, <2 x double> %a2
1073 ret <2 x double> %cond
1074
1075; CHECK-LABEL: @testv2doublene
1076; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1077; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1078; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1079; CHECK: bclr 12, [[REG1]], 0
1080; CHECK: vor 2, 3, 3
1081; CHECK: blr
1082}
1083
1084define <4 x double> @testqv4doubleslt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1085entry:
1086 %cmp1 = fcmp oeq float %c3, %c4
1087 %cmp3tmp = fcmp oeq float %c1, %c2
1088 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
1089 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1090 ret <4 x double> %cond
1091
1092; CHECK-LABEL: @testqv4doubleslt
1093; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1094; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1095; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1096; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1097; CHECK: qvfmr 5, 6
1098; CHECK: .LBB[[BB]]:
1099; CHECK: qvfmr 1, 5
1100; CHECK: blr
1101}
1102
1103define <4 x double> @testqv4doubleult(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1104entry:
1105 %cmp1 = fcmp oeq float %c3, %c4
1106 %cmp3tmp = fcmp oeq float %c1, %c2
1107 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
1108 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1109 ret <4 x double> %cond
1110
1111; CHECK-LABEL: @testqv4doubleult
1112; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1113; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1114; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1115; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1116; CHECK: qvfmr 5, 6
1117; CHECK: .LBB[[BB]]:
1118; CHECK: qvfmr 1, 5
1119; CHECK: blr
1120}
1121
1122define <4 x double> @testqv4doublesle(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1123entry:
1124 %cmp1 = fcmp oeq float %c3, %c4
1125 %cmp3tmp = fcmp oeq float %c1, %c2
1126 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
1127 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1128 ret <4 x double> %cond
1129
1130; CHECK-LABEL: @testqv4doublesle
1131; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1132; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1133; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1134; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1135; CHECK: qvfmr 5, 6
1136; CHECK: .LBB[[BB]]:
1137; CHECK: qvfmr 1, 5
1138; CHECK: blr
1139}
1140
1141define <4 x double> @testqv4doubleule(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1142entry:
1143 %cmp1 = fcmp oeq float %c3, %c4
1144 %cmp3tmp = fcmp oeq float %c1, %c2
1145 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
1146 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1147 ret <4 x double> %cond
1148
1149; CHECK-LABEL: @testqv4doubleule
1150; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1151; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1152; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1153; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1154; CHECK: qvfmr 5, 6
1155; CHECK: .LBB[[BB]]:
1156; CHECK: qvfmr 1, 5
1157; CHECK: blr
1158}
1159
1160define <4 x double> @testqv4doubleeq(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1161entry:
1162 %cmp1 = fcmp oeq float %c3, %c4
1163 %cmp3tmp = fcmp oeq float %c1, %c2
1164 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
1165 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1166 ret <4 x double> %cond
1167
1168; CHECK-LABEL: @testqv4doubleeq
1169; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1170; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1171; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1172; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1173; CHECK: qvfmr 5, 6
1174; CHECK: .LBB[[BB]]:
1175; CHECK: qvfmr 1, 5
1176; CHECK: blr
1177}
1178
1179define <4 x double> @testqv4doublesge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1180entry:
1181 %cmp1 = fcmp oeq float %c3, %c4
1182 %cmp3tmp = fcmp oeq float %c1, %c2
1183 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
1184 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1185 ret <4 x double> %cond
1186
1187; CHECK-LABEL: @testqv4doublesge
1188; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1189; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1190; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1191; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1192; CHECK: qvfmr 5, 6
1193; CHECK: .LBB[[BB]]:
1194; CHECK: qvfmr 1, 5
1195; CHECK: blr
1196}
1197
1198define <4 x double> @testqv4doubleuge(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1199entry:
1200 %cmp1 = fcmp oeq float %c3, %c4
1201 %cmp3tmp = fcmp oeq float %c1, %c2
1202 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
1203 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1204 ret <4 x double> %cond
1205
1206; CHECK-LABEL: @testqv4doubleuge
1207; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1208; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1209; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1210; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1211; CHECK: qvfmr 5, 6
1212; CHECK: .LBB[[BB]]:
1213; CHECK: qvfmr 1, 5
1214; CHECK: blr
1215}
1216
1217define <4 x double> @testqv4doublesgt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1218entry:
1219 %cmp1 = fcmp oeq float %c3, %c4
1220 %cmp3tmp = fcmp oeq float %c1, %c2
1221 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
1222 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1223 ret <4 x double> %cond
1224
1225; CHECK-LABEL: @testqv4doublesgt
1226; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1227; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1228; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1229; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1230; CHECK: qvfmr 5, 6
1231; CHECK: .LBB[[BB]]:
1232; CHECK: qvfmr 1, 5
1233; CHECK: blr
1234}
1235
1236define <4 x double> @testqv4doubleugt(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1237entry:
1238 %cmp1 = fcmp oeq float %c3, %c4
1239 %cmp3tmp = fcmp oeq float %c1, %c2
1240 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
1241 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1242 ret <4 x double> %cond
1243
1244; CHECK-LABEL: @testqv4doubleugt
1245; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1246; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1247; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1248; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1249; CHECK: qvfmr 5, 6
1250; CHECK: .LBB[[BB]]:
1251; CHECK: qvfmr 1, 5
1252; CHECK: blr
1253}
1254
1255define <4 x double> @testqv4doublene(float %c1, float %c2, float %c3, float %c4, <4 x double> %a1, <4 x double> %a2) #1 {
1256entry:
1257 %cmp1 = fcmp oeq float %c3, %c4
1258 %cmp3tmp = fcmp oeq float %c1, %c2
1259 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
1260 %cond = select i1 %cmp3, <4 x double> %a1, <4 x double> %a2
1261 ret <4 x double> %cond
1262
1263; CHECK-LABEL: @testqv4doublene
1264; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1265; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1266; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1267; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1268; CHECK: qvfmr 5, 6
1269; CHECK: .LBB[[BB]]:
1270; CHECK: qvfmr 1, 5
1271; CHECK: blr
1272}
1273
1274define <4 x float> @testqv4floatslt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1275entry:
1276 %cmp1 = fcmp oeq float %c3, %c4
1277 %cmp3tmp = fcmp oeq float %c1, %c2
1278 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
1279 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1280 ret <4 x float> %cond
1281
1282; CHECK-LABEL: @testqv4floatslt
1283; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1284; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1285; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1286; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1287; CHECK: qvfmr 5, 6
1288; CHECK: .LBB[[BB]]:
1289; CHECK: qvfmr 1, 5
1290; CHECK: blr
1291}
1292
1293define <4 x float> @testqv4floatult(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1294entry:
1295 %cmp1 = fcmp oeq float %c3, %c4
1296 %cmp3tmp = fcmp oeq float %c1, %c2
1297 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
1298 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1299 ret <4 x float> %cond
1300
1301; CHECK-LABEL: @testqv4floatult
1302; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1303; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1304; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1305; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1306; CHECK: qvfmr 5, 6
1307; CHECK: .LBB[[BB]]:
1308; CHECK: qvfmr 1, 5
1309; CHECK: blr
1310}
1311
1312define <4 x float> @testqv4floatsle(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1313entry:
1314 %cmp1 = fcmp oeq float %c3, %c4
1315 %cmp3tmp = fcmp oeq float %c1, %c2
1316 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
1317 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1318 ret <4 x float> %cond
1319
1320; CHECK-LABEL: @testqv4floatsle
1321; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1322; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1323; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1324; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1325; CHECK: qvfmr 5, 6
1326; CHECK: .LBB[[BB]]:
1327; CHECK: qvfmr 1, 5
1328; CHECK: blr
1329}
1330
1331define <4 x float> @testqv4floatule(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1332entry:
1333 %cmp1 = fcmp oeq float %c3, %c4
1334 %cmp3tmp = fcmp oeq float %c1, %c2
1335 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
1336 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1337 ret <4 x float> %cond
1338
1339; CHECK-LABEL: @testqv4floatule
1340; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1341; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1342; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1343; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1344; CHECK: qvfmr 5, 6
1345; CHECK: .LBB[[BB]]:
1346; CHECK: qvfmr 1, 5
1347; CHECK: blr
1348}
1349
1350define <4 x float> @testqv4floateq(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1351entry:
1352 %cmp1 = fcmp oeq float %c3, %c4
1353 %cmp3tmp = fcmp oeq float %c1, %c2
1354 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
1355 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1356 ret <4 x float> %cond
1357
1358; CHECK-LABEL: @testqv4floateq
1359; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1360; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1361; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1362; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1363; CHECK: qvfmr 5, 6
1364; CHECK: .LBB[[BB]]:
1365; CHECK: qvfmr 1, 5
1366; CHECK: blr
1367}
1368
1369define <4 x float> @testqv4floatsge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1370entry:
1371 %cmp1 = fcmp oeq float %c3, %c4
1372 %cmp3tmp = fcmp oeq float %c1, %c2
1373 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
1374 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1375 ret <4 x float> %cond
1376
1377; CHECK-LABEL: @testqv4floatsge
1378; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1379; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1380; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1381; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1382; CHECK: qvfmr 5, 6
1383; CHECK: .LBB[[BB]]:
1384; CHECK: qvfmr 1, 5
1385; CHECK: blr
1386}
1387
1388define <4 x float> @testqv4floatuge(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1389entry:
1390 %cmp1 = fcmp oeq float %c3, %c4
1391 %cmp3tmp = fcmp oeq float %c1, %c2
1392 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
1393 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1394 ret <4 x float> %cond
1395
1396; CHECK-LABEL: @testqv4floatuge
1397; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1398; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1399; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1400; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1401; CHECK: qvfmr 5, 6
1402; CHECK: .LBB[[BB]]:
1403; CHECK: qvfmr 1, 5
1404; CHECK: blr
1405}
1406
1407define <4 x float> @testqv4floatsgt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1408entry:
1409 %cmp1 = fcmp oeq float %c3, %c4
1410 %cmp3tmp = fcmp oeq float %c1, %c2
1411 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
1412 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1413 ret <4 x float> %cond
1414
1415; CHECK-LABEL: @testqv4floatsgt
1416; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1417; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1418; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1419; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1420; CHECK: qvfmr 5, 6
1421; CHECK: .LBB[[BB]]:
1422; CHECK: qvfmr 1, 5
1423; CHECK: blr
1424}
1425
1426define <4 x float> @testqv4floatugt(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1427entry:
1428 %cmp1 = fcmp oeq float %c3, %c4
1429 %cmp3tmp = fcmp oeq float %c1, %c2
1430 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
1431 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1432 ret <4 x float> %cond
1433
1434; CHECK-LABEL: @testqv4floatugt
1435; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1436; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1437; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1438; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1439; CHECK: qvfmr 5, 6
1440; CHECK: .LBB[[BB]]:
1441; CHECK: qvfmr 1, 5
1442; CHECK: blr
1443}
1444
1445define <4 x float> @testqv4floatne(float %c1, float %c2, float %c3, float %c4, <4 x float> %a1, <4 x float> %a2) #1 {
1446entry:
1447 %cmp1 = fcmp oeq float %c3, %c4
1448 %cmp3tmp = fcmp oeq float %c1, %c2
1449 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
1450 %cond = select i1 %cmp3, <4 x float> %a1, <4 x float> %a2
1451 ret <4 x float> %cond
1452
1453; CHECK-LABEL: @testqv4floatne
1454; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1455; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1456; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1457; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1458; CHECK: qvfmr 5, 6
1459; CHECK: .LBB[[BB]]:
1460; CHECK: qvfmr 1, 5
1461; CHECK: blr
1462}
1463
1464define <4 x i1> @testqv4i1slt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1465entry:
1466 %cmp1 = fcmp oeq float %c3, %c4
1467 %cmp3tmp = fcmp oeq float %c1, %c2
1468 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
1469 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1470 ret <4 x i1> %cond
1471
1472; CHECK-LABEL: @testqv4i1slt
1473; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1474; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1475; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1476; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1477; CHECK: qvfmr 5, 6
1478; CHECK: .LBB[[BB]]:
1479; CHECK: qvfmr 1, 5
1480; CHECK: blr
1481}
1482
1483define <4 x i1> @testqv4i1ult(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1484entry:
1485 %cmp1 = fcmp oeq float %c3, %c4
1486 %cmp3tmp = fcmp oeq float %c1, %c2
1487 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
1488 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1489 ret <4 x i1> %cond
1490
1491; CHECK-LABEL: @testqv4i1ult
1492; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1493; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1494; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1495; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1496; CHECK: qvfmr 5, 6
1497; CHECK: .LBB[[BB]]:
1498; CHECK: qvfmr 1, 5
1499; CHECK: blr
1500}
1501
1502define <4 x i1> @testqv4i1sle(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1503entry:
1504 %cmp1 = fcmp oeq float %c3, %c4
1505 %cmp3tmp = fcmp oeq float %c1, %c2
1506 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
1507 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1508 ret <4 x i1> %cond
1509
1510; CHECK-LABEL: @testqv4i1sle
1511; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1512; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1513; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1514; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1515; CHECK: qvfmr 5, 6
1516; CHECK: .LBB[[BB]]:
1517; CHECK: qvfmr 1, 5
1518; CHECK: blr
1519}
1520
1521define <4 x i1> @testqv4i1ule(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1522entry:
1523 %cmp1 = fcmp oeq float %c3, %c4
1524 %cmp3tmp = fcmp oeq float %c1, %c2
1525 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
1526 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1527 ret <4 x i1> %cond
1528
1529; CHECK-LABEL: @testqv4i1ule
1530; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1531; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1532; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1533; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1534; CHECK: qvfmr 5, 6
1535; CHECK: .LBB[[BB]]:
1536; CHECK: qvfmr 1, 5
1537; CHECK: blr
1538}
1539
1540define <4 x i1> @testqv4i1eq(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1541entry:
1542 %cmp1 = fcmp oeq float %c3, %c4
1543 %cmp3tmp = fcmp oeq float %c1, %c2
1544 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
1545 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1546 ret <4 x i1> %cond
1547
1548; CHECK-LABEL: @testqv4i1eq
1549; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1550; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1551; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1552; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1553; CHECK: qvfmr 5, 6
1554; CHECK: .LBB[[BB]]:
1555; CHECK: qvfmr 1, 5
1556; CHECK: blr
1557}
1558
1559define <4 x i1> @testqv4i1sge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1560entry:
1561 %cmp1 = fcmp oeq float %c3, %c4
1562 %cmp3tmp = fcmp oeq float %c1, %c2
1563 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
1564 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1565 ret <4 x i1> %cond
1566
1567; CHECK-LABEL: @testqv4i1sge
1568; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1569; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1570; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1571; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1572; CHECK: qvfmr 5, 6
1573; CHECK: .LBB[[BB]]:
1574; CHECK: qvfmr 1, 5
1575; CHECK: blr
1576}
1577
1578define <4 x i1> @testqv4i1uge(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1579entry:
1580 %cmp1 = fcmp oeq float %c3, %c4
1581 %cmp3tmp = fcmp oeq float %c1, %c2
1582 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
1583 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1584 ret <4 x i1> %cond
1585
1586; CHECK-LABEL: @testqv4i1uge
1587; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1588; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1589; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1590; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1591; CHECK: qvfmr 5, 6
1592; CHECK: .LBB[[BB]]:
1593; CHECK: qvfmr 1, 5
1594; CHECK: blr
1595}
1596
1597define <4 x i1> @testqv4i1sgt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1598entry:
1599 %cmp1 = fcmp oeq float %c3, %c4
1600 %cmp3tmp = fcmp oeq float %c1, %c2
1601 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
1602 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1603 ret <4 x i1> %cond
1604
1605; CHECK-LABEL: @testqv4i1sgt
1606; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1607; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1608; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1609; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1610; CHECK: qvfmr 5, 6
1611; CHECK: .LBB[[BB]]:
1612; CHECK: qvfmr 1, 5
1613; CHECK: blr
1614}
1615
1616define <4 x i1> @testqv4i1ugt(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1617entry:
1618 %cmp1 = fcmp oeq float %c3, %c4
1619 %cmp3tmp = fcmp oeq float %c1, %c2
1620 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
1621 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1622 ret <4 x i1> %cond
1623
1624; CHECK-LABEL: @testqv4i1ugt
1625; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1626; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1627; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1628; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1629; CHECK: qvfmr 5, 6
1630; CHECK: .LBB[[BB]]:
1631; CHECK: qvfmr 1, 5
1632; CHECK: blr
1633}
1634
1635define <4 x i1> @testqv4i1ne(float %c1, float %c2, float %c3, float %c4, <4 x i1> %a1, <4 x i1> %a2) #1 {
1636entry:
1637 %cmp1 = fcmp oeq float %c3, %c4
1638 %cmp3tmp = fcmp oeq float %c1, %c2
1639 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
1640 %cond = select i1 %cmp3, <4 x i1> %a1, <4 x i1> %a2
1641 ret <4 x i1> %cond
1642
1643; CHECK-LABEL: @testqv4i1ne
1644; CHECK-DAG: fcmpu {{[0-9]+}}, 3, 4
1645; CHECK-DAG: fcmpu {{[0-9]+}}, 1, 2
1646; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
1647; CHECK: bc 12, [[REG1]], .LBB[[BB:[0-9_]+]]
1648; CHECK: qvfmr 5, 6
1649; CHECK: .LBB[[BB]]:
1650; CHECK: qvfmr 1, 5
1651; CHECK: blr
1652}
1653
1654attributes #0 = { nounwind readnone "target-cpu"="pwr7" }
1655attributes #1 = { nounwind readnone "target-cpu"="a2q" }
1656