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Jia Liuf54f60f2012-02-28 07:46:26 +00001//===-- MipsInstrFormats.td - Mips Instruction Formats -----*- tablegen -*-===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +00007//
Akira Hatanakae2489122011-04-15 21:51:11 +00008//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +00009
Akira Hatanakae2489122011-04-15 21:51:11 +000010//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000011// Describe MIPS instructions format
12//
Bruno Cardoso Lopes041604b2008-06-08 01:39:36 +000013// CPU INSTRUCTION FORMATS
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000014//
15// opcode - operation code.
16// rs - src reg.
17// rt - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
18// rd - dst reg, only used on 3 regs instr.
19// shamt - only used on shift instructions, contains the shift amount.
20// funct - combined with opcode field give us an operation code.
21//
Akira Hatanakae2489122011-04-15 21:51:11 +000022//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000023
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +000024// Format specifies the encoding used by the instruction. This is part of the
25// ad-hoc solution used to emit machine instruction encodings by our machine
26// code emitter.
27class Format<bits<4> val> {
28 bits<4> Value = val;
29}
30
31def Pseudo : Format<0>;
32def FrmR : Format<1>;
33def FrmI : Format<2>;
34def FrmJ : Format<3>;
35def FrmFR : Format<4>;
36def FrmFI : Format<5>;
37def FrmOther : Format<6>; // Instruction w/ a custom format
38
Akira Hatanakabe6a8182013-04-19 19:03:11 +000039class MMRel;
40
41def Std2MicroMips : InstrMapping {
42 let FilterClass = "MMRel";
43 // Instructions with the same BaseOpcode and isNVStore values form a row.
44 let RowFields = ["BaseOpcode"];
45 // Instructions with the same predicate sense form a column.
46 let ColFields = ["Arch"];
47 // The key column is the unpredicated instructions.
48 let KeyCol = ["se"];
49 // Value columns are PredSense=true and PredSense=false
50 let ValueCols = [["se"], ["micromips"]];
51}
52
Zoran Jovanovicb59a5412015-04-22 13:27:34 +000053class StdMMR6Rel;
54
55def Std2MicroMipsR6 : InstrMapping {
56 let FilterClass = "StdMMR6Rel";
57 // Instructions with the same BaseOpcode and isNVStore values form a row.
58 let RowFields = ["BaseOpcode"];
59 // Instructions with the same predicate sense form a column.
60 let ColFields = ["Arch"];
61 // The key column is the unpredicated instructions.
62 let KeyCol = ["se"];
63 // Value columns are PredSense=true and PredSense=false
64 let ValueCols = [["se"], ["micromipsr6"]];
65}
66
Akira Hatanakabe6a8182013-04-19 19:03:11 +000067class StdArch {
68 string Arch = "se";
69}
70
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000071// Generic Mips Format
Akira Hatanakaa66d6762012-07-31 19:13:07 +000072class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
73 InstrItinClass itin, Format f>: Instruction
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000074{
75 field bits<32> Inst;
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +000076 Format Form = f;
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000077
78 let Namespace = "Mips";
79
Akira Hatanaka71928e62012-04-17 18:03:21 +000080 let Size = 4;
81
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +000082 bits<6> Opcode = 0;
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000083
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +000084 // Top 6 bits are the 'opcode' field
85 let Inst{31-26} = Opcode;
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +000086
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +000087 let OutOperandList = outs;
88 let InOperandList = ins;
Bruno Cardoso Lopes57921892007-08-18 02:01:28 +000089
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +000090 let AsmString = asmstr;
91 let Pattern = pattern;
Bruno Cardoso Lopesd4b99452007-08-21 16:06:45 +000092 let Itinerary = itin;
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +000093
94 //
95 // Attributes specific to Mips instructions...
96 //
Daniel Sanderse8efff32016-03-14 16:24:05 +000097 bits<4> FormBits = Form.Value;
98 bit isCTI = 0; // Any form of Control Transfer Instruction.
99 // Required for MIPSR6
100 bit hasForbiddenSlot = 0; // Instruction has a forbidden slot.
Hrvoje Vargadbe4d962016-09-08 07:41:43 +0000101 bit IsPCRelativeLoad = 0; // Load instruction with implicit source register
102 // ($pc) and with explicit offset and destination
103 // register
Simon Dardis730fdb72017-01-16 13:55:58 +0000104 bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is
105 // present in MIPS-I to MIPS-III.
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +0000106
Simon Dardis730fdb72017-01-16 13:55:58 +0000107 // TSFlags layout should be kept in sync with MCTargetDesc/MipsBaseInfo.h.
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +0000108 let TSFlags{3-0} = FormBits;
Daniel Sanderse8efff32016-03-14 16:24:05 +0000109 let TSFlags{4} = isCTI;
110 let TSFlags{5} = hasForbiddenSlot;
Hrvoje Vargadbe4d962016-09-08 07:41:43 +0000111 let TSFlags{6} = IsPCRelativeLoad;
Simon Dardis730fdb72017-01-16 13:55:58 +0000112 let TSFlags{7} = hasFCCRegOperand;
Akira Hatanaka71928e62012-04-17 18:03:21 +0000113
114 let DecoderNamespace = "Mips";
115
116 field bits<32> SoftFail = 0;
Akira Hatanakaa66d6762012-07-31 19:13:07 +0000117}
Akira Hatanakacdf4fd82012-05-22 03:10:09 +0000118
Akira Hatanakaa66d6762012-07-31 19:13:07 +0000119// Mips32/64 Instruction Format
120class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000121 InstrItinClass itin, Format f, string opstr = ""> :
Daniel Sanders3dc2c012014-05-07 10:27:09 +0000122 MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl {
123 let EncodingPredicates = [HasStdEnc];
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000124 string BaseOpcode = opstr;
125 string Arch;
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000126}
127
Bruno Cardoso Lopes5cef9cf2007-10-09 02:55:31 +0000128// Mips Pseudo Instructions Format
Akira Hatanakab1527b72012-12-20 04:20:09 +0000129class MipsPseudo<dag outs, dag ins, list<dag> pattern,
130 InstrItinClass itin = IIPseudo> :
131 MipsInst<outs, ins, "", pattern, itin, Pseudo> {
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +0000132 let isCodeGenOnly = 1;
Akira Hatanakabb050742011-09-27 04:57:54 +0000133 let isPseudo = 1;
134}
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000135
Akira Hatanakaa66d6762012-07-31 19:13:07 +0000136// Mips32/64 Pseudo Instruction Format
Akira Hatanakab1527b72012-12-20 04:20:09 +0000137class PseudoSE<dag outs, dag ins, list<dag> pattern,
Daniel Sanders3dc2c012014-05-07 10:27:09 +0000138 InstrItinClass itin = IIPseudo> :
139 MipsPseudo<outs, ins, pattern, itin>, PredicateControl {
140 let EncodingPredicates = [HasStdEnc];
Akira Hatanakaa66d6762012-07-31 19:13:07 +0000141}
142
Jack Carter30a59822012-10-04 04:03:53 +0000143// Pseudo-instructions for alternate assembly syntax (never used by codegen).
144// These are aliases that require C++ handling to convert to the target
145// instruction, while InstAliases can be handled directly by tblgen.
146class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
Zoran Jovanovic8eb8c982015-09-15 15:06:26 +0000147 MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo>, PredicateControl {
Jack Carter30a59822012-10-04 04:03:53 +0000148 let isPseudo = 1;
149 let Pattern = [];
150}
Akira Hatanakae2489122011-04-15 21:51:11 +0000151//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000152// Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
Akira Hatanakae2489122011-04-15 21:51:11 +0000153//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000154
Evan Cheng94b5a802007-07-19 01:14:50 +0000155class FR<bits<6> op, bits<6> _funct, dag outs, dag ins, string asmstr,
Bruno Cardoso Lopes57921892007-08-18 02:01:28 +0000156 list<dag> pattern, InstrItinClass itin>:
Akira Hatanaka3a810ed2012-07-31 18:55:01 +0000157 InstSE<outs, ins, asmstr, pattern, itin, FrmR>
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000158{
159 bits<5> rd;
160 bits<5> rs;
161 bits<5> rt;
162 bits<5> shamt;
163 bits<6> funct;
164
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +0000165 let Opcode = op;
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000166 let funct = _funct;
167
168 let Inst{25-21} = rs;
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000169 let Inst{20-16} = rt;
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000170 let Inst{15-11} = rd;
171 let Inst{10-6} = shamt;
172 let Inst{5-0} = funct;
173}
174
Akira Hatanakae2489122011-04-15 21:51:11 +0000175//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000176// Format I instruction class in Mips : <|opcode|rs|rt|immediate|>
Akira Hatanakae2489122011-04-15 21:51:11 +0000177//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000178
Bruno Cardoso Lopes57921892007-08-18 02:01:28 +0000179class FI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
Akira Hatanaka3a810ed2012-07-31 18:55:01 +0000180 InstrItinClass itin>: InstSE<outs, ins, asmstr, pattern, itin, FrmI>
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000181{
182 bits<5> rt;
183 bits<5> rs;
184 bits<16> imm16;
185
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +0000186 let Opcode = op;
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000187
188 let Inst{25-21} = rs;
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000189 let Inst{20-16} = rt;
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000190 let Inst{15-0} = imm16;
191}
192
Bruno Cardoso Lopes0c24d8a2011-12-06 03:34:48 +0000193class BranchBase<bits<6> op, dag outs, dag ins, string asmstr,
Akira Hatanaka4b6ac982011-10-11 18:49:17 +0000194 list<dag> pattern, InstrItinClass itin>:
Akira Hatanaka3a810ed2012-07-31 18:55:01 +0000195 InstSE<outs, ins, asmstr, pattern, itin, FrmI>
Akira Hatanaka4b6ac982011-10-11 18:49:17 +0000196{
197 bits<5> rs;
198 bits<5> rt;
199 bits<16> imm16;
200
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +0000201 let Opcode = op;
Akira Hatanaka4b6ac982011-10-11 18:49:17 +0000202
203 let Inst{25-21} = rs;
204 let Inst{20-16} = rt;
205 let Inst{15-0} = imm16;
206}
207
Akira Hatanakae2489122011-04-15 21:51:11 +0000208//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000209// Format J instruction class in Mips : <|opcode|address|>
Akira Hatanakae2489122011-04-15 21:51:11 +0000210//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000211
Zoran Jovanovic507e0842013-10-29 16:38:59 +0000212class FJ<bits<6> op> : StdArch
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000213{
Akira Hatanakaa1580422012-12-21 23:03:50 +0000214 bits<26> target;
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000215
Akira Hatanakaa1580422012-12-21 23:03:50 +0000216 bits<32> Inst;
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000217
Akira Hatanakaa1580422012-12-21 23:03:50 +0000218 let Inst{31-26} = op;
219 let Inst{25-0} = target;
Bruno Cardoso Lopes35e43c42007-06-06 07:42:06 +0000220}
Bruno Cardoso Lopes5cef9cf2007-10-09 02:55:31 +0000221
Akira Hatanakae067e5a2013-01-04 19:38:05 +0000222//===----------------------------------------------------------------------===//
Jack Cartere948ec52012-10-06 01:17:37 +0000223// MFC instruction class in Mips : <|op|mf|rt|rd|0000000|sel|>
224//===----------------------------------------------------------------------===//
Akira Hatanakae36e2f62013-01-04 19:13:49 +0000225class MFC3OP_FM<bits<6> op, bits<5> mfmt>
Jack Cartere948ec52012-10-06 01:17:37 +0000226{
Jack Cartere948ec52012-10-06 01:17:37 +0000227 bits<5> rt;
228 bits<5> rd;
229 bits<3> sel;
230
Akira Hatanakae36e2f62013-01-04 19:13:49 +0000231 bits<32> Inst;
Jack Cartere948ec52012-10-06 01:17:37 +0000232
Akira Hatanakae36e2f62013-01-04 19:13:49 +0000233 let Inst{31-26} = op;
Jack Cartere948ec52012-10-06 01:17:37 +0000234 let Inst{25-21} = mfmt;
235 let Inst{20-16} = rt;
236 let Inst{15-11} = rd;
237 let Inst{10-3} = 0;
238 let Inst{2-0} = sel;
239}
240
Kai Nacke3adf9b82015-05-28 16:23:16 +0000241class MFC2OP_FM<bits<6> op, bits<5> mfmt> : StdArch {
242 bits<5> rt;
243 bits<16> imm16;
244
245 bits<32> Inst;
246
247 let Inst{31-26} = op;
248 let Inst{25-21} = mfmt;
249 let Inst{20-16} = rt;
250 let Inst{15-0} = imm16;
251}
252
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000253class ADD_FM<bits<6> op, bits<6> funct> : StdArch {
Akira Hatanaka1b37c4a2012-12-20 03:34:05 +0000254 bits<5> rd;
255 bits<5> rs;
256 bits<5> rt;
257
258 bits<32> Inst;
259
260 let Inst{31-26} = op;
261 let Inst{25-21} = rs;
262 let Inst{20-16} = rt;
263 let Inst{15-11} = rd;
264 let Inst{10-6} = 0;
265 let Inst{5-0} = funct;
266}
267
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000268class ADDI_FM<bits<6> op> : StdArch {
Akira Hatanakaab1b715b2012-12-20 03:40:03 +0000269 bits<5> rs;
270 bits<5> rt;
271 bits<16> imm16;
272
273 bits<32> Inst;
274
275 let Inst{31-26} = op;
276 let Inst{25-21} = rs;
277 let Inst{20-16} = rt;
278 let Inst{15-0} = imm16;
279}
280
Akira Hatanakacd9b74a2013-04-25 01:11:15 +0000281class SRA_FM<bits<6> funct, bit rotate> : StdArch {
Akira Hatanaka7f96ad32012-12-20 03:44:41 +0000282 bits<5> rd;
283 bits<5> rt;
284 bits<5> shamt;
285
286 bits<32> Inst;
287
288 let Inst{31-26} = 0;
289 let Inst{25-22} = 0;
290 let Inst{21} = rotate;
291 let Inst{20-16} = rt;
292 let Inst{15-11} = rd;
293 let Inst{10-6} = shamt;
294 let Inst{5-0} = funct;
295}
296
Akira Hatanakacd9b74a2013-04-25 01:11:15 +0000297class SRLV_FM<bits<6> funct, bit rotate> : StdArch {
Akira Hatanaka244f9e82012-12-20 03:48:24 +0000298 bits<5> rd;
299 bits<5> rt;
300 bits<5> rs;
301
302 bits<32> Inst;
303
304 let Inst{31-26} = 0;
305 let Inst{25-21} = rs;
306 let Inst{20-16} = rt;
307 let Inst{15-11} = rd;
308 let Inst{10-7} = 0;
309 let Inst{6} = rotate;
310 let Inst{5-0} = funct;
311}
312
Zoran Jovanovic8a80aa72013-11-04 14:53:22 +0000313class BEQ_FM<bits<6> op> : StdArch {
Akira Hatanakaf71ffd22012-12-20 04:10:13 +0000314 bits<5> rs;
315 bits<5> rt;
316 bits<16> offset;
317
318 bits<32> Inst;
319
320 let Inst{31-26} = op;
321 let Inst{25-21} = rs;
322 let Inst{20-16} = rt;
323 let Inst{15-0} = offset;
324}
325
Zoran Jovanovic8a80aa72013-11-04 14:53:22 +0000326class BGEZ_FM<bits<6> op, bits<5> funct> : StdArch {
Akira Hatanakac0ea0bb2012-12-20 04:13:23 +0000327 bits<5> rs;
328 bits<16> offset;
329
330 bits<32> Inst;
331
332 let Inst{31-26} = op;
333 let Inst{25-21} = rs;
334 let Inst{20-16} = funct;
335 let Inst{15-0} = offset;
336}
337
Kai Nacke63072f82015-01-20 16:10:51 +0000338class BBIT_FM<bits<6> op> : StdArch {
339 bits<5> rs;
340 bits<5> p;
341 bits<16> offset;
342
343 bits<32> Inst;
344
345 let Inst{31-26} = op;
346 let Inst{25-21} = rs;
347 let Inst{20-16} = p;
348 let Inst{15-0} = offset;
349}
350
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000351class SLTI_FM<bits<6> op> : StdArch {
Akira Hatanakae7f1acc2012-12-20 04:27:52 +0000352 bits<5> rt;
353 bits<5> rs;
354 bits<16> imm16;
355
356 bits<32> Inst;
357
358 let Inst{31-26} = op;
359 let Inst{25-21} = rs;
360 let Inst{20-16} = rt;
361 let Inst{15-0} = imm16;
362}
363
Vladimir Medic457ba562013-09-06 12:53:21 +0000364class MFLO_FM<bits<6> funct> : StdArch {
Akira Hatanakab14c6e42012-12-21 22:39:17 +0000365 bits<5> rd;
366
367 bits<32> Inst;
368
369 let Inst{31-26} = 0;
370 let Inst{25-16} = 0;
371 let Inst{15-11} = rd;
372 let Inst{10-6} = 0;
373 let Inst{5-0} = funct;
374}
375
Vladimir Medic457ba562013-09-06 12:53:21 +0000376class MTLO_FM<bits<6> funct> : StdArch {
Akira Hatanakab14c6e42012-12-21 22:39:17 +0000377 bits<5> rs;
378
379 bits<32> Inst;
380
381 let Inst{31-26} = 0;
382 let Inst{25-21} = rs;
383 let Inst{20-6} = 0;
384 let Inst{5-0} = funct;
385}
386
Zoran Jovanovicab852782013-09-14 06:49:25 +0000387class SEB_FM<bits<5> funct, bits<6> funct2> : StdArch {
Akira Hatanaka4f4c4aa2012-12-21 22:41:52 +0000388 bits<5> rd;
389 bits<5> rt;
390
391 bits<32> Inst;
392
393 let Inst{31-26} = 0x1f;
394 let Inst{25-21} = 0;
395 let Inst{20-16} = rt;
396 let Inst{15-11} = rd;
397 let Inst{10-6} = funct;
Akira Hatanaka6ac2fc42012-12-21 23:21:32 +0000398 let Inst{5-0} = funct2;
Akira Hatanaka4f4c4aa2012-12-21 22:41:52 +0000399}
400
Zoran Jovanovicab852782013-09-14 06:49:25 +0000401class CLO_FM<bits<6> funct> : StdArch {
Akira Hatanaka895e1cb2012-12-21 22:43:58 +0000402 bits<5> rd;
403 bits<5> rs;
404 bits<5> rt;
405
406 bits<32> Inst;
407
408 let Inst{31-26} = 0x1c;
409 let Inst{25-21} = rs;
410 let Inst{20-16} = rt;
411 let Inst{15-11} = rd;
412 let Inst{10-6} = 0;
413 let Inst{5-0} = funct;
414 let rt = rd;
415}
416
Zoran Jovanovicfc26cfc2013-09-14 07:35:41 +0000417class LUI_FM : StdArch {
Akira Hatanakae738efc2012-12-21 22:46:07 +0000418 bits<5> rt;
419 bits<16> imm16;
420
421 bits<32> Inst;
422
423 let Inst{31-26} = 0xf;
424 let Inst{25-21} = 0;
425 let Inst{20-16} = rt;
426 let Inst{15-0} = imm16;
427}
428
Zoran Jovanovic87d13e52014-03-20 10:18:24 +0000429class JALR_FM {
Akira Hatanaka061d1ea2013-02-07 19:48:00 +0000430 bits<5> rd;
Akira Hatanakaa1580422012-12-21 23:03:50 +0000431 bits<5> rs;
432
433 bits<32> Inst;
434
435 let Inst{31-26} = 0;
436 let Inst{25-21} = rs;
437 let Inst{20-16} = 0;
Akira Hatanaka061d1ea2013-02-07 19:48:00 +0000438 let Inst{15-11} = rd;
Akira Hatanakaa1580422012-12-21 23:03:50 +0000439 let Inst{10-6} = 0;
440 let Inst{5-0} = 9;
441}
442
Zoran Jovanovic8a80aa72013-11-04 14:53:22 +0000443class BGEZAL_FM<bits<5> funct> : StdArch {
Akira Hatanaka31ddec582012-12-21 23:15:59 +0000444 bits<5> rs;
445 bits<16> offset;
446
447 bits<32> Inst;
448
449 let Inst{31-26} = 1;
450 let Inst{25-21} = rs;
451 let Inst{20-16} = funct;
452 let Inst{15-0} = offset;
453}
454
Zoran Jovanovic8e918c32013-12-19 16:25:00 +0000455class SYNC_FM : StdArch {
Akira Hatanakabeea8a32012-12-21 23:17:36 +0000456 bits<5> stype;
457
458 bits<32> Inst;
459
460 let Inst{31-26} = 0;
461 let Inst{10-6} = stype;
462 let Inst{5-0} = 0xf;
463}
464
Daniel Sandersb4484d62014-11-27 17:28:10 +0000465class SYNCI_FM : StdArch {
466 // Produced by the mem_simm16 address as reg << 16 | imm (see getMemEncoding).
467 bits<21> addr;
468 bits<5> rs = addr{20-16};
469 bits<16> offset = addr{15-0};
470
471 bits<32> Inst;
472
473 let Inst{31-26} = 0b000001;
474 let Inst{25-21} = rs;
475 let Inst{20-16} = 0b11111;
476 let Inst{15-0} = offset;
477}
478
Akira Hatanakabe6a8182013-04-19 19:03:11 +0000479class MULT_FM<bits<6> op, bits<6> funct> : StdArch {
Akira Hatanakabeea8a32012-12-21 23:17:36 +0000480 bits<5> rs;
481 bits<5> rt;
482
483 bits<32> Inst;
484
485 let Inst{31-26} = op;
486 let Inst{25-21} = rs;
487 let Inst{20-16} = rt;
488 let Inst{15-6} = 0;
489 let Inst{5-0} = funct;
490}
491
Zoran Jovanovicab852782013-09-14 06:49:25 +0000492class EXT_FM<bits<6> funct> : StdArch {
Akira Hatanaka6ac2fc42012-12-21 23:21:32 +0000493 bits<5> rt;
494 bits<5> rs;
495 bits<5> pos;
496 bits<5> size;
497
498 bits<32> Inst;
499
500 let Inst{31-26} = 0x1f;
501 let Inst{25-21} = rs;
502 let Inst{20-16} = rt;
503 let Inst{15-11} = size;
504 let Inst{10-6} = pos;
505 let Inst{5-0} = funct;
506}
507
Jozef Kolekdc62fc42014-11-19 11:25:50 +0000508class RDHWR_FM : StdArch {
Akira Hatanaka6ac2fc42012-12-21 23:21:32 +0000509 bits<5> rt;
510 bits<5> rd;
511
512 bits<32> Inst;
513
514 let Inst{31-26} = 0x1f;
515 let Inst{25-21} = 0;
516 let Inst{20-16} = rt;
517 let Inst{15-11} = rd;
518 let Inst{10-6} = 0;
519 let Inst{5-0} = 0x3b;
520}
521
Zoran Jovanovicc18b6d12013-11-07 14:35:24 +0000522class TEQ_FM<bits<6> funct> : StdArch {
Akira Hatanaka1cb02422013-05-20 18:07:43 +0000523 bits<5> rs;
524 bits<5> rt;
525 bits<10> code_;
526
527 bits<32> Inst;
528
529 let Inst{31-26} = 0;
530 let Inst{25-21} = rs;
531 let Inst{20-16} = rt;
532 let Inst{15-6} = code_;
533 let Inst{5-0} = funct;
534}
535
Zoran Jovanovicccb70ca2013-11-13 13:15:03 +0000536class TEQI_FM<bits<5> funct> : StdArch {
Vladimir Medic8277c182013-08-26 10:02:40 +0000537 bits<5> rs;
538 bits<16> imm16;
539
540 bits<32> Inst;
541
542 let Inst{31-26} = 1;
543 let Inst{25-21} = rs;
544 let Inst{20-16} = funct;
545 let Inst{15-0} = imm16;
546}
Zoran Jovanovic8e918c32013-12-19 16:25:00 +0000547
548class WAIT_FM : StdArch {
549 bits<32> Inst;
550
551 let Inst{31-26} = 0x10;
552 let Inst{25} = 1;
553 let Inst{24-6} = 0;
554 let Inst{5-0} = 0x20;
555}
556
Kai Nacke13673ac2014-04-02 18:40:43 +0000557class EXTS_FM<bits<6> funct> : StdArch {
558 bits<5> rt;
559 bits<5> rs;
560 bits<5> pos;
561 bits<5> lenm1;
562
563 bits<32> Inst;
564
565 let Inst{31-26} = 0x1c;
566 let Inst{25-21} = rs;
567 let Inst{20-16} = rt;
568 let Inst{15-11} = lenm1;
569 let Inst{10-6} = pos;
570 let Inst{5-0} = funct;
571}
572
Kai Nackeaf47f602014-04-01 18:35:26 +0000573class MTMR_FM<bits<6> funct> : StdArch {
574 bits<5> rs;
575
576 bits<32> Inst;
577
578 let Inst{31-26} = 0x1c;
579 let Inst{25-21} = rs;
580 let Inst{20-6} = 0;
581 let Inst{5-0} = funct;
582}
583
Kai Nacke93fe5e82014-03-20 11:51:58 +0000584class POP_FM<bits<6> funct> : StdArch {
585 bits<5> rd;
586 bits<5> rs;
587
588 bits<32> Inst;
589
590 let Inst{31-26} = 0x1c;
591 let Inst{25-21} = rs;
592 let Inst{20-16} = 0;
593 let Inst{15-11} = rd;
594 let Inst{10-6} = 0;
595 let Inst{5-0} = funct;
596}
597
598class SEQ_FM<bits<6> funct> : StdArch {
599 bits<5> rd;
600 bits<5> rs;
601 bits<5> rt;
602
603 bits<32> Inst;
604
605 let Inst{31-26} = 0x1c;
606 let Inst{25-21} = rs;
607 let Inst{20-16} = rt;
608 let Inst{15-11} = rd;
609 let Inst{10-6} = 0;
610 let Inst{5-0} = funct;
611}
612
Kai Nacke6da86e82014-04-04 16:21:59 +0000613class SEQI_FM<bits<6> funct> : StdArch {
614 bits<5> rs;
615 bits<5> rt;
616 bits<10> imm10;
617
618 bits<32> Inst;
619
620 let Inst{31-26} = 0x1c;
621 let Inst{25-21} = rs;
622 let Inst{20-16} = rt;
623 let Inst{15-6} = imm10;
624 let Inst{5-0} = funct;
625}
626
Akira Hatanakae2489122011-04-15 21:51:11 +0000627//===----------------------------------------------------------------------===//
Vladimir Medicbcf1ca02013-07-12 09:25:35 +0000628// System calls format <op|code_|funct>
629//===----------------------------------------------------------------------===//
630
Zoran Jovanovic8e918c32013-12-19 16:25:00 +0000631class SYS_FM<bits<6> funct> : StdArch
Vladimir Medicbcf1ca02013-07-12 09:25:35 +0000632{
633 bits<20> code_;
634 bits<32> Inst;
635 let Inst{31-26} = 0x0;
636 let Inst{25-6} = code_;
637 let Inst{5-0} = funct;
638}
639
640//===----------------------------------------------------------------------===//
641// Break instruction format <op|code_1|funct>
642//===----------------------------------------------------------------------===//
643
Zoran Jovanovic8e918c32013-12-19 16:25:00 +0000644class BRK_FM<bits<6> funct> : StdArch
Vladimir Medicbcf1ca02013-07-12 09:25:35 +0000645{
646 bits<10> code_1;
647 bits<10> code_2;
648 bits<32> Inst;
649 let Inst{31-26} = 0x0;
650 let Inst{25-16} = code_1;
651 let Inst{15-6} = code_2;
652 let Inst{5-0} = funct;
653}
654
655//===----------------------------------------------------------------------===//
Vladimir Medic29410f92013-07-17 14:05:19 +0000656// Exception return format <Cop0|1|0|funct>
657//===----------------------------------------------------------------------===//
658
Vasileios Kalintiris974d4092015-07-20 12:28:56 +0000659class ER_FM<bits<6> funct, bit LLBit> : StdArch
Vladimir Medic29410f92013-07-17 14:05:19 +0000660{
661 bits<32> Inst;
662 let Inst{31-26} = 0x10;
663 let Inst{25} = 1;
Vasileios Kalintiris974d4092015-07-20 12:28:56 +0000664 let Inst{24-7} = 0;
665 let Inst{6} = LLBit;
Vladimir Medic29410f92013-07-17 14:05:19 +0000666 let Inst{5-0} = funct;
667}
668
Vladimir Medic939877e2013-08-12 13:07:23 +0000669//===----------------------------------------------------------------------===//
670// Enable/disable interrupt instruction format <Cop0|MFMC0|rt|12|0|sc|0|0>
671//===----------------------------------------------------------------------===//
672
Zoran Jovanovic8e918c32013-12-19 16:25:00 +0000673class EI_FM<bits<1> sc> : StdArch
Vladimir Medic939877e2013-08-12 13:07:23 +0000674{
675 bits<32> Inst;
676 bits<5> rt;
677 let Inst{31-26} = 0x10;
678 let Inst{25-21} = 0xb;
679 let Inst{20-16} = rt;
680 let Inst{15-11} = 0xc;
681 let Inst{10-6} = 0;
682 let Inst{5} = sc;
683 let Inst{4-0} = 0;
684}
685
Vladimir Medic29410f92013-07-17 14:05:19 +0000686//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes041604b2008-06-08 01:39:36 +0000687//
Bruno Cardoso Lopes7ceec572008-07-09 04:45:36 +0000688// FLOATING POINT INSTRUCTION FORMATS
Bruno Cardoso Lopes041604b2008-06-08 01:39:36 +0000689//
690// opcode - operation code.
691// fs - src reg.
692// ft - dst reg (on a 2 regs instr) or src reg (on a 3 reg instr).
693// fd - dst reg, only used on 3 regs instr.
694// fmt - double or single precision.
695// funct - combined with opcode field give us an operation code.
696//
Akira Hatanakae2489122011-04-15 21:51:11 +0000697//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes041604b2008-06-08 01:39:36 +0000698
Akira Hatanakae2489122011-04-15 21:51:11 +0000699//===----------------------------------------------------------------------===//
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000700// Format FI instruction class in Mips : <|opcode|base|ft|immediate|>
Akira Hatanakae2489122011-04-15 21:51:11 +0000701//===----------------------------------------------------------------------===//
Bruno Cardoso Lopes041604b2008-06-08 01:39:36 +0000702
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000703class FFI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern>:
Akira Hatanaka3a810ed2012-07-31 18:55:01 +0000704 InstSE<outs, ins, asmstr, pattern, NoItinerary, FrmFI>
Bruno Cardoso Lopes041604b2008-06-08 01:39:36 +0000705{
706 bits<5> ft;
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000707 bits<5> base;
Bruno Cardoso Lopes041604b2008-06-08 01:39:36 +0000708 bits<16> imm16;
709
Bruno Cardoso Lopes2312a3a2011-10-18 17:50:36 +0000710 let Opcode = op;
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000711
712 let Inst{25-21} = base;
Bruno Cardoso Lopesed874ef2011-03-04 17:51:39 +0000713 let Inst{20-16} = ft;
Bruno Cardoso Lopesc9c3f492008-07-05 19:05:21 +0000714 let Inst{15-0} = imm16;
715}
716
Zoran Jovanovicce024862013-12-20 15:44:08 +0000717class ADDS_FM<bits<6> funct, bits<5> fmt> : StdArch {
Akira Hatanaka29b51382012-12-13 01:07:37 +0000718 bits<5> fd;
719 bits<5> fs;
720 bits<5> ft;
721
722 bits<32> Inst;
723
724 let Inst{31-26} = 0x11;
725 let Inst{25-21} = fmt;
726 let Inst{20-16} = ft;
727 let Inst{15-11} = fs;
728 let Inst{10-6} = fd;
729 let Inst{5-0} = funct;
730}
Akira Hatanakadea8f612012-12-13 01:14:07 +0000731
Zoran Jovanovicce024862013-12-20 15:44:08 +0000732class ABSS_FM<bits<6> funct, bits<5> fmt> : StdArch {
Akira Hatanakadea8f612012-12-13 01:14:07 +0000733 bits<5> fd;
734 bits<5> fs;
735
736 bits<32> Inst;
737
738 let Inst{31-26} = 0x11;
739 let Inst{25-21} = fmt;
740 let Inst{20-16} = 0;
741 let Inst{15-11} = fs;
742 let Inst{10-6} = fd;
743 let Inst{5-0} = funct;
744}
Akira Hatanaka2b75dde2012-12-13 01:16:49 +0000745
Zoran Jovanovic8876be32013-12-25 10:09:27 +0000746class MFC1_FM<bits<5> funct> : StdArch {
Akira Hatanaka2b75dde2012-12-13 01:16:49 +0000747 bits<5> rt;
748 bits<5> fs;
749
750 bits<32> Inst;
751
752 let Inst{31-26} = 0x11;
753 let Inst{25-21} = funct;
754 let Inst{20-16} = rt;
755 let Inst{15-11} = fs;
756 let Inst{10-0} = 0;
757}
Akira Hatanaka92994f42012-12-13 01:24:00 +0000758
Akira Hatanakaf0aa6c92013-04-25 01:21:25 +0000759class LW_FM<bits<6> op> : StdArch {
Akira Hatanaka92994f42012-12-13 01:24:00 +0000760 bits<5> rt;
761 bits<21> addr;
762
763 bits<32> Inst;
764
765 let Inst{31-26} = op;
766 let Inst{25-21} = addr{20-16};
767 let Inst{20-16} = rt;
768 let Inst{15-0} = addr{15-0};
769}
Akira Hatanakab0d4acb2012-12-13 01:27:48 +0000770
Zoran Jovanovicce024862013-12-20 15:44:08 +0000771class MADDS_FM<bits<3> funct, bits<3> fmt> : StdArch {
Akira Hatanakab0d4acb2012-12-13 01:27:48 +0000772 bits<5> fd;
773 bits<5> fr;
774 bits<5> fs;
775 bits<5> ft;
776
777 bits<32> Inst;
778
779 let Inst{31-26} = 0x13;
780 let Inst{25-21} = fr;
781 let Inst{20-16} = ft;
782 let Inst{15-11} = fs;
783 let Inst{10-6} = fd;
784 let Inst{5-3} = funct;
785 let Inst{2-0} = fmt;
786}
Akira Hatanakacd3dfd22012-12-13 01:30:49 +0000787
Zoran Jovanovicce024862013-12-20 15:44:08 +0000788class LWXC1_FM<bits<6> funct> : StdArch {
Akira Hatanakacd3dfd22012-12-13 01:30:49 +0000789 bits<5> fd;
790 bits<5> base;
791 bits<5> index;
792
793 bits<32> Inst;
794
795 let Inst{31-26} = 0x13;
796 let Inst{25-21} = base;
797 let Inst{20-16} = index;
798 let Inst{15-11} = 0;
799 let Inst{10-6} = fd;
800 let Inst{5-0} = funct;
801}
802
Zoran Jovanovicce024862013-12-20 15:44:08 +0000803class SWXC1_FM<bits<6> funct> : StdArch {
Akira Hatanakacd3dfd22012-12-13 01:30:49 +0000804 bits<5> fs;
805 bits<5> base;
806 bits<5> index;
807
808 bits<32> Inst;
809
810 let Inst{31-26} = 0x13;
811 let Inst{25-21} = base;
812 let Inst{20-16} = index;
813 let Inst{15-11} = fs;
814 let Inst{10-6} = 0;
815 let Inst{5-0} = funct;
816}
Akira Hatanakafd9163b2012-12-13 01:32:36 +0000817
Zoran Jovanovicce024862013-12-20 15:44:08 +0000818class BC1F_FM<bit nd, bit tf> : StdArch {
Akira Hatanaka1fb1b8b2013-07-26 20:13:47 +0000819 bits<3> fcc;
Akira Hatanakafd9163b2012-12-13 01:32:36 +0000820 bits<16> offset;
821
822 bits<32> Inst;
823
824 let Inst{31-26} = 0x11;
825 let Inst{25-21} = 0x8;
Akira Hatanaka1fb1b8b2013-07-26 20:13:47 +0000826 let Inst{20-18} = fcc;
Akira Hatanakafd9163b2012-12-13 01:32:36 +0000827 let Inst{17} = nd;
828 let Inst{16} = tf;
829 let Inst{15-0} = offset;
830}
Akira Hatanaka79e1cdb2012-12-13 01:34:09 +0000831
Zoran Jovanovicce024862013-12-20 15:44:08 +0000832class CEQS_FM<bits<5> fmt> : StdArch {
Akira Hatanaka79e1cdb2012-12-13 01:34:09 +0000833 bits<5> fs;
834 bits<5> ft;
Simon Dardis730fdb72017-01-16 13:55:58 +0000835 bits<3> fcc;
Akira Hatanaka79e1cdb2012-12-13 01:34:09 +0000836 bits<4> cond;
837
838 bits<32> Inst;
839
840 let Inst{31-26} = 0x11;
841 let Inst{25-21} = fmt;
842 let Inst{20-16} = ft;
843 let Inst{15-11} = fs;
Simon Dardis730fdb72017-01-16 13:55:58 +0000844 let Inst{10-8} = fcc;
Akira Hatanaka79e1cdb2012-12-13 01:34:09 +0000845 let Inst{7-4} = 0x3;
846 let Inst{3-0} = cond;
847}
Akira Hatanaka6262bbf2012-12-13 01:41:15 +0000848
Vladimir Medic64828a12013-07-16 10:07:14 +0000849class C_COND_FM<bits<5> fmt, bits<4> c> : CEQS_FM<fmt> {
850 let cond = c;
851}
852
Zoran Jovanovic8876be32013-12-25 10:09:27 +0000853class CMov_I_F_FM<bits<6> funct, bits<5> fmt> : StdArch {
Akira Hatanaka6262bbf2012-12-13 01:41:15 +0000854 bits<5> fd;
855 bits<5> fs;
856 bits<5> rt;
857
858 bits<32> Inst;
859
860 let Inst{31-26} = 0x11;
861 let Inst{25-21} = fmt;
862 let Inst{20-16} = rt;
863 let Inst{15-11} = fs;
864 let Inst{10-6} = fd;
865 let Inst{5-0} = funct;
866}
867
Vladimir Medice0fbb442013-09-06 12:41:17 +0000868class CMov_F_I_FM<bit tf> : StdArch {
Akira Hatanaka6262bbf2012-12-13 01:41:15 +0000869 bits<5> rd;
870 bits<5> rs;
Akira Hatanaka8bce21c2013-07-26 20:51:20 +0000871 bits<3> fcc;
Akira Hatanaka6262bbf2012-12-13 01:41:15 +0000872
873 bits<32> Inst;
874
875 let Inst{31-26} = 0;
876 let Inst{25-21} = rs;
Akira Hatanaka8bce21c2013-07-26 20:51:20 +0000877 let Inst{20-18} = fcc;
Akira Hatanaka6262bbf2012-12-13 01:41:15 +0000878 let Inst{17} = 0;
879 let Inst{16} = tf;
880 let Inst{15-11} = rd;
881 let Inst{10-6} = 0;
882 let Inst{5-0} = 1;
883}
884
Zoran Jovanovic8876be32013-12-25 10:09:27 +0000885class CMov_F_F_FM<bits<5> fmt, bit tf> : StdArch {
Akira Hatanaka6262bbf2012-12-13 01:41:15 +0000886 bits<5> fd;
887 bits<5> fs;
Akira Hatanaka8bce21c2013-07-26 20:51:20 +0000888 bits<3> fcc;
Akira Hatanaka6262bbf2012-12-13 01:41:15 +0000889
890 bits<32> Inst;
891
892 let Inst{31-26} = 0x11;
893 let Inst{25-21} = fmt;
Akira Hatanaka8bce21c2013-07-26 20:51:20 +0000894 let Inst{20-18} = fcc;
Akira Hatanaka6262bbf2012-12-13 01:41:15 +0000895 let Inst{17} = 0;
896 let Inst{16} = tf;
897 let Inst{15-11} = fs;
898 let Inst{10-6} = fd;
899 let Inst{5-0} = 0x11;
900}
Daniel Sanders442f1a12014-04-03 13:21:51 +0000901
902class BARRIER_FM<bits<5> op> : StdArch {
903 bits<32> Inst;
904
905 let Inst{31-26} = 0; // SPECIAL
906 let Inst{25-21} = 0;
907 let Inst{20-16} = 0; // rt = 0
908 let Inst{15-11} = 0; // rd = 0
909 let Inst{10-6} = op; // Operation
910 let Inst{5-0} = 0; // SLL
911}
Daniel Sanders8dcb1162014-05-08 11:51:18 +0000912
Daniel Sanderse6198bf2014-06-24 13:00:32 +0000913class SDBBP_FM : StdArch {
914 bits<20> code_;
915
916 bits<32> Inst;
917
918 let Inst{31-26} = 0b011100; // SPECIAL2
919 let Inst{25-6} = code_;
920 let Inst{5-0} = 0b111111; // SDBBP
921}
922
Matheus Almeida595fcab2014-06-11 15:05:56 +0000923class JR_HB_FM<bits<6> op> : StdArch{
924 bits<5> rs;
925
926 bits<32> Inst;
927
928 let Inst{31-26} = 0; // SPECIAL
929 let Inst{25-21} = rs;
930 let Inst{20-11} = 0;
931 let Inst{10} = 1;
932 let Inst{9-6} = 0;
933 let Inst{5-0} = op;
934}
935
936class JALR_HB_FM<bits<6> op> : StdArch {
937 bits<5> rd;
938 bits<5> rs;
939
940 bits<32> Inst;
941
942 let Inst{31-26} = 0; // SPECIAL
943 let Inst{25-21} = rs;
944 let Inst{20-16} = 0;
945 let Inst{15-11} = rd;
946 let Inst{10} = 1;
947 let Inst{9-6} = 0;
948 let Inst{5-0} = op;
949}
950
Daniel Sanders8dcb1162014-05-08 11:51:18 +0000951class COP0_TLB_FM<bits<6> op> : StdArch {
952 bits<32> Inst;
953
954 let Inst{31-26} = 0x10; // COP0
955 let Inst{25} = 1; // CO
956 let Inst{24-6} = 0;
957 let Inst{5-0} = op; // Operation
958}
Daniel Sandersc171f652014-06-13 13:15:59 +0000959
960class CACHEOP_FM<bits<6> op> : StdArch {
961 bits<21> addr;
962 bits<5> hint;
963 bits<5> base = addr{20-16};
964 bits<16> offset = addr{15-0};
965
966 bits<32> Inst;
967
968 let Inst{31-26} = op;
969 let Inst{25-21} = base;
970 let Inst{20-16} = hint;
971 let Inst{15-0} = offset;
972}