| Ulrich Weigand | 9e3577f | 2013-05-06 16:17:29 +0000 | [diff] [blame] | 1 | ; Test 64-bit subtraction in which the second operand is variable. |
| 2 | ; |
| 3 | ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s |
| 4 | |
| 5 | ; Check SGR. |
| 6 | define i64 @f1(i64 %a, i64 %b) { |
| 7 | ; CHECK: f1: |
| 8 | ; CHECK: sgr %r2, %r3 |
| 9 | ; CHECK: br %r14 |
| 10 | %sub = sub i64 %a, %b |
| 11 | ret i64 %sub |
| 12 | } |
| 13 | |
| 14 | ; Check SG with no displacement. |
| 15 | define i64 @f2(i64 %a, i64 *%src) { |
| 16 | ; CHECK: f2: |
| 17 | ; CHECK: sg %r2, 0(%r3) |
| 18 | ; CHECK: br %r14 |
| 19 | %b = load i64 *%src |
| 20 | %sub = sub i64 %a, %b |
| 21 | ret i64 %sub |
| 22 | } |
| 23 | |
| 24 | ; Check the high end of the aligned SG range. |
| 25 | define i64 @f3(i64 %a, i64 *%src) { |
| 26 | ; CHECK: f3: |
| 27 | ; CHECK: sg %r2, 524280(%r3) |
| 28 | ; CHECK: br %r14 |
| 29 | %ptr = getelementptr i64 *%src, i64 65535 |
| 30 | %b = load i64 *%ptr |
| 31 | %sub = sub i64 %a, %b |
| 32 | ret i64 %sub |
| 33 | } |
| 34 | |
| 35 | ; Check the next doubleword up, which needs separate address logic. |
| 36 | ; Other sequences besides this one would be OK. |
| 37 | define i64 @f4(i64 %a, i64 *%src) { |
| 38 | ; CHECK: f4: |
| 39 | ; CHECK: agfi %r3, 524288 |
| 40 | ; CHECK: sg %r2, 0(%r3) |
| 41 | ; CHECK: br %r14 |
| 42 | %ptr = getelementptr i64 *%src, i64 65536 |
| 43 | %b = load i64 *%ptr |
| 44 | %sub = sub i64 %a, %b |
| 45 | ret i64 %sub |
| 46 | } |
| 47 | |
| 48 | ; Check the high end of the negative aligned SG range. |
| 49 | define i64 @f5(i64 %a, i64 *%src) { |
| 50 | ; CHECK: f5: |
| 51 | ; CHECK: sg %r2, -8(%r3) |
| 52 | ; CHECK: br %r14 |
| 53 | %ptr = getelementptr i64 *%src, i64 -1 |
| 54 | %b = load i64 *%ptr |
| 55 | %sub = sub i64 %a, %b |
| 56 | ret i64 %sub |
| 57 | } |
| 58 | |
| 59 | ; Check the low end of the SG range. |
| 60 | define i64 @f6(i64 %a, i64 *%src) { |
| 61 | ; CHECK: f6: |
| 62 | ; CHECK: sg %r2, -524288(%r3) |
| 63 | ; CHECK: br %r14 |
| 64 | %ptr = getelementptr i64 *%src, i64 -65536 |
| 65 | %b = load i64 *%ptr |
| 66 | %sub = sub i64 %a, %b |
| 67 | ret i64 %sub |
| 68 | } |
| 69 | |
| 70 | ; Check the next doubleword down, which needs separate address logic. |
| 71 | ; Other sequences besides this one would be OK. |
| 72 | define i64 @f7(i64 %a, i64 *%src) { |
| 73 | ; CHECK: f7: |
| 74 | ; CHECK: agfi %r3, -524296 |
| 75 | ; CHECK: sg %r2, 0(%r3) |
| 76 | ; CHECK: br %r14 |
| 77 | %ptr = getelementptr i64 *%src, i64 -65537 |
| 78 | %b = load i64 *%ptr |
| 79 | %sub = sub i64 %a, %b |
| 80 | ret i64 %sub |
| 81 | } |
| 82 | |
| 83 | ; Check that SG allows an index. |
| 84 | define i64 @f8(i64 %a, i64 %src, i64 %index) { |
| 85 | ; CHECK: f8: |
| 86 | ; CHECK: sg %r2, 524280({{%r4,%r3|%r3,%r4}}) |
| 87 | ; CHECK: br %r14 |
| 88 | %add1 = add i64 %src, %index |
| 89 | %add2 = add i64 %add1, 524280 |
| 90 | %ptr = inttoptr i64 %add2 to i64 * |
| 91 | %b = load i64 *%ptr |
| 92 | %sub = sub i64 %a, %b |
| 93 | ret i64 %sub |
| 94 | } |