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Dan Gohman10e730a2015-06-29 23:51:55 +00001//===-- WebAssemblyTargetTransformInfo.cpp - WebAssembly-specific TTI -----===//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Dan Gohman10e730a2015-06-29 23:51:55 +00006//
7//===----------------------------------------------------------------------===//
8///
9/// \file
Adrian Prantl5f8f34e42018-05-01 15:54:18 +000010/// This file defines the WebAssembly-specific TargetTransformInfo
Dan Gohman10e730a2015-06-29 23:51:55 +000011/// implementation.
12///
13//===----------------------------------------------------------------------===//
14
15#include "WebAssemblyTargetTransformInfo.h"
David Blaikieb3bde2e2017-11-17 01:07:10 +000016#include "llvm/CodeGen/CostTable.h"
Dan Gohman10e730a2015-06-29 23:51:55 +000017#include "llvm/Support/Debug.h"
Dan Gohman10e730a2015-06-29 23:51:55 +000018using namespace llvm;
19
20#define DEBUG_TYPE "wasmtti"
21
22TargetTransformInfo::PopcntSupportKind
Dan Gohman01612f62015-08-24 16:51:46 +000023WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
Dan Gohman10e730a2015-06-29 23:51:55 +000024 assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
Dan Gohman01612f62015-08-24 16:51:46 +000025 return TargetTransformInfo::PSK_FastHardware;
26}
Dan Gohman73d7a552016-05-23 22:47:07 +000027
28unsigned WebAssemblyTTIImpl::getNumberOfRegisters(bool Vector) {
29 unsigned Result = BaseT::getNumberOfRegisters(Vector);
30
31 // For SIMD, use at least 16 registers, as a rough guess.
32 if (Vector)
33 Result = std::max(Result, 16u);
34
35 return Result;
36}
37
Daniel Neilsonc0112ae2017-06-12 14:22:21 +000038unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) const {
Dan Gohman73d7a552016-05-23 22:47:07 +000039 if (Vector && getST()->hasSIMD128())
40 return 128;
41
42 return 64;
43}
44
45unsigned WebAssemblyTTIImpl::getArithmeticInstrCost(
46 unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
47 TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
Mohammed Agabaria2c96c432017-01-11 08:23:37 +000048 TTI::OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args) {
Dan Gohman73d7a552016-05-23 22:47:07 +000049
50 unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
51 Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
52
Heejin Ahn18c56a02019-02-04 19:13:39 +000053 if (auto *VTy = dyn_cast<VectorType>(Ty)) {
Dan Gohman73d7a552016-05-23 22:47:07 +000054 switch (Opcode) {
55 case Instruction::LShr:
56 case Instruction::AShr:
57 case Instruction::Shl:
58 // SIMD128's shifts currently only accept a scalar shift count. For each
59 // element, we'll need to extract, op, insert. The following is a rough
60 // approxmation.
61 if (Opd2Info != TTI::OK_UniformValue &&
62 Opd2Info != TTI::OK_UniformConstantValue)
63 Cost = VTy->getNumElements() *
64 (TargetTransformInfo::TCC_Basic +
65 getArithmeticInstrCost(Opcode, VTy->getElementType()) +
66 TargetTransformInfo::TCC_Basic);
67 break;
68 }
69 }
70 return Cost;
71}
72
73unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
74 unsigned Index) {
75 unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
76
77 // SIMD128's insert/extract currently only take constant indices.
78 if (Index == -1u)
79 return Cost + 25 * TargetTransformInfo::TCC_Expensive;
80
81 return Cost;
82}