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gerrit-public.fairphone.software / toolchain / llvm-project / 188ed9d56ecda032cbfd051d51cf2ec07c9e4f9d / . / llvm / lib / Target / ARM / ARMISelLowering.h
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Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef ARMISELLOWERING_H
16#define ARMISELLOWERING_H
17
Craig Topper188ed9d2012-03-17 07:33:42 +0000[diff] [blame^]18#include "ARM.h"
Rafael Espindolafa0df552007-11-05 23:12:20 +0000[diff] [blame]19#include "ARMSubtarget.h"
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]20#include "llvm/Target/TargetLowering.h"
Evan Chengdf907f42010-07-23 22:39:59 +0000[diff] [blame]21#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]22#include "llvm/CodeGen/FastISel.h"
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]23#include "llvm/CodeGen/SelectionDAG.h"
Bob Wilsona4c22902009-04-17 19:07:39 +0000[diff] [blame]24#include "llvm/CodeGen/CallingConvLower.h"
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]25#include <vector>
26
27namespace llvm {
28 class ARMConstantPoolValue;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]29
30 namespace ARMISD {
31 // ARM Specific DAG Nodes
32 enum NodeType {
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]33 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohmaned1cf1a2008-09-23 18:42:32 +0000[diff] [blame]34 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]35
36 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
37 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Cheng2f2435d2011-01-21 18:55:51 +0000[diff] [blame]38 WrapperDYN, // WrapperDYN - A wrapper node for TargetGlobalAddress in
39 // DYN mode.
Evan Chengdfce83c2011-01-17 08:03:18 +0000[diff] [blame]40 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
41 // PIC mode.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]42 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]43
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]44 CALL, // Function call.
Evan Chengc3c949b42007-06-19 21:05:09 +0000[diff] [blame]45 CALL_PRED, // Function call that's predicable.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]46 CALL_NOLINK, // Function call with branch not branch-and-link.
47 tCALL, // Thumb function call.
48 BRCOND, // Conditional branch.
49 BR_JT, // Jumptable branch.
Evan Chengc6d70ae2009-07-29 02:18:14 +0000[diff] [blame]50 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]51 RET_FLAG, // Return with a flag operand.
52
53 PIC_ADD, // Add with a PC operand and a PIC label.
54
55 CMP, // ARM compare instructions.
David Goodwindbf11ba2009-06-29 15:33:01 +0000[diff] [blame]56 CMPZ, // ARM compare that sets only Z flag.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]57 CMPFP, // ARM VFP compare instruction, sets FPSCR.
58 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
59 FMSTAT, // ARM fmstat instruction.
Evan Chenge87681c2012-02-23 01:19:06 +0000[diff] [blame]60
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]61 CMOV, // ARM conditional move instructions.
Evan Chenge87681c2012-02-23 01:19:06 +0000[diff] [blame]62 CAND, // ARM conditional and instructions.
63 COR, // ARM conditional or instructions.
64 CXOR, // ARM conditional xor instructions.
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]65
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]66 BCC_i64,
67
Jim Grosbach8546ec92010-01-18 19:58:49 +0000[diff] [blame]68 RBIT, // ARM bitreverse instruction
69
Bob Wilsone4191e72010-03-19 22:51:32 +0000[diff] [blame]70 FTOSI, // FP to sint within a FP register.
71 FTOUI, // FP to uint within a FP register.
72 SITOF, // sint to FP within a FP register.
73 UITOF, // uint to FP within a FP register.
74
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]75 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
76 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
77 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]78
Evan Chenge8916542011-08-30 01:34:54 +0000[diff] [blame]79 ADDC, // Add with carry
80 ADDE, // Add using carry
81 SUBC, // Sub with carry
82 SUBE, // Sub using carry
83
Jim Grosbachd7cf55c2009-11-09 00:11:35 +0000[diff] [blame]84 VMOVRRD, // double to two gprs.
85 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +0000[diff] [blame]86
Jim Grosbachbbdc5d22010-10-19 23:27:08 +0000[diff] [blame]87 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
88 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Jim Grosbachaeca45d2009-05-12 23:59:14 +0000[diff] [blame]89
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]90 TC_RETURN, // Tail call return pseudo.
91
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]92 THREAD_POINTER,
93
Evan Chengb972e562009-08-07 00:34:42 +0000[diff] [blame]94 DYN_ALLOC, // Dynamic allocation on the stack.
95
Bob Wilson7ed59712010-10-30 00:54:37 +0000[diff] [blame]96 MEMBARRIER, // Memory barrier (DMB)
97 MEMBARRIER_MCR, // Memory barrier (MCR)
Evan Cheng8740ee32010-11-03 06:34:55 +0000[diff] [blame]98
99 PRELOAD, // Preload
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]100
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]101 VCEQ, // Vector compare equal.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]102 VCEQZ, // Vector compare equal to zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]103 VCGE, // Vector compare greater than or equal.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]104 VCGEZ, // Vector compare greater than or equal to zero.
105 VCLEZ, // Vector compare less than or equal to zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]106 VCGEU, // Vector compare unsigned greater than or equal.
107 VCGT, // Vector compare greater than.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]108 VCGTZ, // Vector compare greater than zero.
109 VCLTZ, // Vector compare less than zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]110 VCGTU, // Vector compare unsigned greater than.
111 VTST, // Vector test bits.
112
113 // Vector shift by immediate:
114 VSHL, // ...left
115 VSHRs, // ...right (signed)
116 VSHRu, // ...right (unsigned)
117 VSHLLs, // ...left long (signed)
118 VSHLLu, // ...left long (unsigned)
119 VSHLLi, // ...left long (with maximum shift count)
120 VSHRN, // ...right narrow
121
122 // Vector rounding shift by immediate:
123 VRSHRs, // ...right (signed)
124 VRSHRu, // ...right (unsigned)
125 VRSHRN, // ...right narrow
126
127 // Vector saturating shift by immediate:
128 VQSHLs, // ...left (signed)
129 VQSHLu, // ...left (unsigned)
130 VQSHLsu, // ...left (signed to unsigned)
131 VQSHRNs, // ...right narrow (signed)
132 VQSHRNu, // ...right narrow (unsigned)
133 VQSHRNsu, // ...right narrow (signed to unsigned)
134
135 // Vector saturating rounding shift by immediate:
136 VQRSHRNs, // ...right narrow (signed)
137 VQRSHRNu, // ...right narrow (unsigned)
138 VQRSHRNsu, // ...right narrow (signed to unsigned)
139
140 // Vector shift and insert:
141 VSLI, // ...left
142 VSRI, // ...right
143
144 // Vector get lane (VMOV scalar to ARM core register)
145 // (These are used for 8- and 16-bit element types only.)
146 VGETLANEu, // zero-extend vector extract element
147 VGETLANEs, // sign-extend vector extract element
148
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]149 // Vector move immediate and move negated immediate:
Bob Wilsona3f19012010-07-13 21:16:48 +0000[diff] [blame]150 VMOVIMM,
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]151 VMVNIMM,
152
Evan Cheng7ca4b6e2011-11-15 02:12:34 +0000[diff] [blame]153 // Vector move f32 immediate:
154 VMOVFPIMM,
155
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]156 // Vector duplicate:
Bob Wilsoneb54d512009-08-14 05:13:08 +0000[diff] [blame]157 VDUP,
Bob Wilsoncce31f62009-08-14 05:08:32 +0000[diff] [blame]158 VDUPLANE,
Bob Wilsonf45dee32009-08-04 00:36:16 +0000[diff] [blame]159
Bob Wilsonea3a4022009-08-12 22:31:50 +0000[diff] [blame]160 // Vector shuffles:
Bob Wilson32cd8552009-08-19 17:03:43 +0000[diff] [blame]161 VEXT, // extract
Bob Wilsonea3a4022009-08-12 22:31:50 +0000[diff] [blame]162 VREV64, // reverse elements within 64-bit doublewords
163 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov9a232f42009-08-21 12:41:24 +0000[diff] [blame]164 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsona7062312009-08-21 20:54:19 +0000[diff] [blame]165 VZIP, // zip (interleave)
166 VUZP, // unzip (deinterleave)
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000[diff] [blame]167 VTRN, // transpose
Bill Wendlinge1fd78f2011-03-14 23:02:38 +0000[diff] [blame]168 VTBL1, // 1-register shuffle with mask
169 VTBL2, // 2-register shuffle with mask
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000[diff] [blame]170
Bob Wilson38ab35a2010-09-01 23:50:19 +0000[diff] [blame]171 // Vector multiply long:
172 VMULLs, // ...signed
173 VMULLu, // ...unsigned
174
Bob Wilsond8a9a042010-06-04 00:04:02 +0000[diff] [blame]175 // Operands of the standard BUILD_VECTOR node are not legalized, which
176 // is fine if BUILD_VECTORs are always lowered to shuffles or other
177 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
178 // operands need to be legalized. Define an ARM-specific version of
179 // BUILD_VECTOR for this purpose.
180 BUILD_VECTOR,
181
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000[diff] [blame]182 // Floating-point max and min:
183 FMAX,
Jim Grosbach11013ed2010-07-16 23:05:05 +0000[diff] [blame]184 FMIN,
185
186 // Bit-field insert
Owen Anderson07473072010-11-03 22:44:51 +0000[diff] [blame]187 BFI,
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]188
Owen Anderson07473072010-11-03 22:44:51 +0000[diff] [blame]189 // Vector OR with immediate
Owen Anderson30c48922010-11-05 19:27:46 +0000[diff] [blame]190 VORRIMM,
191 // Vector AND with NOT of immediate
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]192 VBICIMM,
193
Cameron Zwarich53dd03d2011-03-30 23:01:21 +0000[diff] [blame]194 // Vector bitwise select
195 VBSL,
196
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]197 // Vector load N-element structure to all lanes:
198 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
199 VLD3DUP,
Bob Wilson06fce872011-02-07 17:43:21 +0000[diff] [blame]200 VLD4DUP,
201
202 // NEON loads with post-increment base updates:
203 VLD1_UPD,
204 VLD2_UPD,
205 VLD3_UPD,
206 VLD4_UPD,
207 VLD2LN_UPD,
208 VLD3LN_UPD,
209 VLD4LN_UPD,
210 VLD2DUP_UPD,
211 VLD3DUP_UPD,
212 VLD4DUP_UPD,
213
214 // NEON stores with post-increment base updates:
215 VST1_UPD,
216 VST2_UPD,
217 VST3_UPD,
218 VST4_UPD,
219 VST2LN_UPD,
220 VST3LN_UPD,
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]221 VST4LN_UPD,
222
223 // 64-bit atomic ops (value split into two registers)
224 ATOMADD64_DAG,
225 ATOMSUB64_DAG,
226 ATOMOR64_DAG,
227 ATOMXOR64_DAG,
228 ATOMAND64_DAG,
229 ATOMNAND64_DAG,
230 ATOMSWAP64_DAG,
231 ATOMCMPXCHG64_DAG
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]232 };
233 }
234
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]235 /// Define some predicates that are used for node matching.
236 namespace ARM {
Jim Grosbach11013ed2010-07-16 23:05:05 +0000[diff] [blame]237 bool isBitFieldInvertedMask(unsigned v);
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]238 }
239
Bob Wilsondd0e2362009-05-20 16:30:25 +0000[diff] [blame]240 //===--------------------------------------------------------------------===//
Dale Johannesen8447d342007-03-20 00:30:56 +0000[diff] [blame]241 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]242
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]243 class ARMTargetLowering : public TargetLowering {
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]244 public:
Dan Gohman5f6a9da52007-08-02 21:21:54 +0000[diff] [blame]245 explicit ARMTargetLowering(TargetMachine &TM);
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]246
Jim Grosbach8d3ba732010-07-19 17:20:38 +0000[diff] [blame]247 virtual unsigned getJumpTableEncoding(void) const;
248
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]249 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
Duncan Sands6ed40142008-12-01 11:39:25 +0000[diff] [blame]250
251 /// ReplaceNodeResults - Replace the results of node with an illegal result
252 /// type with new values built out of custom code.
253 ///
254 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]255 SelectionDAG &DAG) const;
Duncan Sands6ed40142008-12-01 11:39:25 +0000[diff] [blame]256
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]257 virtual const char *getTargetNodeName(unsigned Opcode) const;
258
Duncan Sandsf2641e12011-09-06 19:07:46 +0000[diff] [blame]259 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
260 virtual EVT getSetCCResultType(EVT VT) const;
261
Dan Gohman25c16532010-05-01 00:01:06 +0000[diff] [blame]262 virtual MachineBasicBlock *
263 EmitInstrWithCustomInserter(MachineInstr *MI,
264 MachineBasicBlock *MBB) const;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]265
Evan Chenge6fba772011-08-30 19:09:48 +0000[diff] [blame]266 virtual void
267 AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
268
Evan Chengf863e3f2011-07-13 00:42:17 +0000[diff] [blame]269 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
Evan Chengd42641c2011-02-02 01:06:55 +0000[diff] [blame]270 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
271
272 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const;
273
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000[diff] [blame]274 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
275 /// unaligned memory accesses. of the specified type.
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000[diff] [blame]276 virtual bool allowsUnalignedMemoryAccesses(EVT VT) const;
277
Lang Hames9929c422011-11-02 22:52:45 +0000[diff] [blame]278 virtual EVT getOptimalMemOpType(uint64_t Size,
279 unsigned DstAlign, unsigned SrcAlign,
Lang Hames1f4603d2011-11-02 23:37:04 +0000[diff] [blame]280 bool IsZeroVal,
Lang Hames9929c422011-11-02 22:52:45 +0000[diff] [blame]281 bool MemcpyStrSrc,
282 MachineFunction &MF) const;
283
Chris Lattner1eb94d92007-03-30 23:15:24 +0000[diff] [blame]284 /// isLegalAddressingMode - Return true if the addressing mode represented
285 /// by AM is legal for this target, for a load/store of the specified type.
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]286 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
Evan Chengdc49a8d2009-08-14 20:09:37 +0000[diff] [blame]287 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]288
Evan Cheng3d3c24a2009-11-11 19:05:52 +0000[diff] [blame]289 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach84511e12010-06-02 21:53:11 +0000[diff] [blame]290 /// icmp immediate, that is the target has icmp instructions which can
291 /// compare a register against the immediate without having to materialize
292 /// the immediate into a register.
Evan Cheng15b80e42009-11-12 07:13:11 +0000[diff] [blame]293 virtual bool isLegalICmpImmediate(int64_t Imm) const;
Evan Cheng3d3c24a2009-11-11 19:05:52 +0000[diff] [blame]294
Dan Gohman6136e942011-05-03 00:46:49 +0000[diff] [blame]295 /// isLegalAddImmediate - Return true if the specified immediate is legal
296 /// add immediate, that is the target has add instructions which can
297 /// add a register and the immediate without having to materialize
298 /// the immediate into a register.
299 virtual bool isLegalAddImmediate(int64_t Imm) const;
300
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]301 /// getPreIndexedAddressParts - returns true by value, base pointer and
302 /// offset pointer and addressing mode by reference if the node's address
303 /// can be legally represented as pre-indexed load / store address.
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]304 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
305 SDValue &Offset,
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]306 ISD::MemIndexedMode &AM,
Dan Gohman02b93132009-01-15 16:29:45 +0000[diff] [blame]307 SelectionDAG &DAG) const;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]308
309 /// getPostIndexedAddressParts - returns true by value, base pointer and
310 /// offset pointer and addressing mode by reference if this node can be
311 /// combined with a load / store to form a post-indexed load / store.
312 virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]313 SDValue &Base, SDValue &Offset,
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]314 ISD::MemIndexedMode &AM,
Dan Gohman02b93132009-01-15 16:29:45 +0000[diff] [blame]315 SelectionDAG &DAG) const;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]316
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]317 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
Dan Gohmane1d9ee62008-02-13 22:28:48 +0000[diff] [blame]318 const APInt &Mask,
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]319 APInt &KnownZero,
Dan Gohmanf990faf2008-02-13 00:35:47 +0000[diff] [blame]320 APInt &KnownOne,
Dan Gohman309d3d52007-06-22 14:59:07 +0000[diff] [blame]321 const SelectionDAG &DAG,
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]322 unsigned Depth) const;
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000[diff] [blame]323
324
Evan Cheng078b0b02011-01-08 01:24:27 +0000[diff] [blame]325 virtual bool ExpandInlineAsm(CallInst *CI) const;
326
Chris Lattnerd6855142007-03-25 02:14:49 +0000[diff] [blame]327 ConstraintType getConstraintType(const std::string &Constraint) const;
John Thompsone8360b72010-10-29 17:29:13 +0000[diff] [blame]328
329 /// Examine constraint string and operand type and determine a weight value.
330 /// The operand object must already have been set up with the operand type.
331 ConstraintWeight getSingleConstraintMatchWeight(
332 AsmOperandInfo &info, const char *constraint) const;
333
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]334 std::pair<unsigned, const TargetRegisterClass*>
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]335 getRegForInlineAsmConstraint(const std::string &Constraint,
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]336 EVT VT) const;
Rafael Espindolafa0df552007-11-05 23:12:20 +0000[diff] [blame]337
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +0000[diff] [blame]338 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
339 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
340 /// true it means one of the asm constraint of the inline asm instruction
341 /// being processed is 'm'.
342 virtual void LowerAsmOperandForConstraint(SDValue Op,
Eric Christopherde9399b2011-06-02 23:16:42 +0000[diff] [blame]343 std::string &Constraint,
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +0000[diff] [blame]344 std::vector<SDValue> &Ops,
345 SelectionDAG &DAG) const;
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]346
Dan Gohman4df9d9c2010-05-11 16:21:03 +0000[diff] [blame]347 const ARMSubtarget* getSubtarget() const {
Dan Gohman544ab2c2008-04-12 04:36:06 +0000[diff] [blame]348 return Subtarget;
Rafael Espindolafa0df552007-11-05 23:12:20 +0000[diff] [blame]349 }
350
Evan Cheng4cad68e2010-05-15 02:18:07 +0000[diff] [blame]351 /// getRegClassFor - Return the register class that should be used for the
352 /// specified value type.
Craig Topper760b1342012-02-22 05:59:10 +0000[diff] [blame]353 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
Evan Cheng4cad68e2010-05-15 02:18:07 +0000[diff] [blame]354
Anton Korobeynikov19edda02010-07-24 21:52:08 +0000[diff] [blame]355 /// getMaximalGlobalOffset - Returns the maximal possible offset which can
356 /// be used for loads / stores from the global.
357 virtual unsigned getMaximalGlobalOffset() const;
358
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]359 /// createFastISel - This method returns a target specific FastISel object,
360 /// or null if the target does not support "fast" ISel.
361 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
362
Evan Cheng4401f882010-05-20 23:26:43 +0000[diff] [blame]363 Sched::Preference getSchedulingPreference(SDNode *N) const;
364
Anton Korobeynikovc32e99e2009-08-21 12:40:07 +0000[diff] [blame]365 bool isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const;
Anton Korobeynikov29a44df2009-09-23 19:04:09 +0000[diff] [blame]366 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
Evan Cheng4a609f3c2009-10-28 01:44:26 +0000[diff] [blame]367
368 /// isFPImmLegal - Returns true if the target can instruction select the
369 /// specified FP immediate natively. If false, the legalizer will
370 /// materialize the FP immediate as a load from a constant pool.
371 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
372
Bob Wilson5549d492010-09-21 17:56:22 +0000[diff] [blame]373 virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
374 const CallInst &I,
375 unsigned Intrinsic) const;
Evan Cheng10f99a32010-07-19 22:15:08 +0000[diff] [blame]376 protected:
Evan Chenga77f3d32010-07-21 06:09:07 +0000[diff] [blame]377 std::pair<const TargetRegisterClass*, uint8_t>
378 findRepresentativeClass(EVT VT) const;
Evan Cheng10f99a32010-07-19 22:15:08 +0000[diff] [blame]379
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]380 private:
381 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
382 /// make the right decision when generating code for different targets.
383 const ARMSubtarget *Subtarget;
384
Evan Chengdf907f42010-07-23 22:39:59 +0000[diff] [blame]385 const TargetRegisterInfo *RegInfo;
386
Evan Chengbf407072010-09-10 01:29:16 +0000[diff] [blame]387 const InstrItineraryData *Itins;
388
Bob Wilson844d6c82009-07-13 18:11:36 +0000[diff] [blame]389 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]390 ///
391 unsigned ARMPCLabelIndex;
392
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]393 void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT);
394 void addDRTypeForNEON(EVT VT);
395 void addQRTypeForNEON(EVT VT);
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]396
397 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]398 void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]399 SDValue Chain, SDValue &Arg,
400 RegsToPassVector &RegsToPass,
401 CCValAssign &VA, CCValAssign &NextVA,
402 SDValue &StackPtr,
403 SmallVector<SDValue, 8> &MemOpChains,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]404 ISD::ArgFlagsTy Flags) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]405 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]406 SDValue &Root, SelectionDAG &DAG,
407 DebugLoc dl) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]408
Jim Grosbach84511e12010-06-02 21:53:11 +0000[diff] [blame]409 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
410 bool isVarArg) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]411 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
412 DebugLoc dl, SelectionDAG &DAG,
413 const CCValAssign &VA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]414 ISD::ArgFlagsTy Flags) const;
Jim Grosbachc98892f2010-05-26 20:22:18 +0000[diff] [blame]415 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbachbd9485d2010-05-22 01:06:18 +0000[diff] [blame]416 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha570d052010-02-08 23:22:00 +0000[diff] [blame]417 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]418 const ARMSubtarget *Subtarget) const;
419 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
420 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
421 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
422 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]423 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]424 SelectionDAG &DAG) const;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]425 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]426 SelectionDAG &DAG) const;
427 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
428 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
Bill Wendling6a981312010-08-11 08:43:16 +0000[diff] [blame]429 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]430 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
431 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng25f93642010-07-08 02:08:50 +0000[diff] [blame]432 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng168ced92010-05-22 01:47:14 +0000[diff] [blame]433 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]434 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]435 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
436 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Nate Begemanb69b1822010-08-03 21:31:55 +0000[diff] [blame]437 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
Lang Hamesc35ee8b2012-03-15 18:49:02 +0000[diff] [blame]438 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
439 const ARMSubtarget *ST) const;
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]440 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
Bob Wilson6f2b8962011-01-07 21:37:30 +0000[diff] [blame]441 const ARMSubtarget *ST) const;
442
443 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola18a831d2007-10-19 14:35:17 +0000[diff] [blame]444
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]445 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000[diff] [blame]446 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]447 const SmallVectorImpl<ISD::InputArg> &Ins,
448 DebugLoc dl, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]449 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]450
451 virtual SDValue
452 LowerFormalArguments(SDValue Chain,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000[diff] [blame]453 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]454 const SmallVectorImpl<ISD::InputArg> &Ins,
455 DebugLoc dl, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]456 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]457
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000[diff] [blame]458 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
459 DebugLoc dl, SDValue &Chain, unsigned ArgOffset)
460 const;
461
462 void computeRegArea(CCState &CCInfo, MachineFunction &MF,
463 unsigned &VARegSize, unsigned &VARegSaveSize) const;
464
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]465 virtual SDValue
Evan Cheng6f36a082010-02-02 23:55:14 +0000[diff] [blame]466 LowerCall(SDValue Chain, SDValue Callee,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000[diff] [blame]467 CallingConv::ID CallConv, bool isVarArg,
Evan Cheng65f9d192012-02-28 18:51:51 +0000[diff] [blame]468 bool doesNotRet, bool &isTailCall,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]469 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +0000[diff] [blame]470 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]471 const SmallVectorImpl<ISD::InputArg> &Ins,
472 DebugLoc dl, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]473 SmallVectorImpl<SDValue> &InVals) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]474
Stuart Hastings67c5c3e2011-02-28 17:17:53 +0000[diff] [blame]475 /// HandleByVal - Target-specific cleanup for ByVal support.
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000[diff] [blame]476 virtual void HandleByVal(CCState *, unsigned &) const;
Stuart Hastings67c5c3e2011-02-28 17:17:53 +0000[diff] [blame]477
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]478 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
479 /// for tail call optimization. Targets which want to do tail call
480 /// optimization should implement this function.
481 bool IsEligibleForTailCallOptimization(SDValue Callee,
482 CallingConv::ID CalleeCC,
483 bool isVarArg,
484 bool isCalleeStructRet,
485 bool isCallerStructRet,
486 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +0000[diff] [blame]487 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]488 const SmallVectorImpl<ISD::InputArg> &Ins,
489 SelectionDAG& DAG) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]490 virtual SDValue
491 LowerReturn(SDValue Chain,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000[diff] [blame]492 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]493 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +0000[diff] [blame]494 const SmallVectorImpl<SDValue> &OutVals,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]495 DebugLoc dl, SelectionDAG &DAG) const;
Evan Cheng15b80e42009-11-12 07:13:11 +0000[diff] [blame]496
Evan Chengd4b08732010-11-30 23:55:39 +0000[diff] [blame]497 virtual bool isUsedByReturnOnly(SDNode *N) const;
498
Evan Cheng0663f232011-03-21 01:19:09 +0000[diff] [blame]499 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
500
Evan Cheng15b80e42009-11-12 07:13:11 +0000[diff] [blame]501 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]502 SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
503 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
504 SelectionDAG &DAG, DebugLoc dl) const;
Bob Wilson45acbd02011-03-08 01:17:20 +0000[diff] [blame]505 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]506
507 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000[diff] [blame]508
Jim Grosbach8f9a3ac2009-12-12 01:40:06 +0000[diff] [blame]509 MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
510 MachineBasicBlock *BB,
511 unsigned Size) const;
512 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
513 MachineBasicBlock *BB,
514 unsigned Size,
515 unsigned BinOpcode) const;
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]516 MachineBasicBlock *EmitAtomicBinary64(MachineInstr *MI,
517 MachineBasicBlock *BB,
518 unsigned Op1,
519 unsigned Op2,
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]520 bool NeedsCarry = false,
521 bool IsCmpxchg = false) const;
Jim Grosbachd4b733e2011-04-26 19:44:18 +0000[diff] [blame]522 MachineBasicBlock * EmitAtomicBinaryMinMax(MachineInstr *MI,
523 MachineBasicBlock *BB,
524 unsigned Size,
525 bool signExtend,
526 ARMCC::CondCodes Cond) const;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000[diff] [blame]527
Bill Wendling030b58e2011-10-06 22:18:16 +0000[diff] [blame]528 void SetupEntryBlockForSjLj(MachineInstr *MI,
529 MachineBasicBlock *MBB,
530 MachineBasicBlock *DispatchBB, int FI) const;
531
Bill Wendling374ee192011-10-03 21:25:38 +0000[diff] [blame]532 MachineBasicBlock *EmitSjLjDispatchBlock(MachineInstr *MI,
533 MachineBasicBlock *MBB) const;
534
Andrew Trick0ed57782011-04-23 03:55:32 +0000[diff] [blame]535 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]536 };
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]537
Owen Andersona4076922010-11-05 21:57:54 +0000[diff] [blame]538 enum NEONModImmType {
539 VMOVModImm,
540 VMVNModImm,
541 OtherModImm
542 };
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]543
544
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]545 namespace ARM {
546 FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
547 }
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]548}
549
550#endif // ARMISELLOWERING_H