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gerrit-public.fairphone.software / toolchain / llvm-project / 1b6dacbb86d9c426bd3cb009a446e7da441fd97c / . / llvm / test / CodeGen / PowerPC / atomic-2.ll
blob: 1857d5d697e65ad94f40ab110be9d701c2b254dc [file] [log] [blame]
Eli Friedman4d5532a2011-07-18 21:23:42 +0000[diff] [blame]1; RUN: llc < %s -march=ppc64 | FileCheck %s
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]2; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s
3; RUN: llc < %s -march=ppc64 -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-P8U
Evan Cheng5102bd92008-04-19 02:30:38 +0000[diff] [blame]4
Chris Lattner80ed9dc2011-06-18 06:05:24 +0000[diff] [blame]5define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]6; CHECK-LABEL: exchange_and_add:
Eli Friedman4d5532a2011-07-18 21:23:42 +0000[diff] [blame]7; CHECK: ldarx
Eli Friedman6fb0c1e2011-09-26 21:30:17 +0000[diff] [blame]8 %tmp = atomicrmw add i64* %mem, i64 %val monotonic
Eli Friedman4d5532a2011-07-18 21:23:42 +0000[diff] [blame]9; CHECK: stdcx.
Chris Lattner80ed9dc2011-06-18 06:05:24 +0000[diff] [blame]10 ret i64 %tmp
Evan Cheng5102bd92008-04-19 02:30:38 +0000[diff] [blame]11}
12
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]13define i8 @exchange_and_add8(i8* %mem, i8 %val) nounwind {
14; CHECK-LABEL: exchange_and_add8:
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]15; CHECK-P8U: lbarx
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]16 %tmp = atomicrmw add i8* %mem, i8 %val monotonic
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]17; CHECK-P8U: stbcx.
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]18 ret i8 %tmp
19}
20
21define i16 @exchange_and_add16(i16* %mem, i16 %val) nounwind {
22; CHECK-LABEL: exchange_and_add16:
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]23; CHECK-P8U: lharx
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]24 %tmp = atomicrmw add i16* %mem, i16 %val monotonic
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]25; CHECK-P8U: sthcx.
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]26 ret i16 %tmp
27}
28
Chris Lattner80ed9dc2011-06-18 06:05:24 +0000[diff] [blame]29define i64 @exchange_and_cmp(i64* %mem) nounwind {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]30; CHECK-LABEL: exchange_and_cmp:
Eli Friedman4d5532a2011-07-18 21:23:42 +0000[diff] [blame]31; CHECK: ldarx
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]32 %tmppair = cmpxchg i64* %mem, i64 0, i64 1 monotonic monotonic
33 %tmp = extractvalue { i64, i1 } %tmppair, 0
Eli Friedman4d5532a2011-07-18 21:23:42 +0000[diff] [blame]34; CHECK: stdcx.
35; CHECK: stdcx.
Chris Lattner80ed9dc2011-06-18 06:05:24 +0000[diff] [blame]36 ret i64 %tmp
Evan Cheng5102bd92008-04-19 02:30:38 +0000[diff] [blame]37}
38
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]39define i8 @exchange_and_cmp8(i8* %mem) nounwind {
40; CHECK-LABEL: exchange_and_cmp8:
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]41; CHECK-P8U: lbarx
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]42 %tmppair = cmpxchg i8* %mem, i8 0, i8 1 monotonic monotonic
43 %tmp = extractvalue { i8, i1 } %tmppair, 0
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]44; CHECK-P8U: stbcx.
45; CHECK-P8U: stbcx.
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]46 ret i8 %tmp
47}
48
49define i16 @exchange_and_cmp16(i16* %mem) nounwind {
50; CHECK-LABEL: exchange_and_cmp16:
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]51; CHECK-P8U: lharx
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]52 %tmppair = cmpxchg i16* %mem, i16 0, i16 1 monotonic monotonic
53 %tmp = extractvalue { i16, i1 } %tmppair, 0
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]54; CHECK-P8U: sthcx.
55; CHECK-P8U: sthcx.
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]56 ret i16 %tmp
57}
58
Chris Lattner80ed9dc2011-06-18 06:05:24 +0000[diff] [blame]59define i64 @exchange(i64* %mem, i64 %val) nounwind {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]60; CHECK-LABEL: exchange:
Eli Friedman4d5532a2011-07-18 21:23:42 +0000[diff] [blame]61; CHECK: ldarx
Eli Friedman6fb0c1e2011-09-26 21:30:17 +0000[diff] [blame]62 %tmp = atomicrmw xchg i64* %mem, i64 1 monotonic
Eli Friedman4d5532a2011-07-18 21:23:42 +0000[diff] [blame]63; CHECK: stdcx.
Chris Lattner80ed9dc2011-06-18 06:05:24 +0000[diff] [blame]64 ret i64 %tmp
Evan Cheng5102bd92008-04-19 02:30:38 +0000[diff] [blame]65}
Hal Finkel1b5ff082012-12-25 17:22:53 +0000[diff] [blame]66
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]67define i8 @exchange8(i8* %mem, i8 %val) nounwind {
68; CHECK-LABEL: exchange8:
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]69; CHECK-P8U: lbarx
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]70 %tmp = atomicrmw xchg i8* %mem, i8 1 monotonic
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]71; CHECK-P8U: stbcx.
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]72 ret i8 %tmp
73}
74
75define i16 @exchange16(i16* %mem, i16 %val) nounwind {
76; CHECK-LABEL: exchange16:
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]77; CHECK-P8U: lharx
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]78 %tmp = atomicrmw xchg i16* %mem, i16 1 monotonic
Hal Finkel58f5f9c2015-04-11 13:40:36 +0000[diff] [blame]79; CHECK-P8U: sthcx.
Nemanja Ivanovic0adf26b2015-03-10 20:51:07 +0000[diff] [blame]80 ret i16 %tmp
81}
82
Hal Finkel1b5ff082012-12-25 17:22:53 +0000[diff] [blame]83define void @atomic_store(i64* %mem, i64 %val) nounwind {
84entry:
85; CHECK: @atomic_store
86 store atomic i64 %val, i64* %mem release, align 64
Hal Finkel7c5cb062015-04-23 18:30:38 +0000[diff] [blame]87; CHECK: lwsync
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]88; CHECK-NOT: stdcx
89; CHECK: std
Hal Finkel1b5ff082012-12-25 17:22:53 +0000[diff] [blame]90 ret void
91}
92
93define i64 @atomic_load(i64* %mem) nounwind {
94entry:
95; CHECK: @atomic_load
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]96 %tmp = load atomic i64, i64* %mem acquire, align 64
Robin Morissete1ca44b2014-10-02 22:27:07 +0000[diff] [blame]97; CHECK-NOT: ldarx
98; CHECK: ld
Hal Finkel7c5cb062015-04-23 18:30:38 +0000[diff] [blame]99; CHECK: lwsync
Hal Finkel1b5ff082012-12-25 17:22:53 +0000[diff] [blame]100 ret i64 %tmp
101}
102