blob: d3f430f21f3af2afc2cca93b6cf219622d48b580 [file] [log] [blame]
Renato Golind93295e2014-04-02 09:03:43 +00001//===-- ARMOptimizeBarriersPass - two DMBs without a memory access in between,
2//removed one -===//
3//
4// The LLVM Compiler Infrastructure
5//
6// This file is distributed under the University of Illinois Open Source
7// License. See LICENSE.TXT for details.
8//
9//===------------------------------------------------------------------------------------------===//
10
Renato Golind93295e2014-04-02 09:03:43 +000011#include "ARM.h"
Renato Golind93295e2014-04-02 09:03:43 +000012#include "ARMInstrInfo.h"
Chandler Carruthd9903882015-01-14 11:23:27 +000013#include "ARMMachineFunctionInfo.h"
Renato Golind93295e2014-04-02 09:03:43 +000014#include "llvm/ADT/Statistic.h"
15#include "llvm/CodeGen/MachineFunctionPass.h"
16using namespace llvm;
17
Chandler Carruth84e68b22014-04-22 02:41:26 +000018#define DEBUG_TYPE "double barriers"
19
Renato Golind93295e2014-04-02 09:03:43 +000020STATISTIC(NumDMBsRemoved, "Number of DMBs removed");
21
22namespace {
23class ARMOptimizeBarriersPass : public MachineFunctionPass {
24public:
25 static char ID;
26 ARMOptimizeBarriersPass() : MachineFunctionPass(ID) {}
27
Craig Topper9d74a5a2014-04-29 07:58:41 +000028 bool runOnMachineFunction(MachineFunction &Fn) override;
Renato Golind93295e2014-04-02 09:03:43 +000029
Derek Schuff1dbf7a52016-04-04 17:09:25 +000030 MachineFunctionProperties getRequiredProperties() const override {
31 return MachineFunctionProperties().set(
32 MachineFunctionProperties::Property::AllVRegsAllocated);
33 }
34
Craig Topper9d74a5a2014-04-29 07:58:41 +000035 const char *getPassName() const override {
Renato Golind93295e2014-04-02 09:03:43 +000036 return "optimise barriers pass";
37 }
Renato Golind93295e2014-04-02 09:03:43 +000038};
39char ARMOptimizeBarriersPass::ID = 0;
Alexander Kornienkof00654e2015-06-23 09:49:53 +000040}
Renato Golind93295e2014-04-02 09:03:43 +000041
42// Returns whether the instruction can safely move past a DMB instruction
43// The current implementation allows this iif MI does not have any possible
44// memory access
45static bool CanMovePastDMB(const MachineInstr *MI) {
46 return !(MI->mayLoad() ||
47 MI->mayStore() ||
48 MI->hasUnmodeledSideEffects() ||
49 MI->isCall() ||
50 MI->isReturn());
51}
52
53bool ARMOptimizeBarriersPass::runOnMachineFunction(MachineFunction &MF) {
54 // Vector to store the DMBs we will remove after the first iteration
55 std::vector<MachineInstr *> ToRemove;
56 // DMBType is the Imm value of the first operand. It determines whether it's a
57 // DMB ish, dmb sy, dmb osh, etc
58 int64_t DMBType = -1;
59
60 // Find a dmb. If we can move it until the next dmb, tag the second one for
61 // removal
62 for (auto &MBB : MF) {
63 // Will be true when we have seen a DMB, and not seen any instruction since
64 // that cannot move past a DMB
65 bool IsRemovableNextDMB = false;
66 for (auto &MI : MBB) {
67 if (MI.getOpcode() == ARM::DMB) {
68 if (IsRemovableNextDMB) {
69 // If the Imm of this DMB is the same as that of the last DMB, we can
70 // tag this second DMB for removal
71 if (MI.getOperand(0).getImm() == DMBType) {
72 ToRemove.push_back(&MI);
73 } else {
74 // If it has a different DMBType, we cannot remove it, but will scan
75 // for the next DMB, recording this DMB's type as last seen DMB type
76 DMBType = MI.getOperand(0).getImm();
77 }
78 } else {
79 // After we see a DMB, a next one is removable
80 IsRemovableNextDMB = true;
81 DMBType = MI.getOperand(0).getImm();
82 }
83 } else if (!CanMovePastDMB(&MI)) {
84 // If we find an instruction unable to pass past a DMB, a next DMB is
85 // not removable
86 IsRemovableNextDMB = false;
87 }
88 }
89 }
90 // Remove the tagged DMB
91 for (auto MI : ToRemove) {
92 MI->eraseFromParent();
93 ++NumDMBsRemoved;
94 }
95
96 return NumDMBsRemoved > 0;
97}
98
99/// createARMOptimizeBarriersPass - Returns an instance of the remove double
100/// barriers
101/// pass.
102FunctionPass *llvm::createARMOptimizeBarriersPass() {
103 return new ARMOptimizeBarriersPass();
104}