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Tom Stellard347ac792015-06-26 21:15:07 +00001//===-- AMDGPUBaseInfo.h - Top level definitions for AMDGPU -----*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10#ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11#define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
12
13#include "AMDKernelCodeT.h"
Nicolai Haehnledf3a20c2016-04-06 19:40:20 +000014#include "llvm/IR/CallingConv.h"
Tom Stellard347ac792015-06-26 21:15:07 +000015
16namespace llvm {
17
18class FeatureBitset;
Tom Stellardac00eb52015-12-15 16:26:16 +000019class Function;
Tom Stellarde3b5aea2015-12-02 17:00:42 +000020class GlobalValue;
Tom Stellarde135ffd2015-09-25 21:41:28 +000021class MCContext;
Sam Kolton1eeb11b2016-09-09 14:44:04 +000022class MCInstrDesc;
23class MCRegisterInfo;
Tom Stellarde135ffd2015-09-25 21:41:28 +000024class MCSection;
Tom Stellard2b65ed32015-12-21 18:44:27 +000025class MCSubtargetInfo;
Tom Stellard347ac792015-06-26 21:15:07 +000026
27namespace AMDGPU {
28
29struct IsaVersion {
30 unsigned Major;
31 unsigned Minor;
32 unsigned Stepping;
33};
34
35IsaVersion getIsaVersion(const FeatureBitset &Features);
Tom Stellardff7416b2015-06-26 21:58:31 +000036void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
37 const FeatureBitset &Features);
Tom Stellarde135ffd2015-09-25 21:41:28 +000038MCSection *getHSATextSection(MCContext &Ctx);
Tom Stellard347ac792015-06-26 21:15:07 +000039
Tom Stellard00f2f912015-12-02 19:47:57 +000040MCSection *getHSADataGlobalAgentSection(MCContext &Ctx);
41
42MCSection *getHSADataGlobalProgramSection(MCContext &Ctx);
43
Tom Stellard9760f032015-12-03 03:34:32 +000044MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx);
45
Tom Stellarde3b5aea2015-12-02 17:00:42 +000046bool isGroupSegment(const GlobalValue *GV);
Tom Stellard00f2f912015-12-02 19:47:57 +000047bool isGlobalSegment(const GlobalValue *GV);
48bool isReadOnlySegment(const GlobalValue *GV);
Tom Stellarde3b5aea2015-12-02 17:00:42 +000049
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +000050/// \returns Integer value requested using \p F's \p Name attribute.
51///
52/// \returns \p Default if attribute is not present.
53///
54/// \returns \p Default and emits error if requested value cannot be converted
55/// to integer.
Matt Arsenault83002722016-05-12 02:45:18 +000056int getIntegerAttribute(const Function &F, StringRef Name, int Default);
57
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +000058/// \returns A pair of integer values requested using \p F's \p Name attribute
59/// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
60/// is false).
61///
62/// \returns \p Default if attribute is not present.
63///
64/// \returns \p Default and emits error if one of the requested values cannot be
65/// converted to integer, or \p OnlyFirstRequired is false and "second" value is
66/// not present.
67std::pair<int, int> getIntegerPairAttribute(const Function &F,
68 StringRef Name,
69 std::pair<int, int> Default,
70 bool OnlyFirstRequired = false);
71
Marek Olsakfccabaf2016-01-13 11:45:36 +000072unsigned getInitialPSInputAddr(const Function &F);
73
Nicolai Haehnledf3a20c2016-04-06 19:40:20 +000074bool isShader(CallingConv::ID cc);
75bool isCompute(CallingConv::ID cc);
Tom Stellardac00eb52015-12-15 16:26:16 +000076
Tom Stellard2b65ed32015-12-21 18:44:27 +000077bool isSI(const MCSubtargetInfo &STI);
78bool isCI(const MCSubtargetInfo &STI);
79bool isVI(const MCSubtargetInfo &STI);
80
81/// If \p Reg is a pseudo reg, return the correct hardware register given
82/// \p STI otherwise return \p Reg.
83unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
84
Sam Kolton1eeb11b2016-09-09 14:44:04 +000085/// \brief Can this operand also contain immediate values?
86bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
87
88/// \brief Is this floating-point operand?
89bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
90
91/// \brief Does this opearnd support only inlinable literals?
92bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
93
94/// \brief Get size of register operand
95unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
96 unsigned OpNo);
97
98/// \brief Is this literal inlinable
99bool isInlinableLiteral64(int64_t Literal, bool IsVI);
100bool isInlinableLiteral32(int32_t Literal, bool IsVI);
101
Tom Stellard347ac792015-06-26 21:15:07 +0000102} // end namespace AMDGPU
103} // end namespace llvm
104
105#endif