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Tim Northover3b0846e2014-05-24 12:50:23 +00001//===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the AArch64 specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef AArch64SUBTARGET_H
15#define AArch64SUBTARGET_H
16
Eric Christopher29aab7b2014-06-10 17:44:12 +000017#include "AArch64FrameLowering.h"
Eric Christopher841da852014-06-10 23:26:45 +000018#include "AArch64ISelLowering.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +000019#include "AArch64InstrInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +000020#include "AArch64RegisterInfo.h"
Eric Christopherfcb06ca2014-06-10 18:21:53 +000021#include "AArch64SelectionDAGInfo.h"
Eric Christopher6f2a2032014-06-10 18:06:23 +000022#include "llvm/IR/DataLayout.h"
Eric Christopher29aab7b2014-06-10 17:44:12 +000023#include "llvm/Target/TargetSubtargetInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +000024#include <string>
25
26#define GET_SUBTARGETINFO_HEADER
27#include "AArch64GenSubtargetInfo.inc"
28
29namespace llvm {
30class GlobalValue;
31class StringRef;
32
33class AArch64Subtarget : public AArch64GenSubtargetInfo {
34protected:
35 enum ARMProcFamilyEnum {Others, CortexA53, CortexA57, Cyclone};
36
37 /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
38 ARMProcFamilyEnum ARMProcFamily;
39
40 bool HasFPARMv8;
41 bool HasNEON;
42 bool HasCrypto;
43 bool HasCRC;
44
45 // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
46 bool HasZeroCycleRegMove;
47
48 // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
49 bool HasZeroCycleZeroing;
50
51 /// CPUString - String name of used CPU.
52 std::string CPUString;
53
54 /// TargetTriple - What processor and OS we're targeting.
55 Triple TargetTriple;
56
Eric Christopher6f2a2032014-06-10 18:06:23 +000057 const DataLayout DL;
Eric Christopher29aab7b2014-06-10 17:44:12 +000058 AArch64FrameLowering FrameLowering;
Eric Christopherf63bc642014-06-10 22:57:25 +000059 AArch64InstrInfo InstrInfo;
Eric Christopherfcb06ca2014-06-10 18:21:53 +000060 AArch64SelectionDAGInfo TSInfo;
Eric Christopher7c9d4e02014-06-11 00:46:34 +000061 AArch64TargetLowering TLInfo;
62private:
63 /// initializeSubtargetDependencies - Initializes using CPUString and the
64 /// passed in feature string so that we can use initializer lists for
65 /// subtarget initialization.
66 AArch64Subtarget &initializeSubtargetDependencies(StringRef FS);
Eric Christopher29aab7b2014-06-10 17:44:12 +000067
Tim Northover3b0846e2014-05-24 12:50:23 +000068public:
69 /// This constructor initializes the data members to match that
70 /// of the specified triple.
71 AArch64Subtarget(const std::string &TT, const std::string &CPU,
Eric Christopher841da852014-06-10 23:26:45 +000072 const std::string &FS, TargetMachine &TM, bool LittleEndian);
Tim Northover3b0846e2014-05-24 12:50:23 +000073
Eric Christopherfcb06ca2014-06-10 18:21:53 +000074 const AArch64SelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
Eric Christopher29aab7b2014-06-10 17:44:12 +000075 const AArch64FrameLowering *getFrameLowering() const {
76 return &FrameLowering;
77 }
Eric Christopher841da852014-06-10 23:26:45 +000078 const AArch64TargetLowering *getTargetLowering() const {
Eric Christopher7c9d4e02014-06-11 00:46:34 +000079 return &TLInfo;
Eric Christopher841da852014-06-10 23:26:45 +000080 }
Eric Christopherf63bc642014-06-10 22:57:25 +000081 const AArch64InstrInfo *getInstrInfo() const { return &InstrInfo; }
Eric Christopher6f2a2032014-06-10 18:06:23 +000082 const DataLayout *getDataLayout() const { return &DL; }
Tim Northover3b0846e2014-05-24 12:50:23 +000083 bool enableMachineScheduler() const override { return true; }
84
85 bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
86
87 bool hasZeroCycleZeroing() const { return HasZeroCycleZeroing; }
88
89 bool hasFPARMv8() const { return HasFPARMv8; }
90 bool hasNEON() const { return HasNEON; }
91 bool hasCrypto() const { return HasCrypto; }
92 bool hasCRC() const { return HasCRC; }
93
Eric Christopher17254ee2014-06-10 18:11:20 +000094 bool isLittleEndian() const { return DL.isLittleEndian(); }
Tim Northover3b0846e2014-05-24 12:50:23 +000095
96 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
97
98 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
99
100 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
101
102 bool isCyclone() const { return CPUString == "cyclone"; }
103
104 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
105 /// that still makes it profitable to inline the call.
106 unsigned getMaxInlineSizeThreshold() const { return 64; }
107
108 /// ParseSubtargetFeatures - Parses features string setting specified
109 /// subtarget options. Definition of function is auto generated by tblgen.
110 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
111
112 /// ClassifyGlobalReference - Find the target operand flags that describe
113 /// how a global value should be referenced for the current subtarget.
114 unsigned char ClassifyGlobalReference(const GlobalValue *GV,
115 const TargetMachine &TM) const;
116
117 /// This function returns the name of a function which has an interface
118 /// like the non-standard bzero function, if such a function exists on
119 /// the current subtarget and it is considered prefereable over
120 /// memset with zero passed as the second argument. Otherwise it
121 /// returns null.
122 const char *getBZeroEntry() const;
123
124 void overrideSchedPolicy(MachineSchedPolicy &Policy, MachineInstr *begin,
125 MachineInstr *end,
126 unsigned NumRegionInstrs) const override;
127
128 bool enableEarlyIfConversion() const override;
129};
130} // End llvm namespace
131
132#endif // AArch64SUBTARGET_H