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gerrit-public.fairphone.software / toolchain / llvm-project / 220b1c13bf2b80a3273f0062096f23a8978a795a / . / llvm / test / CodeGen / RISCV / select-cc.ll
blob: ddc5983525eeeb33d126a5e40f41f84bd92dcf97 [file] [log] [blame]
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN: | FileCheck -check-prefix=RV32I %s
4
5define i32 @foo(i32 %a, i32 *%b) {
6; RV32I-LABEL: foo:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]7; RV32I: # %bb.0:
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]8; RV32I-NEXT: lw a2, 0(a1)
9; RV32I-NEXT: beq a0, a2, .LBB0_2
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]10; RV32I-NEXT: # %bb.1:
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]11; RV32I-NEXT: addi a0, a2, 0
12; RV32I-NEXT: .LBB0_2:
13; RV32I-NEXT: lw a2, 0(a1)
14; RV32I-NEXT: bne a0, a2, .LBB0_4
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]15; RV32I-NEXT: # %bb.3:
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]16; RV32I-NEXT: addi a0, a2, 0
17; RV32I-NEXT: .LBB0_4:
18; RV32I-NEXT: lw a2, 0(a1)
19; RV32I-NEXT: bltu a2, a0, .LBB0_6
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]20; RV32I-NEXT: # %bb.5:
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]21; RV32I-NEXT: addi a0, a2, 0
22; RV32I-NEXT: .LBB0_6:
23; RV32I-NEXT: lw a2, 0(a1)
24; RV32I-NEXT: bgeu a0, a2, .LBB0_8
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]25; RV32I-NEXT: # %bb.7:
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]26; RV32I-NEXT: addi a0, a2, 0
27; RV32I-NEXT: .LBB0_8:
28; RV32I-NEXT: lw a2, 0(a1)
29; RV32I-NEXT: bltu a0, a2, .LBB0_10
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]30; RV32I-NEXT: # %bb.9:
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]31; RV32I-NEXT: addi a0, a2, 0
32; RV32I-NEXT: .LBB0_10:
33; RV32I-NEXT: lw a2, 0(a1)
34; RV32I-NEXT: bgeu a2, a0, .LBB0_12
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]35; RV32I-NEXT: # %bb.11:
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]36; RV32I-NEXT: addi a0, a2, 0
37; RV32I-NEXT: .LBB0_12:
38; RV32I-NEXT: lw a2, 0(a1)
39; RV32I-NEXT: blt a2, a0, .LBB0_14
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]40; RV32I-NEXT: # %bb.13:
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]41; RV32I-NEXT: addi a0, a2, 0
42; RV32I-NEXT: .LBB0_14:
43; RV32I-NEXT: lw a2, 0(a1)
44; RV32I-NEXT: bge a0, a2, .LBB0_16
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]45; RV32I-NEXT: # %bb.15:
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]46; RV32I-NEXT: addi a0, a2, 0
47; RV32I-NEXT: .LBB0_16:
48; RV32I-NEXT: lw a2, 0(a1)
49; RV32I-NEXT: blt a0, a2, .LBB0_18
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]50; RV32I-NEXT: # %bb.17:
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]51; RV32I-NEXT: addi a0, a2, 0
52; RV32I-NEXT: .LBB0_18:
53; RV32I-NEXT: lw a1, 0(a1)
54; RV32I-NEXT: bge a1, a0, .LBB0_20
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]55; RV32I-NEXT: # %bb.19:
Alex Bradbury65385162017-11-21 07:51:32 +0000[diff] [blame]56; RV32I-NEXT: addi a0, a1, 0
57; RV32I-NEXT: .LBB0_20:
58; RV32I-NEXT: jalr zero, ra, 0
59 %val1 = load volatile i32, i32* %b
60 %tst1 = icmp eq i32 %a, %val1
61 %val2 = select i1 %tst1, i32 %a, i32 %val1
62
63 %val3 = load volatile i32, i32* %b
64 %tst2 = icmp ne i32 %val2, %val3
65 %val4 = select i1 %tst2, i32 %val2, i32 %val3
66
67 %val5 = load volatile i32, i32* %b
68 %tst3 = icmp ugt i32 %val4, %val5
69 %val6 = select i1 %tst3, i32 %val4, i32 %val5
70
71 %val7 = load volatile i32, i32* %b
72 %tst4 = icmp uge i32 %val6, %val7
73 %val8 = select i1 %tst4, i32 %val6, i32 %val7
74
75 %val9 = load volatile i32, i32* %b
76 %tst5 = icmp ult i32 %val8, %val9
77 %val10 = select i1 %tst5, i32 %val8, i32 %val9
78
79 %val11 = load volatile i32, i32* %b
80 %tst6 = icmp ule i32 %val10, %val11
81 %val12 = select i1 %tst6, i32 %val10, i32 %val11
82
83 %val13 = load volatile i32, i32* %b
84 %tst7 = icmp sgt i32 %val12, %val13
85 %val14 = select i1 %tst7, i32 %val12, i32 %val13
86
87 %val15 = load volatile i32, i32* %b
88 %tst8 = icmp sge i32 %val14, %val15
89 %val16 = select i1 %tst8, i32 %val14, i32 %val15
90
91 %val17 = load volatile i32, i32* %b
92 %tst9 = icmp slt i32 %val16, %val17
93 %val18 = select i1 %tst9, i32 %val16, i32 %val17
94
95 %val19 = load volatile i32, i32* %b
96 %tst10 = icmp sle i32 %val18, %val19
97 %val20 = select i1 %tst10, i32 %val18, i32 %val19
98
99 ret i32 %val20
100}