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gerrit-public.fairphone.software / toolchain / llvm-project / 7811430588b390aece10b136fcb3af6d3d8e2722 / . / llvm / test / CodeGen / AArch64 / minmax-of-minmax.ll
blob: a71cc85ee08e1bd0e204206c853adb3679501ab4 [file] [log] [blame]
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
3
4; There are 4 commuted variants (abbc/abcb/bcab/bcba) *
5; 4 predicate variants ([*][lg][te] *
6; 4 min/max flavors (smin/smax/umin/max)
7; = 64 tests
8
9define <4 x i32> @smin_ab_bc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
10; CHECK-LABEL: smin_ab_bc:
11; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]12; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]13; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]14; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]15; CHECK-NEXT: ret
16 %cmp_ab = icmp slt <4 x i32> %a, %b
17 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
18 %cmp_bc = icmp slt <4 x i32> %b, %c
19 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
20 %cmp_ac = icmp slt <4 x i32> %a, %c
21 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
22 ret <4 x i32> %r
23}
24
25define <4 x i32> @smin_ab_cb(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
26; CHECK-LABEL: smin_ab_cb:
27; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]28; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]29; CHECK-NEXT: smin v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]30; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]31; CHECK-NEXT: ret
32 %cmp_ab = icmp slt <4 x i32> %a, %b
33 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
34 %cmp_cb = icmp slt <4 x i32> %c, %b
35 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
36 %cmp_ac = icmp slt <4 x i32> %a, %c
37 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
38 ret <4 x i32> %r
39}
40
41define <4 x i32> @smin_bc_ab(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
42; CHECK-LABEL: smin_bc_ab:
43; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]44; CHECK-NEXT: smin v2.4s, v1.4s, v2.4s
45; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
46; CHECK-NEXT: smin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]47; CHECK-NEXT: ret
48 %cmp_bc = icmp slt <4 x i32> %b, %c
49 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
50 %cmp_ab = icmp slt <4 x i32> %a, %b
51 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
52 %cmp_ca = icmp slt <4 x i32> %c, %a
53 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
54 ret <4 x i32> %r
55}
56
57define <4 x i32> @smin_bc_ba(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
58; CHECK-LABEL: smin_bc_ba:
59; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]60; CHECK-NEXT: smin v2.4s, v1.4s, v2.4s
61; CHECK-NEXT: smin v0.4s, v1.4s, v0.4s
62; CHECK-NEXT: smin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]63; CHECK-NEXT: ret
64 %cmp_bc = icmp slt <4 x i32> %b, %c
65 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
66 %cmp_ba = icmp slt <4 x i32> %b, %a
67 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
68 %cmp_ca = icmp slt <4 x i32> %c, %a
69 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
70 ret <4 x i32> %r
71}
72
73define <4 x i32> @smin_ab_bc_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
74; CHECK-LABEL: smin_ab_bc_swap_pred:
75; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]76; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]77; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]78; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]79; CHECK-NEXT: ret
80 %cmp_ab = icmp slt <4 x i32> %a, %b
81 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
82 %cmp_bc = icmp slt <4 x i32> %b, %c
83 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
84 %cmp_ac = icmp sgt <4 x i32> %c, %a
85 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
86 ret <4 x i32> %r
87}
88
89define <4 x i32> @smin_ab_cb_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
90; CHECK-LABEL: smin_ab_cb_swap_pred:
91; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]92; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]93; CHECK-NEXT: smin v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]94; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]95; CHECK-NEXT: ret
96 %cmp_ab = icmp slt <4 x i32> %a, %b
97 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
98 %cmp_cb = icmp slt <4 x i32> %c, %b
99 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
100 %cmp_ac = icmp sgt <4 x i32> %c, %a
101 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
102 ret <4 x i32> %r
103}
104
105define <4 x i32> @smin_bc_ab_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
106; CHECK-LABEL: smin_bc_ab_swap_pred:
107; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]108; CHECK-NEXT: smin v2.4s, v1.4s, v2.4s
109; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
110; CHECK-NEXT: smin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]111; CHECK-NEXT: ret
112 %cmp_bc = icmp slt <4 x i32> %b, %c
113 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
114 %cmp_ab = icmp slt <4 x i32> %a, %b
115 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
116 %cmp_ca = icmp sgt <4 x i32> %a, %c
117 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
118 ret <4 x i32> %r
119}
120
121define <4 x i32> @smin_bc_ba_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
122; CHECK-LABEL: smin_bc_ba_swap_pred:
123; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]124; CHECK-NEXT: smin v2.4s, v1.4s, v2.4s
125; CHECK-NEXT: smin v0.4s, v1.4s, v0.4s
126; CHECK-NEXT: smin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]127; CHECK-NEXT: ret
128 %cmp_bc = icmp slt <4 x i32> %b, %c
129 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
130 %cmp_ba = icmp slt <4 x i32> %b, %a
131 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
132 %cmp_ca = icmp sgt <4 x i32> %a, %c
133 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
134 ret <4 x i32> %r
135}
136
137define <4 x i32> @smin_ab_bc_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
138; CHECK-LABEL: smin_ab_bc_eq_pred:
139; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]140; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]141; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]142; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]143; CHECK-NEXT: ret
144 %cmp_ab = icmp slt <4 x i32> %a, %b
145 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
146 %cmp_bc = icmp slt <4 x i32> %b, %c
147 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
148 %cmp_ac = icmp sle <4 x i32> %a, %c
149 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
150 ret <4 x i32> %r
151}
152
153define <4 x i32> @smin_ab_cb_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
154; CHECK-LABEL: smin_ab_cb_eq_pred:
155; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]156; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]157; CHECK-NEXT: smin v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]158; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]159; CHECK-NEXT: ret
160 %cmp_ab = icmp slt <4 x i32> %a, %b
161 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
162 %cmp_cb = icmp slt <4 x i32> %c, %b
163 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
164 %cmp_ac = icmp sle <4 x i32> %a, %c
165 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
166 ret <4 x i32> %r
167}
168
169define <4 x i32> @smin_bc_ab_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
170; CHECK-LABEL: smin_bc_ab_eq_pred:
171; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]172; CHECK-NEXT: smin v2.4s, v1.4s, v2.4s
173; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
174; CHECK-NEXT: smin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]175; CHECK-NEXT: ret
176 %cmp_bc = icmp slt <4 x i32> %b, %c
177 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
178 %cmp_ab = icmp slt <4 x i32> %a, %b
179 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
180 %cmp_ca = icmp sle <4 x i32> %c, %a
181 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
182 ret <4 x i32> %r
183}
184
185define <4 x i32> @smin_bc_ba_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
186; CHECK-LABEL: smin_bc_ba_eq_pred:
187; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]188; CHECK-NEXT: smin v2.4s, v1.4s, v2.4s
189; CHECK-NEXT: smin v0.4s, v1.4s, v0.4s
190; CHECK-NEXT: smin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]191; CHECK-NEXT: ret
192 %cmp_bc = icmp slt <4 x i32> %b, %c
193 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
194 %cmp_ba = icmp slt <4 x i32> %b, %a
195 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
196 %cmp_ca = icmp sle <4 x i32> %c, %a
197 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
198 ret <4 x i32> %r
199}
200
201define <4 x i32> @smin_ab_bc_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
202; CHECK-LABEL: smin_ab_bc_eq_swap_pred:
203; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]204; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]205; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]206; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]207; CHECK-NEXT: ret
208 %cmp_ab = icmp slt <4 x i32> %a, %b
209 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
210 %cmp_bc = icmp slt <4 x i32> %b, %c
211 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
212 %cmp_ac = icmp sge <4 x i32> %c, %a
213 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
214 ret <4 x i32> %r
215}
216
217define <4 x i32> @smin_ab_cb_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
218; CHECK-LABEL: smin_ab_cb_eq_swap_pred:
219; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]220; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]221; CHECK-NEXT: smin v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]222; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]223; CHECK-NEXT: ret
224 %cmp_ab = icmp slt <4 x i32> %a, %b
225 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
226 %cmp_cb = icmp slt <4 x i32> %c, %b
227 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
228 %cmp_ac = icmp sge <4 x i32> %c, %a
229 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
230 ret <4 x i32> %r
231}
232
233define <4 x i32> @smin_bc_ab_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
234; CHECK-LABEL: smin_bc_ab_eq_swap_pred:
235; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]236; CHECK-NEXT: smin v2.4s, v1.4s, v2.4s
237; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
238; CHECK-NEXT: smin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]239; CHECK-NEXT: ret
240 %cmp_bc = icmp slt <4 x i32> %b, %c
241 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
242 %cmp_ab = icmp slt <4 x i32> %a, %b
243 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
244 %cmp_ca = icmp sge <4 x i32> %a, %c
245 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
246 ret <4 x i32> %r
247}
248
249define <4 x i32> @smin_bc_ba_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
250; CHECK-LABEL: smin_bc_ba_eq_swap_pred:
251; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]252; CHECK-NEXT: smin v2.4s, v1.4s, v2.4s
253; CHECK-NEXT: smin v0.4s, v1.4s, v0.4s
254; CHECK-NEXT: smin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]255; CHECK-NEXT: ret
256 %cmp_bc = icmp slt <4 x i32> %b, %c
257 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
258 %cmp_ba = icmp slt <4 x i32> %b, %a
259 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
260 %cmp_ca = icmp sge <4 x i32> %a, %c
261 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
262 ret <4 x i32> %r
263}
264
265define <4 x i32> @smax_ab_bc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
266; CHECK-LABEL: smax_ab_bc:
267; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]268; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]269; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]270; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]271; CHECK-NEXT: ret
272 %cmp_ab = icmp sgt <4 x i32> %a, %b
273 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
274 %cmp_bc = icmp sgt <4 x i32> %b, %c
275 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
276 %cmp_ac = icmp sgt <4 x i32> %a, %c
277 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
278 ret <4 x i32> %r
279}
280
281define <4 x i32> @smax_ab_cb(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
282; CHECK-LABEL: smax_ab_cb:
283; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]284; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]285; CHECK-NEXT: smax v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]286; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]287; CHECK-NEXT: ret
288 %cmp_ab = icmp sgt <4 x i32> %a, %b
289 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
290 %cmp_cb = icmp sgt <4 x i32> %c, %b
291 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
292 %cmp_ac = icmp sgt <4 x i32> %a, %c
293 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
294 ret <4 x i32> %r
295}
296
297define <4 x i32> @smax_bc_ab(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
298; CHECK-LABEL: smax_bc_ab:
299; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]300; CHECK-NEXT: smax v2.4s, v1.4s, v2.4s
301; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
302; CHECK-NEXT: smax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]303; CHECK-NEXT: ret
304 %cmp_bc = icmp sgt <4 x i32> %b, %c
305 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
306 %cmp_ab = icmp sgt <4 x i32> %a, %b
307 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
308 %cmp_ca = icmp sgt <4 x i32> %c, %a
309 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
310 ret <4 x i32> %r
311}
312
313define <4 x i32> @smax_bc_ba(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
314; CHECK-LABEL: smax_bc_ba:
315; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]316; CHECK-NEXT: smax v2.4s, v1.4s, v2.4s
317; CHECK-NEXT: smax v0.4s, v1.4s, v0.4s
318; CHECK-NEXT: smax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]319; CHECK-NEXT: ret
320 %cmp_bc = icmp sgt <4 x i32> %b, %c
321 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
322 %cmp_ba = icmp sgt <4 x i32> %b, %a
323 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
324 %cmp_ca = icmp sgt <4 x i32> %c, %a
325 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
326 ret <4 x i32> %r
327}
328
329define <4 x i32> @smax_ab_bc_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
330; CHECK-LABEL: smax_ab_bc_swap_pred:
331; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]332; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]333; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]334; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]335; CHECK-NEXT: ret
336 %cmp_ab = icmp sgt <4 x i32> %a, %b
337 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
338 %cmp_bc = icmp sgt <4 x i32> %b, %c
339 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
340 %cmp_ac = icmp slt <4 x i32> %c, %a
341 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
342 ret <4 x i32> %r
343}
344
345define <4 x i32> @smax_ab_cb_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
346; CHECK-LABEL: smax_ab_cb_swap_pred:
347; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]348; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]349; CHECK-NEXT: smax v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]350; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]351; CHECK-NEXT: ret
352 %cmp_ab = icmp sgt <4 x i32> %a, %b
353 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
354 %cmp_cb = icmp sgt <4 x i32> %c, %b
355 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
356 %cmp_ac = icmp slt <4 x i32> %c, %a
357 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
358 ret <4 x i32> %r
359}
360
361define <4 x i32> @smax_bc_ab_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
362; CHECK-LABEL: smax_bc_ab_swap_pred:
363; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]364; CHECK-NEXT: smax v2.4s, v1.4s, v2.4s
365; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
366; CHECK-NEXT: smax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]367; CHECK-NEXT: ret
368 %cmp_bc = icmp sgt <4 x i32> %b, %c
369 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
370 %cmp_ab = icmp sgt <4 x i32> %a, %b
371 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
372 %cmp_ca = icmp slt <4 x i32> %a, %c
373 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
374 ret <4 x i32> %r
375}
376
377define <4 x i32> @smax_bc_ba_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
378; CHECK-LABEL: smax_bc_ba_swap_pred:
379; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]380; CHECK-NEXT: smax v2.4s, v1.4s, v2.4s
381; CHECK-NEXT: smax v0.4s, v1.4s, v0.4s
382; CHECK-NEXT: smax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]383; CHECK-NEXT: ret
384 %cmp_bc = icmp sgt <4 x i32> %b, %c
385 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
386 %cmp_ba = icmp sgt <4 x i32> %b, %a
387 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
388 %cmp_ca = icmp slt <4 x i32> %a, %c
389 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
390 ret <4 x i32> %r
391}
392
393define <4 x i32> @smax_ab_bc_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
394; CHECK-LABEL: smax_ab_bc_eq_pred:
395; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]396; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]397; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]398; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]399; CHECK-NEXT: ret
400 %cmp_ab = icmp sgt <4 x i32> %a, %b
401 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
402 %cmp_bc = icmp sgt <4 x i32> %b, %c
403 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
404 %cmp_ac = icmp sge <4 x i32> %a, %c
405 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
406 ret <4 x i32> %r
407}
408
409define <4 x i32> @smax_ab_cb_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
410; CHECK-LABEL: smax_ab_cb_eq_pred:
411; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]412; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]413; CHECK-NEXT: smax v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]414; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]415; CHECK-NEXT: ret
416 %cmp_ab = icmp sgt <4 x i32> %a, %b
417 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
418 %cmp_cb = icmp sgt <4 x i32> %c, %b
419 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
420 %cmp_ac = icmp sge <4 x i32> %a, %c
421 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
422 ret <4 x i32> %r
423}
424
425define <4 x i32> @smax_bc_ab_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
426; CHECK-LABEL: smax_bc_ab_eq_pred:
427; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]428; CHECK-NEXT: smax v2.4s, v1.4s, v2.4s
429; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
430; CHECK-NEXT: smax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]431; CHECK-NEXT: ret
432 %cmp_bc = icmp sgt <4 x i32> %b, %c
433 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
434 %cmp_ab = icmp sgt <4 x i32> %a, %b
435 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
436 %cmp_ca = icmp sge <4 x i32> %c, %a
437 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
438 ret <4 x i32> %r
439}
440
441define <4 x i32> @smax_bc_ba_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
442; CHECK-LABEL: smax_bc_ba_eq_pred:
443; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]444; CHECK-NEXT: smax v2.4s, v1.4s, v2.4s
445; CHECK-NEXT: smax v0.4s, v1.4s, v0.4s
446; CHECK-NEXT: smax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]447; CHECK-NEXT: ret
448 %cmp_bc = icmp sgt <4 x i32> %b, %c
449 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
450 %cmp_ba = icmp sgt <4 x i32> %b, %a
451 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
452 %cmp_ca = icmp sge <4 x i32> %c, %a
453 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
454 ret <4 x i32> %r
455}
456
457define <4 x i32> @smax_ab_bc_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
458; CHECK-LABEL: smax_ab_bc_eq_swap_pred:
459; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]460; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]461; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]462; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]463; CHECK-NEXT: ret
464 %cmp_ab = icmp sgt <4 x i32> %a, %b
465 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
466 %cmp_bc = icmp sgt <4 x i32> %b, %c
467 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
468 %cmp_ac = icmp sle <4 x i32> %c, %a
469 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
470 ret <4 x i32> %r
471}
472
473define <4 x i32> @smax_ab_cb_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
474; CHECK-LABEL: smax_ab_cb_eq_swap_pred:
475; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]476; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]477; CHECK-NEXT: smax v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]478; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]479; CHECK-NEXT: ret
480 %cmp_ab = icmp sgt <4 x i32> %a, %b
481 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
482 %cmp_cb = icmp sgt <4 x i32> %c, %b
483 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
484 %cmp_ac = icmp sle <4 x i32> %c, %a
485 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
486 ret <4 x i32> %r
487}
488
489define <4 x i32> @smax_bc_ab_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
490; CHECK-LABEL: smax_bc_ab_eq_swap_pred:
491; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]492; CHECK-NEXT: smax v2.4s, v1.4s, v2.4s
493; CHECK-NEXT: smax v0.4s, v0.4s, v1.4s
494; CHECK-NEXT: smax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]495; CHECK-NEXT: ret
496 %cmp_bc = icmp sgt <4 x i32> %b, %c
497 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
498 %cmp_ab = icmp sgt <4 x i32> %a, %b
499 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
500 %cmp_ca = icmp sle <4 x i32> %a, %c
501 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
502 ret <4 x i32> %r
503}
504
505define <4 x i32> @smax_bc_ba_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
506; CHECK-LABEL: smax_bc_ba_eq_swap_pred:
507; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]508; CHECK-NEXT: smax v2.4s, v1.4s, v2.4s
509; CHECK-NEXT: smax v0.4s, v1.4s, v0.4s
510; CHECK-NEXT: smax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]511; CHECK-NEXT: ret
512 %cmp_bc = icmp sgt <4 x i32> %b, %c
513 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
514 %cmp_ba = icmp sgt <4 x i32> %b, %a
515 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
516 %cmp_ca = icmp sle <4 x i32> %a, %c
517 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
518 ret <4 x i32> %r
519}
520
521define <4 x i32> @umin_ab_bc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
522; CHECK-LABEL: umin_ab_bc:
523; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]524; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]525; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]526; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]527; CHECK-NEXT: ret
528 %cmp_ab = icmp ult <4 x i32> %a, %b
529 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
530 %cmp_bc = icmp ult <4 x i32> %b, %c
531 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
532 %cmp_ac = icmp ult <4 x i32> %a, %c
533 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
534 ret <4 x i32> %r
535}
536
537define <4 x i32> @umin_ab_cb(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
538; CHECK-LABEL: umin_ab_cb:
539; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]540; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]541; CHECK-NEXT: umin v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]542; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]543; CHECK-NEXT: ret
544 %cmp_ab = icmp ult <4 x i32> %a, %b
545 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
546 %cmp_cb = icmp ult <4 x i32> %c, %b
547 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
548 %cmp_ac = icmp ult <4 x i32> %a, %c
549 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
550 ret <4 x i32> %r
551}
552
553define <4 x i32> @umin_bc_ab(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
554; CHECK-LABEL: umin_bc_ab:
555; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]556; CHECK-NEXT: umin v2.4s, v1.4s, v2.4s
557; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
558; CHECK-NEXT: umin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]559; CHECK-NEXT: ret
560 %cmp_bc = icmp ult <4 x i32> %b, %c
561 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
562 %cmp_ab = icmp ult <4 x i32> %a, %b
563 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
564 %cmp_ca = icmp ult <4 x i32> %c, %a
565 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
566 ret <4 x i32> %r
567}
568
569define <4 x i32> @umin_bc_ba(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
570; CHECK-LABEL: umin_bc_ba:
571; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]572; CHECK-NEXT: umin v2.4s, v1.4s, v2.4s
573; CHECK-NEXT: umin v0.4s, v1.4s, v0.4s
574; CHECK-NEXT: umin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]575; CHECK-NEXT: ret
576 %cmp_bc = icmp ult <4 x i32> %b, %c
577 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
578 %cmp_ba = icmp ult <4 x i32> %b, %a
579 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
580 %cmp_ca = icmp ult <4 x i32> %c, %a
581 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
582 ret <4 x i32> %r
583}
584
585define <4 x i32> @umin_ab_bc_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
586; CHECK-LABEL: umin_ab_bc_swap_pred:
587; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]588; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]589; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]590; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]591; CHECK-NEXT: ret
592 %cmp_ab = icmp ult <4 x i32> %a, %b
593 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
594 %cmp_bc = icmp ult <4 x i32> %b, %c
595 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
596 %cmp_ac = icmp ugt <4 x i32> %c, %a
597 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
598 ret <4 x i32> %r
599}
600
601define <4 x i32> @umin_ab_cb_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
602; CHECK-LABEL: umin_ab_cb_swap_pred:
603; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]604; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]605; CHECK-NEXT: umin v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]606; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]607; CHECK-NEXT: ret
608 %cmp_ab = icmp ult <4 x i32> %a, %b
609 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
610 %cmp_cb = icmp ult <4 x i32> %c, %b
611 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
612 %cmp_ac = icmp ugt <4 x i32> %c, %a
613 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
614 ret <4 x i32> %r
615}
616
617define <4 x i32> @umin_bc_ab_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
618; CHECK-LABEL: umin_bc_ab_swap_pred:
619; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]620; CHECK-NEXT: umin v2.4s, v1.4s, v2.4s
621; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
622; CHECK-NEXT: umin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]623; CHECK-NEXT: ret
624 %cmp_bc = icmp ult <4 x i32> %b, %c
625 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
626 %cmp_ab = icmp ult <4 x i32> %a, %b
627 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
628 %cmp_ca = icmp ugt <4 x i32> %a, %c
629 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
630 ret <4 x i32> %r
631}
632
633define <4 x i32> @umin_bc_ba_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
634; CHECK-LABEL: umin_bc_ba_swap_pred:
635; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]636; CHECK-NEXT: umin v2.4s, v1.4s, v2.4s
637; CHECK-NEXT: umin v0.4s, v1.4s, v0.4s
638; CHECK-NEXT: umin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]639; CHECK-NEXT: ret
640 %cmp_bc = icmp ult <4 x i32> %b, %c
641 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
642 %cmp_ba = icmp ult <4 x i32> %b, %a
643 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
644 %cmp_ca = icmp ugt <4 x i32> %a, %c
645 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
646 ret <4 x i32> %r
647}
648
649define <4 x i32> @umin_ab_bc_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
650; CHECK-LABEL: umin_ab_bc_eq_pred:
651; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]652; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]653; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]654; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]655; CHECK-NEXT: ret
656 %cmp_ab = icmp ult <4 x i32> %a, %b
657 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
658 %cmp_bc = icmp ult <4 x i32> %b, %c
659 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
660 %cmp_ac = icmp ule <4 x i32> %a, %c
661 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
662 ret <4 x i32> %r
663}
664
665define <4 x i32> @umin_ab_cb_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
666; CHECK-LABEL: umin_ab_cb_eq_pred:
667; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]668; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]669; CHECK-NEXT: umin v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]670; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]671; CHECK-NEXT: ret
672 %cmp_ab = icmp ult <4 x i32> %a, %b
673 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
674 %cmp_cb = icmp ult <4 x i32> %c, %b
675 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
676 %cmp_ac = icmp ule <4 x i32> %a, %c
677 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
678 ret <4 x i32> %r
679}
680
681define <4 x i32> @umin_bc_ab_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
682; CHECK-LABEL: umin_bc_ab_eq_pred:
683; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]684; CHECK-NEXT: umin v2.4s, v1.4s, v2.4s
685; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
686; CHECK-NEXT: umin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]687; CHECK-NEXT: ret
688 %cmp_bc = icmp ult <4 x i32> %b, %c
689 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
690 %cmp_ab = icmp ult <4 x i32> %a, %b
691 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
692 %cmp_ca = icmp ule <4 x i32> %c, %a
693 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
694 ret <4 x i32> %r
695}
696
697define <4 x i32> @umin_bc_ba_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
698; CHECK-LABEL: umin_bc_ba_eq_pred:
699; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]700; CHECK-NEXT: umin v2.4s, v1.4s, v2.4s
701; CHECK-NEXT: umin v0.4s, v1.4s, v0.4s
702; CHECK-NEXT: umin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]703; CHECK-NEXT: ret
704 %cmp_bc = icmp ult <4 x i32> %b, %c
705 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
706 %cmp_ba = icmp ult <4 x i32> %b, %a
707 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
708 %cmp_ca = icmp ule <4 x i32> %c, %a
709 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
710 ret <4 x i32> %r
711}
712
713define <4 x i32> @umin_ab_bc_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
714; CHECK-LABEL: umin_ab_bc_eq_swap_pred:
715; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]716; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]717; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]718; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]719; CHECK-NEXT: ret
720 %cmp_ab = icmp ult <4 x i32> %a, %b
721 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
722 %cmp_bc = icmp ult <4 x i32> %b, %c
723 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
724 %cmp_ac = icmp uge <4 x i32> %c, %a
725 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
726 ret <4 x i32> %r
727}
728
729define <4 x i32> @umin_ab_cb_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
730; CHECK-LABEL: umin_ab_cb_eq_swap_pred:
731; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]732; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]733; CHECK-NEXT: umin v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]734; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]735; CHECK-NEXT: ret
736 %cmp_ab = icmp ult <4 x i32> %a, %b
737 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
738 %cmp_cb = icmp ult <4 x i32> %c, %b
739 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
740 %cmp_ac = icmp uge <4 x i32> %c, %a
741 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
742 ret <4 x i32> %r
743}
744
745define <4 x i32> @umin_bc_ab_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
746; CHECK-LABEL: umin_bc_ab_eq_swap_pred:
747; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]748; CHECK-NEXT: umin v2.4s, v1.4s, v2.4s
749; CHECK-NEXT: umin v0.4s, v0.4s, v1.4s
750; CHECK-NEXT: umin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]751; CHECK-NEXT: ret
752 %cmp_bc = icmp ult <4 x i32> %b, %c
753 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
754 %cmp_ab = icmp ult <4 x i32> %a, %b
755 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
756 %cmp_ca = icmp uge <4 x i32> %a, %c
757 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
758 ret <4 x i32> %r
759}
760
761define <4 x i32> @umin_bc_ba_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
762; CHECK-LABEL: umin_bc_ba_eq_swap_pred:
763; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]764; CHECK-NEXT: umin v2.4s, v1.4s, v2.4s
765; CHECK-NEXT: umin v0.4s, v1.4s, v0.4s
766; CHECK-NEXT: umin v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]767; CHECK-NEXT: ret
768 %cmp_bc = icmp ult <4 x i32> %b, %c
769 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
770 %cmp_ba = icmp ult <4 x i32> %b, %a
771 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
772 %cmp_ca = icmp uge <4 x i32> %a, %c
773 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
774 ret <4 x i32> %r
775}
776
777define <4 x i32> @umax_ab_bc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
778; CHECK-LABEL: umax_ab_bc:
779; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]780; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]781; CHECK-NEXT: umax v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]782; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]783; CHECK-NEXT: ret
784 %cmp_ab = icmp ugt <4 x i32> %a, %b
785 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
786 %cmp_bc = icmp ugt <4 x i32> %b, %c
787 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
788 %cmp_ac = icmp ugt <4 x i32> %a, %c
789 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
790 ret <4 x i32> %r
791}
792
793define <4 x i32> @umax_ab_cb(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
794; CHECK-LABEL: umax_ab_cb:
795; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]796; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]797; CHECK-NEXT: umax v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]798; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]799; CHECK-NEXT: ret
800 %cmp_ab = icmp ugt <4 x i32> %a, %b
801 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
802 %cmp_cb = icmp ugt <4 x i32> %c, %b
803 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
804 %cmp_ac = icmp ugt <4 x i32> %a, %c
805 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
806 ret <4 x i32> %r
807}
808
809define <4 x i32> @umax_bc_ab(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
810; CHECK-LABEL: umax_bc_ab:
811; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]812; CHECK-NEXT: umax v2.4s, v1.4s, v2.4s
813; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
814; CHECK-NEXT: umax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]815; CHECK-NEXT: ret
816 %cmp_bc = icmp ugt <4 x i32> %b, %c
817 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
818 %cmp_ab = icmp ugt <4 x i32> %a, %b
819 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
820 %cmp_ca = icmp ugt <4 x i32> %c, %a
821 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
822 ret <4 x i32> %r
823}
824
825define <4 x i32> @umax_bc_ba(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
826; CHECK-LABEL: umax_bc_ba:
827; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]828; CHECK-NEXT: umax v2.4s, v1.4s, v2.4s
829; CHECK-NEXT: umax v0.4s, v1.4s, v0.4s
830; CHECK-NEXT: umax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]831; CHECK-NEXT: ret
832 %cmp_bc = icmp ugt <4 x i32> %b, %c
833 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
834 %cmp_ba = icmp ugt <4 x i32> %b, %a
835 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
836 %cmp_ca = icmp ugt <4 x i32> %c, %a
837 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
838 ret <4 x i32> %r
839}
840
841define <4 x i32> @umax_ab_bc_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
842; CHECK-LABEL: umax_ab_bc_swap_pred:
843; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]844; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]845; CHECK-NEXT: umax v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]846; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]847; CHECK-NEXT: ret
848 %cmp_ab = icmp ugt <4 x i32> %a, %b
849 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
850 %cmp_bc = icmp ugt <4 x i32> %b, %c
851 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
852 %cmp_ac = icmp ult <4 x i32> %c, %a
853 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
854 ret <4 x i32> %r
855}
856
857define <4 x i32> @umax_ab_cb_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
858; CHECK-LABEL: umax_ab_cb_swap_pred:
859; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]860; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]861; CHECK-NEXT: umax v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]862; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]863; CHECK-NEXT: ret
864 %cmp_ab = icmp ugt <4 x i32> %a, %b
865 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
866 %cmp_cb = icmp ugt <4 x i32> %c, %b
867 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
868 %cmp_ac = icmp ult <4 x i32> %c, %a
869 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
870 ret <4 x i32> %r
871}
872
873define <4 x i32> @umax_bc_ab_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
874; CHECK-LABEL: umax_bc_ab_swap_pred:
875; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]876; CHECK-NEXT: umax v2.4s, v1.4s, v2.4s
877; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
878; CHECK-NEXT: umax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]879; CHECK-NEXT: ret
880 %cmp_bc = icmp ugt <4 x i32> %b, %c
881 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
882 %cmp_ab = icmp ugt <4 x i32> %a, %b
883 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
884 %cmp_ca = icmp ult <4 x i32> %a, %c
885 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
886 ret <4 x i32> %r
887}
888
889define <4 x i32> @umax_bc_ba_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
890; CHECK-LABEL: umax_bc_ba_swap_pred:
891; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]892; CHECK-NEXT: umax v2.4s, v1.4s, v2.4s
893; CHECK-NEXT: umax v0.4s, v1.4s, v0.4s
894; CHECK-NEXT: umax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]895; CHECK-NEXT: ret
896 %cmp_bc = icmp ugt <4 x i32> %b, %c
897 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
898 %cmp_ba = icmp ugt <4 x i32> %b, %a
899 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
900 %cmp_ca = icmp ult <4 x i32> %a, %c
901 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
902 ret <4 x i32> %r
903}
904
905define <4 x i32> @umax_ab_bc_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
906; CHECK-LABEL: umax_ab_bc_eq_pred:
907; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]908; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]909; CHECK-NEXT: umax v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]910; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]911; CHECK-NEXT: ret
912 %cmp_ab = icmp ugt <4 x i32> %a, %b
913 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
914 %cmp_bc = icmp ugt <4 x i32> %b, %c
915 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
916 %cmp_ac = icmp uge <4 x i32> %a, %c
917 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
918 ret <4 x i32> %r
919}
920
921define <4 x i32> @umax_ab_cb_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
922; CHECK-LABEL: umax_ab_cb_eq_pred:
923; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]924; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]925; CHECK-NEXT: umax v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]926; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]927; CHECK-NEXT: ret
928 %cmp_ab = icmp ugt <4 x i32> %a, %b
929 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
930 %cmp_cb = icmp ugt <4 x i32> %c, %b
931 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
932 %cmp_ac = icmp uge <4 x i32> %a, %c
933 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
934 ret <4 x i32> %r
935}
936
937define <4 x i32> @umax_bc_ab_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
938; CHECK-LABEL: umax_bc_ab_eq_pred:
939; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]940; CHECK-NEXT: umax v2.4s, v1.4s, v2.4s
941; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
942; CHECK-NEXT: umax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]943; CHECK-NEXT: ret
944 %cmp_bc = icmp ugt <4 x i32> %b, %c
945 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
946 %cmp_ab = icmp ugt <4 x i32> %a, %b
947 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
948 %cmp_ca = icmp uge <4 x i32> %c, %a
949 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
950 ret <4 x i32> %r
951}
952
953define <4 x i32> @umax_bc_ba_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
954; CHECK-LABEL: umax_bc_ba_eq_pred:
955; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]956; CHECK-NEXT: umax v2.4s, v1.4s, v2.4s
957; CHECK-NEXT: umax v0.4s, v1.4s, v0.4s
958; CHECK-NEXT: umax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]959; CHECK-NEXT: ret
960 %cmp_bc = icmp ugt <4 x i32> %b, %c
961 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
962 %cmp_ba = icmp ugt <4 x i32> %b, %a
963 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
964 %cmp_ca = icmp uge <4 x i32> %c, %a
965 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
966 ret <4 x i32> %r
967}
968
969define <4 x i32> @umax_ab_bc_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
970; CHECK-LABEL: umax_ab_bc_eq_swap_pred:
971; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]972; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]973; CHECK-NEXT: umax v1.4s, v1.4s, v2.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]974; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]975; CHECK-NEXT: ret
976 %cmp_ab = icmp ugt <4 x i32> %a, %b
977 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
978 %cmp_bc = icmp ugt <4 x i32> %b, %c
979 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
980 %cmp_ac = icmp ule <4 x i32> %c, %a
981 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
982 ret <4 x i32> %r
983}
984
985define <4 x i32> @umax_ab_cb_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
986; CHECK-LABEL: umax_ab_cb_eq_swap_pred:
987; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]988; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]989; CHECK-NEXT: umax v1.4s, v2.4s, v1.4s
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]990; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]991; CHECK-NEXT: ret
992 %cmp_ab = icmp ugt <4 x i32> %a, %b
993 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
994 %cmp_cb = icmp ugt <4 x i32> %c, %b
995 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
996 %cmp_ac = icmp ule <4 x i32> %c, %a
997 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
998 ret <4 x i32> %r
999}
1000
1001define <4 x i32> @umax_bc_ab_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
1002; CHECK-LABEL: umax_bc_ab_eq_swap_pred:
1003; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]1004; CHECK-NEXT: umax v2.4s, v1.4s, v2.4s
1005; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s
1006; CHECK-NEXT: umax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]1007; CHECK-NEXT: ret
1008 %cmp_bc = icmp ugt <4 x i32> %b, %c
1009 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
1010 %cmp_ab = icmp ugt <4 x i32> %a, %b
1011 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
1012 %cmp_ca = icmp ule <4 x i32> %a, %c
1013 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
1014 ret <4 x i32> %r
1015}
1016
1017define <4 x i32> @umax_bc_ba_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
1018; CHECK-LABEL: umax_bc_ba_eq_swap_pred:
1019; CHECK: // %bb.0:
Sanjay Patel78114302018-01-02 20:56:45 +0000[diff] [blame^]1020; CHECK-NEXT: umax v2.4s, v1.4s, v2.4s
1021; CHECK-NEXT: umax v0.4s, v1.4s, v0.4s
1022; CHECK-NEXT: umax v0.4s, v2.4s, v0.4s
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame]1023; CHECK-NEXT: ret
1024 %cmp_bc = icmp ugt <4 x i32> %b, %c
1025 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
1026 %cmp_ba = icmp ugt <4 x i32> %b, %a
1027 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
1028 %cmp_ca = icmp ule <4 x i32> %a, %c
1029 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
1030 ret <4 x i32> %r
1031}
1032