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gerrit-public.fairphone.software / toolchain / llvm-project / 35a6ee86afc2bb0a148ceb397b24276526a70343 / . / llvm / test / CodeGen / AArch64 / minmax-of-minmax.ll
blob: 6172477072262522c96d3311962b16c7086ece13 [file] [log] [blame]
Sanjay Patel35a6ee82018-01-02 20:16:45 +0000[diff] [blame^]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
3
4; There are 4 commuted variants (abbc/abcb/bcab/bcba) *
5; 4 predicate variants ([*][lg][te] *
6; 4 min/max flavors (smin/smax/umin/max)
7; = 64 tests
8
9define <4 x i32> @smin_ab_bc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
10; CHECK-LABEL: smin_ab_bc:
11; CHECK: // %bb.0:
12; CHECK-NEXT: smin v3.4s, v0.4s, v1.4s
13; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
14; CHECK-NEXT: cmgt v0.4s, v2.4s, v0.4s
15; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
16; CHECK-NEXT: ret
17 %cmp_ab = icmp slt <4 x i32> %a, %b
18 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
19 %cmp_bc = icmp slt <4 x i32> %b, %c
20 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
21 %cmp_ac = icmp slt <4 x i32> %a, %c
22 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
23 ret <4 x i32> %r
24}
25
26define <4 x i32> @smin_ab_cb(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
27; CHECK-LABEL: smin_ab_cb:
28; CHECK: // %bb.0:
29; CHECK-NEXT: smin v3.4s, v0.4s, v1.4s
30; CHECK-NEXT: smin v1.4s, v2.4s, v1.4s
31; CHECK-NEXT: cmgt v0.4s, v2.4s, v0.4s
32; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
33; CHECK-NEXT: ret
34 %cmp_ab = icmp slt <4 x i32> %a, %b
35 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
36 %cmp_cb = icmp slt <4 x i32> %c, %b
37 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
38 %cmp_ac = icmp slt <4 x i32> %a, %c
39 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
40 ret <4 x i32> %r
41}
42
43define <4 x i32> @smin_bc_ab(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
44; CHECK-LABEL: smin_bc_ab:
45; CHECK: // %bb.0:
46; CHECK-NEXT: smin v3.4s, v1.4s, v2.4s
47; CHECK-NEXT: smin v1.4s, v0.4s, v1.4s
48; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
49; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
50; CHECK-NEXT: ret
51 %cmp_bc = icmp slt <4 x i32> %b, %c
52 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
53 %cmp_ab = icmp slt <4 x i32> %a, %b
54 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
55 %cmp_ca = icmp slt <4 x i32> %c, %a
56 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
57 ret <4 x i32> %r
58}
59
60define <4 x i32> @smin_bc_ba(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
61; CHECK-LABEL: smin_bc_ba:
62; CHECK: // %bb.0:
63; CHECK-NEXT: smin v3.4s, v1.4s, v2.4s
64; CHECK-NEXT: smin v1.4s, v1.4s, v0.4s
65; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
66; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
67; CHECK-NEXT: ret
68 %cmp_bc = icmp slt <4 x i32> %b, %c
69 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
70 %cmp_ba = icmp slt <4 x i32> %b, %a
71 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
72 %cmp_ca = icmp slt <4 x i32> %c, %a
73 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
74 ret <4 x i32> %r
75}
76
77define <4 x i32> @smin_ab_bc_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
78; CHECK-LABEL: smin_ab_bc_swap_pred:
79; CHECK: // %bb.0:
80; CHECK-NEXT: smin v3.4s, v0.4s, v1.4s
81; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
82; CHECK-NEXT: cmgt v0.4s, v2.4s, v0.4s
83; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
84; CHECK-NEXT: ret
85 %cmp_ab = icmp slt <4 x i32> %a, %b
86 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
87 %cmp_bc = icmp slt <4 x i32> %b, %c
88 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
89 %cmp_ac = icmp sgt <4 x i32> %c, %a
90 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
91 ret <4 x i32> %r
92}
93
94define <4 x i32> @smin_ab_cb_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
95; CHECK-LABEL: smin_ab_cb_swap_pred:
96; CHECK: // %bb.0:
97; CHECK-NEXT: smin v3.4s, v0.4s, v1.4s
98; CHECK-NEXT: smin v1.4s, v2.4s, v1.4s
99; CHECK-NEXT: cmgt v0.4s, v2.4s, v0.4s
100; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
101; CHECK-NEXT: ret
102 %cmp_ab = icmp slt <4 x i32> %a, %b
103 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
104 %cmp_cb = icmp slt <4 x i32> %c, %b
105 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
106 %cmp_ac = icmp sgt <4 x i32> %c, %a
107 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
108 ret <4 x i32> %r
109}
110
111define <4 x i32> @smin_bc_ab_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
112; CHECK-LABEL: smin_bc_ab_swap_pred:
113; CHECK: // %bb.0:
114; CHECK-NEXT: smin v3.4s, v1.4s, v2.4s
115; CHECK-NEXT: smin v1.4s, v0.4s, v1.4s
116; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
117; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
118; CHECK-NEXT: ret
119 %cmp_bc = icmp slt <4 x i32> %b, %c
120 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
121 %cmp_ab = icmp slt <4 x i32> %a, %b
122 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
123 %cmp_ca = icmp sgt <4 x i32> %a, %c
124 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
125 ret <4 x i32> %r
126}
127
128define <4 x i32> @smin_bc_ba_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
129; CHECK-LABEL: smin_bc_ba_swap_pred:
130; CHECK: // %bb.0:
131; CHECK-NEXT: smin v3.4s, v1.4s, v2.4s
132; CHECK-NEXT: smin v1.4s, v1.4s, v0.4s
133; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
134; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
135; CHECK-NEXT: ret
136 %cmp_bc = icmp slt <4 x i32> %b, %c
137 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
138 %cmp_ba = icmp slt <4 x i32> %b, %a
139 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
140 %cmp_ca = icmp sgt <4 x i32> %a, %c
141 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
142 ret <4 x i32> %r
143}
144
145define <4 x i32> @smin_ab_bc_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
146; CHECK-LABEL: smin_ab_bc_eq_pred:
147; CHECK: // %bb.0:
148; CHECK-NEXT: smin v3.4s, v0.4s, v1.4s
149; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
150; CHECK-NEXT: cmge v0.4s, v2.4s, v0.4s
151; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
152; CHECK-NEXT: ret
153 %cmp_ab = icmp slt <4 x i32> %a, %b
154 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
155 %cmp_bc = icmp slt <4 x i32> %b, %c
156 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
157 %cmp_ac = icmp sle <4 x i32> %a, %c
158 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
159 ret <4 x i32> %r
160}
161
162define <4 x i32> @smin_ab_cb_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
163; CHECK-LABEL: smin_ab_cb_eq_pred:
164; CHECK: // %bb.0:
165; CHECK-NEXT: smin v3.4s, v0.4s, v1.4s
166; CHECK-NEXT: smin v1.4s, v2.4s, v1.4s
167; CHECK-NEXT: cmge v0.4s, v2.4s, v0.4s
168; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
169; CHECK-NEXT: ret
170 %cmp_ab = icmp slt <4 x i32> %a, %b
171 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
172 %cmp_cb = icmp slt <4 x i32> %c, %b
173 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
174 %cmp_ac = icmp sle <4 x i32> %a, %c
175 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
176 ret <4 x i32> %r
177}
178
179define <4 x i32> @smin_bc_ab_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
180; CHECK-LABEL: smin_bc_ab_eq_pred:
181; CHECK: // %bb.0:
182; CHECK-NEXT: smin v3.4s, v1.4s, v2.4s
183; CHECK-NEXT: smin v1.4s, v0.4s, v1.4s
184; CHECK-NEXT: cmge v0.4s, v0.4s, v2.4s
185; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
186; CHECK-NEXT: ret
187 %cmp_bc = icmp slt <4 x i32> %b, %c
188 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
189 %cmp_ab = icmp slt <4 x i32> %a, %b
190 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
191 %cmp_ca = icmp sle <4 x i32> %c, %a
192 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
193 ret <4 x i32> %r
194}
195
196define <4 x i32> @smin_bc_ba_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
197; CHECK-LABEL: smin_bc_ba_eq_pred:
198; CHECK: // %bb.0:
199; CHECK-NEXT: smin v3.4s, v1.4s, v2.4s
200; CHECK-NEXT: smin v1.4s, v1.4s, v0.4s
201; CHECK-NEXT: cmge v0.4s, v0.4s, v2.4s
202; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
203; CHECK-NEXT: ret
204 %cmp_bc = icmp slt <4 x i32> %b, %c
205 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
206 %cmp_ba = icmp slt <4 x i32> %b, %a
207 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
208 %cmp_ca = icmp sle <4 x i32> %c, %a
209 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
210 ret <4 x i32> %r
211}
212
213define <4 x i32> @smin_ab_bc_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
214; CHECK-LABEL: smin_ab_bc_eq_swap_pred:
215; CHECK: // %bb.0:
216; CHECK-NEXT: smin v3.4s, v0.4s, v1.4s
217; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
218; CHECK-NEXT: cmge v0.4s, v2.4s, v0.4s
219; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
220; CHECK-NEXT: ret
221 %cmp_ab = icmp slt <4 x i32> %a, %b
222 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
223 %cmp_bc = icmp slt <4 x i32> %b, %c
224 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
225 %cmp_ac = icmp sge <4 x i32> %c, %a
226 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
227 ret <4 x i32> %r
228}
229
230define <4 x i32> @smin_ab_cb_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
231; CHECK-LABEL: smin_ab_cb_eq_swap_pred:
232; CHECK: // %bb.0:
233; CHECK-NEXT: smin v3.4s, v0.4s, v1.4s
234; CHECK-NEXT: smin v1.4s, v2.4s, v1.4s
235; CHECK-NEXT: cmge v0.4s, v2.4s, v0.4s
236; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
237; CHECK-NEXT: ret
238 %cmp_ab = icmp slt <4 x i32> %a, %b
239 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
240 %cmp_cb = icmp slt <4 x i32> %c, %b
241 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
242 %cmp_ac = icmp sge <4 x i32> %c, %a
243 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
244 ret <4 x i32> %r
245}
246
247define <4 x i32> @smin_bc_ab_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
248; CHECK-LABEL: smin_bc_ab_eq_swap_pred:
249; CHECK: // %bb.0:
250; CHECK-NEXT: smin v3.4s, v1.4s, v2.4s
251; CHECK-NEXT: smin v1.4s, v0.4s, v1.4s
252; CHECK-NEXT: cmge v0.4s, v0.4s, v2.4s
253; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
254; CHECK-NEXT: ret
255 %cmp_bc = icmp slt <4 x i32> %b, %c
256 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
257 %cmp_ab = icmp slt <4 x i32> %a, %b
258 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
259 %cmp_ca = icmp sge <4 x i32> %a, %c
260 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
261 ret <4 x i32> %r
262}
263
264define <4 x i32> @smin_bc_ba_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
265; CHECK-LABEL: smin_bc_ba_eq_swap_pred:
266; CHECK: // %bb.0:
267; CHECK-NEXT: smin v3.4s, v1.4s, v2.4s
268; CHECK-NEXT: smin v1.4s, v1.4s, v0.4s
269; CHECK-NEXT: cmge v0.4s, v0.4s, v2.4s
270; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
271; CHECK-NEXT: ret
272 %cmp_bc = icmp slt <4 x i32> %b, %c
273 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
274 %cmp_ba = icmp slt <4 x i32> %b, %a
275 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
276 %cmp_ca = icmp sge <4 x i32> %a, %c
277 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
278 ret <4 x i32> %r
279}
280
281define <4 x i32> @smax_ab_bc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
282; CHECK-LABEL: smax_ab_bc:
283; CHECK: // %bb.0:
284; CHECK-NEXT: smax v3.4s, v0.4s, v1.4s
285; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
286; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
287; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
288; CHECK-NEXT: ret
289 %cmp_ab = icmp sgt <4 x i32> %a, %b
290 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
291 %cmp_bc = icmp sgt <4 x i32> %b, %c
292 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
293 %cmp_ac = icmp sgt <4 x i32> %a, %c
294 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
295 ret <4 x i32> %r
296}
297
298define <4 x i32> @smax_ab_cb(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
299; CHECK-LABEL: smax_ab_cb:
300; CHECK: // %bb.0:
301; CHECK-NEXT: smax v3.4s, v0.4s, v1.4s
302; CHECK-NEXT: smax v1.4s, v2.4s, v1.4s
303; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
304; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
305; CHECK-NEXT: ret
306 %cmp_ab = icmp sgt <4 x i32> %a, %b
307 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
308 %cmp_cb = icmp sgt <4 x i32> %c, %b
309 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
310 %cmp_ac = icmp sgt <4 x i32> %a, %c
311 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
312 ret <4 x i32> %r
313}
314
315define <4 x i32> @smax_bc_ab(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
316; CHECK-LABEL: smax_bc_ab:
317; CHECK: // %bb.0:
318; CHECK-NEXT: smax v3.4s, v1.4s, v2.4s
319; CHECK-NEXT: smax v1.4s, v0.4s, v1.4s
320; CHECK-NEXT: cmgt v0.4s, v2.4s, v0.4s
321; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
322; CHECK-NEXT: ret
323 %cmp_bc = icmp sgt <4 x i32> %b, %c
324 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
325 %cmp_ab = icmp sgt <4 x i32> %a, %b
326 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
327 %cmp_ca = icmp sgt <4 x i32> %c, %a
328 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
329 ret <4 x i32> %r
330}
331
332define <4 x i32> @smax_bc_ba(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
333; CHECK-LABEL: smax_bc_ba:
334; CHECK: // %bb.0:
335; CHECK-NEXT: smax v3.4s, v1.4s, v2.4s
336; CHECK-NEXT: smax v1.4s, v1.4s, v0.4s
337; CHECK-NEXT: cmgt v0.4s, v2.4s, v0.4s
338; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
339; CHECK-NEXT: ret
340 %cmp_bc = icmp sgt <4 x i32> %b, %c
341 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
342 %cmp_ba = icmp sgt <4 x i32> %b, %a
343 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
344 %cmp_ca = icmp sgt <4 x i32> %c, %a
345 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
346 ret <4 x i32> %r
347}
348
349define <4 x i32> @smax_ab_bc_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
350; CHECK-LABEL: smax_ab_bc_swap_pred:
351; CHECK: // %bb.0:
352; CHECK-NEXT: smax v3.4s, v0.4s, v1.4s
353; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
354; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
355; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
356; CHECK-NEXT: ret
357 %cmp_ab = icmp sgt <4 x i32> %a, %b
358 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
359 %cmp_bc = icmp sgt <4 x i32> %b, %c
360 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
361 %cmp_ac = icmp slt <4 x i32> %c, %a
362 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
363 ret <4 x i32> %r
364}
365
366define <4 x i32> @smax_ab_cb_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
367; CHECK-LABEL: smax_ab_cb_swap_pred:
368; CHECK: // %bb.0:
369; CHECK-NEXT: smax v3.4s, v0.4s, v1.4s
370; CHECK-NEXT: smax v1.4s, v2.4s, v1.4s
371; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
372; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
373; CHECK-NEXT: ret
374 %cmp_ab = icmp sgt <4 x i32> %a, %b
375 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
376 %cmp_cb = icmp sgt <4 x i32> %c, %b
377 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
378 %cmp_ac = icmp slt <4 x i32> %c, %a
379 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
380 ret <4 x i32> %r
381}
382
383define <4 x i32> @smax_bc_ab_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
384; CHECK-LABEL: smax_bc_ab_swap_pred:
385; CHECK: // %bb.0:
386; CHECK-NEXT: smax v3.4s, v1.4s, v2.4s
387; CHECK-NEXT: smax v1.4s, v0.4s, v1.4s
388; CHECK-NEXT: cmgt v0.4s, v2.4s, v0.4s
389; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
390; CHECK-NEXT: ret
391 %cmp_bc = icmp sgt <4 x i32> %b, %c
392 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
393 %cmp_ab = icmp sgt <4 x i32> %a, %b
394 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
395 %cmp_ca = icmp slt <4 x i32> %a, %c
396 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
397 ret <4 x i32> %r
398}
399
400define <4 x i32> @smax_bc_ba_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
401; CHECK-LABEL: smax_bc_ba_swap_pred:
402; CHECK: // %bb.0:
403; CHECK-NEXT: smax v3.4s, v1.4s, v2.4s
404; CHECK-NEXT: smax v1.4s, v1.4s, v0.4s
405; CHECK-NEXT: cmgt v0.4s, v2.4s, v0.4s
406; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
407; CHECK-NEXT: ret
408 %cmp_bc = icmp sgt <4 x i32> %b, %c
409 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
410 %cmp_ba = icmp sgt <4 x i32> %b, %a
411 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
412 %cmp_ca = icmp slt <4 x i32> %a, %c
413 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
414 ret <4 x i32> %r
415}
416
417define <4 x i32> @smax_ab_bc_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
418; CHECK-LABEL: smax_ab_bc_eq_pred:
419; CHECK: // %bb.0:
420; CHECK-NEXT: smax v3.4s, v0.4s, v1.4s
421; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
422; CHECK-NEXT: cmge v0.4s, v0.4s, v2.4s
423; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
424; CHECK-NEXT: ret
425 %cmp_ab = icmp sgt <4 x i32> %a, %b
426 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
427 %cmp_bc = icmp sgt <4 x i32> %b, %c
428 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
429 %cmp_ac = icmp sge <4 x i32> %a, %c
430 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
431 ret <4 x i32> %r
432}
433
434define <4 x i32> @smax_ab_cb_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
435; CHECK-LABEL: smax_ab_cb_eq_pred:
436; CHECK: // %bb.0:
437; CHECK-NEXT: smax v3.4s, v0.4s, v1.4s
438; CHECK-NEXT: smax v1.4s, v2.4s, v1.4s
439; CHECK-NEXT: cmge v0.4s, v0.4s, v2.4s
440; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
441; CHECK-NEXT: ret
442 %cmp_ab = icmp sgt <4 x i32> %a, %b
443 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
444 %cmp_cb = icmp sgt <4 x i32> %c, %b
445 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
446 %cmp_ac = icmp sge <4 x i32> %a, %c
447 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
448 ret <4 x i32> %r
449}
450
451define <4 x i32> @smax_bc_ab_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
452; CHECK-LABEL: smax_bc_ab_eq_pred:
453; CHECK: // %bb.0:
454; CHECK-NEXT: smax v3.4s, v1.4s, v2.4s
455; CHECK-NEXT: smax v1.4s, v0.4s, v1.4s
456; CHECK-NEXT: cmge v0.4s, v2.4s, v0.4s
457; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
458; CHECK-NEXT: ret
459 %cmp_bc = icmp sgt <4 x i32> %b, %c
460 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
461 %cmp_ab = icmp sgt <4 x i32> %a, %b
462 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
463 %cmp_ca = icmp sge <4 x i32> %c, %a
464 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
465 ret <4 x i32> %r
466}
467
468define <4 x i32> @smax_bc_ba_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
469; CHECK-LABEL: smax_bc_ba_eq_pred:
470; CHECK: // %bb.0:
471; CHECK-NEXT: smax v3.4s, v1.4s, v2.4s
472; CHECK-NEXT: smax v1.4s, v1.4s, v0.4s
473; CHECK-NEXT: cmge v0.4s, v2.4s, v0.4s
474; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
475; CHECK-NEXT: ret
476 %cmp_bc = icmp sgt <4 x i32> %b, %c
477 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
478 %cmp_ba = icmp sgt <4 x i32> %b, %a
479 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
480 %cmp_ca = icmp sge <4 x i32> %c, %a
481 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
482 ret <4 x i32> %r
483}
484
485define <4 x i32> @smax_ab_bc_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
486; CHECK-LABEL: smax_ab_bc_eq_swap_pred:
487; CHECK: // %bb.0:
488; CHECK-NEXT: smax v3.4s, v0.4s, v1.4s
489; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
490; CHECK-NEXT: cmge v0.4s, v0.4s, v2.4s
491; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
492; CHECK-NEXT: ret
493 %cmp_ab = icmp sgt <4 x i32> %a, %b
494 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
495 %cmp_bc = icmp sgt <4 x i32> %b, %c
496 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
497 %cmp_ac = icmp sle <4 x i32> %c, %a
498 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
499 ret <4 x i32> %r
500}
501
502define <4 x i32> @smax_ab_cb_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
503; CHECK-LABEL: smax_ab_cb_eq_swap_pred:
504; CHECK: // %bb.0:
505; CHECK-NEXT: smax v3.4s, v0.4s, v1.4s
506; CHECK-NEXT: smax v1.4s, v2.4s, v1.4s
507; CHECK-NEXT: cmge v0.4s, v0.4s, v2.4s
508; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
509; CHECK-NEXT: ret
510 %cmp_ab = icmp sgt <4 x i32> %a, %b
511 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
512 %cmp_cb = icmp sgt <4 x i32> %c, %b
513 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
514 %cmp_ac = icmp sle <4 x i32> %c, %a
515 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
516 ret <4 x i32> %r
517}
518
519define <4 x i32> @smax_bc_ab_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
520; CHECK-LABEL: smax_bc_ab_eq_swap_pred:
521; CHECK: // %bb.0:
522; CHECK-NEXT: smax v3.4s, v1.4s, v2.4s
523; CHECK-NEXT: smax v1.4s, v0.4s, v1.4s
524; CHECK-NEXT: cmge v0.4s, v2.4s, v0.4s
525; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
526; CHECK-NEXT: ret
527 %cmp_bc = icmp sgt <4 x i32> %b, %c
528 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
529 %cmp_ab = icmp sgt <4 x i32> %a, %b
530 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
531 %cmp_ca = icmp sle <4 x i32> %a, %c
532 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
533 ret <4 x i32> %r
534}
535
536define <4 x i32> @smax_bc_ba_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
537; CHECK-LABEL: smax_bc_ba_eq_swap_pred:
538; CHECK: // %bb.0:
539; CHECK-NEXT: smax v3.4s, v1.4s, v2.4s
540; CHECK-NEXT: smax v1.4s, v1.4s, v0.4s
541; CHECK-NEXT: cmge v0.4s, v2.4s, v0.4s
542; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
543; CHECK-NEXT: ret
544 %cmp_bc = icmp sgt <4 x i32> %b, %c
545 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
546 %cmp_ba = icmp sgt <4 x i32> %b, %a
547 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
548 %cmp_ca = icmp sle <4 x i32> %a, %c
549 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
550 ret <4 x i32> %r
551}
552
553define <4 x i32> @umin_ab_bc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
554; CHECK-LABEL: umin_ab_bc:
555; CHECK: // %bb.0:
556; CHECK-NEXT: umin v3.4s, v0.4s, v1.4s
557; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
558; CHECK-NEXT: cmhi v0.4s, v2.4s, v0.4s
559; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
560; CHECK-NEXT: ret
561 %cmp_ab = icmp ult <4 x i32> %a, %b
562 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
563 %cmp_bc = icmp ult <4 x i32> %b, %c
564 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
565 %cmp_ac = icmp ult <4 x i32> %a, %c
566 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
567 ret <4 x i32> %r
568}
569
570define <4 x i32> @umin_ab_cb(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
571; CHECK-LABEL: umin_ab_cb:
572; CHECK: // %bb.0:
573; CHECK-NEXT: umin v3.4s, v0.4s, v1.4s
574; CHECK-NEXT: umin v1.4s, v2.4s, v1.4s
575; CHECK-NEXT: cmhi v0.4s, v2.4s, v0.4s
576; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
577; CHECK-NEXT: ret
578 %cmp_ab = icmp ult <4 x i32> %a, %b
579 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
580 %cmp_cb = icmp ult <4 x i32> %c, %b
581 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
582 %cmp_ac = icmp ult <4 x i32> %a, %c
583 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
584 ret <4 x i32> %r
585}
586
587define <4 x i32> @umin_bc_ab(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
588; CHECK-LABEL: umin_bc_ab:
589; CHECK: // %bb.0:
590; CHECK-NEXT: umin v3.4s, v1.4s, v2.4s
591; CHECK-NEXT: umin v1.4s, v0.4s, v1.4s
592; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
593; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
594; CHECK-NEXT: ret
595 %cmp_bc = icmp ult <4 x i32> %b, %c
596 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
597 %cmp_ab = icmp ult <4 x i32> %a, %b
598 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
599 %cmp_ca = icmp ult <4 x i32> %c, %a
600 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
601 ret <4 x i32> %r
602}
603
604define <4 x i32> @umin_bc_ba(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
605; CHECK-LABEL: umin_bc_ba:
606; CHECK: // %bb.0:
607; CHECK-NEXT: umin v3.4s, v1.4s, v2.4s
608; CHECK-NEXT: umin v1.4s, v1.4s, v0.4s
609; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
610; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
611; CHECK-NEXT: ret
612 %cmp_bc = icmp ult <4 x i32> %b, %c
613 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
614 %cmp_ba = icmp ult <4 x i32> %b, %a
615 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
616 %cmp_ca = icmp ult <4 x i32> %c, %a
617 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
618 ret <4 x i32> %r
619}
620
621define <4 x i32> @umin_ab_bc_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
622; CHECK-LABEL: umin_ab_bc_swap_pred:
623; CHECK: // %bb.0:
624; CHECK-NEXT: umin v3.4s, v0.4s, v1.4s
625; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
626; CHECK-NEXT: cmhi v0.4s, v2.4s, v0.4s
627; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
628; CHECK-NEXT: ret
629 %cmp_ab = icmp ult <4 x i32> %a, %b
630 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
631 %cmp_bc = icmp ult <4 x i32> %b, %c
632 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
633 %cmp_ac = icmp ugt <4 x i32> %c, %a
634 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
635 ret <4 x i32> %r
636}
637
638define <4 x i32> @umin_ab_cb_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
639; CHECK-LABEL: umin_ab_cb_swap_pred:
640; CHECK: // %bb.0:
641; CHECK-NEXT: umin v3.4s, v0.4s, v1.4s
642; CHECK-NEXT: umin v1.4s, v2.4s, v1.4s
643; CHECK-NEXT: cmhi v0.4s, v2.4s, v0.4s
644; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
645; CHECK-NEXT: ret
646 %cmp_ab = icmp ult <4 x i32> %a, %b
647 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
648 %cmp_cb = icmp ult <4 x i32> %c, %b
649 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
650 %cmp_ac = icmp ugt <4 x i32> %c, %a
651 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
652 ret <4 x i32> %r
653}
654
655define <4 x i32> @umin_bc_ab_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
656; CHECK-LABEL: umin_bc_ab_swap_pred:
657; CHECK: // %bb.0:
658; CHECK-NEXT: umin v3.4s, v1.4s, v2.4s
659; CHECK-NEXT: umin v1.4s, v0.4s, v1.4s
660; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
661; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
662; CHECK-NEXT: ret
663 %cmp_bc = icmp ult <4 x i32> %b, %c
664 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
665 %cmp_ab = icmp ult <4 x i32> %a, %b
666 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
667 %cmp_ca = icmp ugt <4 x i32> %a, %c
668 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
669 ret <4 x i32> %r
670}
671
672define <4 x i32> @umin_bc_ba_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
673; CHECK-LABEL: umin_bc_ba_swap_pred:
674; CHECK: // %bb.0:
675; CHECK-NEXT: umin v3.4s, v1.4s, v2.4s
676; CHECK-NEXT: umin v1.4s, v1.4s, v0.4s
677; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
678; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
679; CHECK-NEXT: ret
680 %cmp_bc = icmp ult <4 x i32> %b, %c
681 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
682 %cmp_ba = icmp ult <4 x i32> %b, %a
683 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
684 %cmp_ca = icmp ugt <4 x i32> %a, %c
685 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
686 ret <4 x i32> %r
687}
688
689define <4 x i32> @umin_ab_bc_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
690; CHECK-LABEL: umin_ab_bc_eq_pred:
691; CHECK: // %bb.0:
692; CHECK-NEXT: umin v3.4s, v0.4s, v1.4s
693; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
694; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
695; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
696; CHECK-NEXT: ret
697 %cmp_ab = icmp ult <4 x i32> %a, %b
698 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
699 %cmp_bc = icmp ult <4 x i32> %b, %c
700 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
701 %cmp_ac = icmp ule <4 x i32> %a, %c
702 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
703 ret <4 x i32> %r
704}
705
706define <4 x i32> @umin_ab_cb_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
707; CHECK-LABEL: umin_ab_cb_eq_pred:
708; CHECK: // %bb.0:
709; CHECK-NEXT: umin v3.4s, v0.4s, v1.4s
710; CHECK-NEXT: umin v1.4s, v2.4s, v1.4s
711; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
712; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
713; CHECK-NEXT: ret
714 %cmp_ab = icmp ult <4 x i32> %a, %b
715 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
716 %cmp_cb = icmp ult <4 x i32> %c, %b
717 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
718 %cmp_ac = icmp ule <4 x i32> %a, %c
719 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
720 ret <4 x i32> %r
721}
722
723define <4 x i32> @umin_bc_ab_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
724; CHECK-LABEL: umin_bc_ab_eq_pred:
725; CHECK: // %bb.0:
726; CHECK-NEXT: umin v3.4s, v1.4s, v2.4s
727; CHECK-NEXT: umin v1.4s, v0.4s, v1.4s
728; CHECK-NEXT: cmhs v0.4s, v0.4s, v2.4s
729; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
730; CHECK-NEXT: ret
731 %cmp_bc = icmp ult <4 x i32> %b, %c
732 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
733 %cmp_ab = icmp ult <4 x i32> %a, %b
734 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
735 %cmp_ca = icmp ule <4 x i32> %c, %a
736 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
737 ret <4 x i32> %r
738}
739
740define <4 x i32> @umin_bc_ba_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
741; CHECK-LABEL: umin_bc_ba_eq_pred:
742; CHECK: // %bb.0:
743; CHECK-NEXT: umin v3.4s, v1.4s, v2.4s
744; CHECK-NEXT: umin v1.4s, v1.4s, v0.4s
745; CHECK-NEXT: cmhs v0.4s, v0.4s, v2.4s
746; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
747; CHECK-NEXT: ret
748 %cmp_bc = icmp ult <4 x i32> %b, %c
749 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
750 %cmp_ba = icmp ult <4 x i32> %b, %a
751 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
752 %cmp_ca = icmp ule <4 x i32> %c, %a
753 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
754 ret <4 x i32> %r
755}
756
757define <4 x i32> @umin_ab_bc_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
758; CHECK-LABEL: umin_ab_bc_eq_swap_pred:
759; CHECK: // %bb.0:
760; CHECK-NEXT: umin v3.4s, v0.4s, v1.4s
761; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
762; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
763; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
764; CHECK-NEXT: ret
765 %cmp_ab = icmp ult <4 x i32> %a, %b
766 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
767 %cmp_bc = icmp ult <4 x i32> %b, %c
768 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
769 %cmp_ac = icmp uge <4 x i32> %c, %a
770 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
771 ret <4 x i32> %r
772}
773
774define <4 x i32> @umin_ab_cb_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
775; CHECK-LABEL: umin_ab_cb_eq_swap_pred:
776; CHECK: // %bb.0:
777; CHECK-NEXT: umin v3.4s, v0.4s, v1.4s
778; CHECK-NEXT: umin v1.4s, v2.4s, v1.4s
779; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
780; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
781; CHECK-NEXT: ret
782 %cmp_ab = icmp ult <4 x i32> %a, %b
783 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
784 %cmp_cb = icmp ult <4 x i32> %c, %b
785 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
786 %cmp_ac = icmp uge <4 x i32> %c, %a
787 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
788 ret <4 x i32> %r
789}
790
791define <4 x i32> @umin_bc_ab_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
792; CHECK-LABEL: umin_bc_ab_eq_swap_pred:
793; CHECK: // %bb.0:
794; CHECK-NEXT: umin v3.4s, v1.4s, v2.4s
795; CHECK-NEXT: umin v1.4s, v0.4s, v1.4s
796; CHECK-NEXT: cmhs v0.4s, v0.4s, v2.4s
797; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
798; CHECK-NEXT: ret
799 %cmp_bc = icmp ult <4 x i32> %b, %c
800 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
801 %cmp_ab = icmp ult <4 x i32> %a, %b
802 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
803 %cmp_ca = icmp uge <4 x i32> %a, %c
804 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
805 ret <4 x i32> %r
806}
807
808define <4 x i32> @umin_bc_ba_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
809; CHECK-LABEL: umin_bc_ba_eq_swap_pred:
810; CHECK: // %bb.0:
811; CHECK-NEXT: umin v3.4s, v1.4s, v2.4s
812; CHECK-NEXT: umin v1.4s, v1.4s, v0.4s
813; CHECK-NEXT: cmhs v0.4s, v0.4s, v2.4s
814; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
815; CHECK-NEXT: ret
816 %cmp_bc = icmp ult <4 x i32> %b, %c
817 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
818 %cmp_ba = icmp ult <4 x i32> %b, %a
819 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
820 %cmp_ca = icmp uge <4 x i32> %a, %c
821 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
822 ret <4 x i32> %r
823}
824
825define <4 x i32> @umax_ab_bc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
826; CHECK-LABEL: umax_ab_bc:
827; CHECK: // %bb.0:
828; CHECK-NEXT: umax v3.4s, v0.4s, v1.4s
829; CHECK-NEXT: umax v1.4s, v1.4s, v2.4s
830; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
831; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
832; CHECK-NEXT: ret
833 %cmp_ab = icmp ugt <4 x i32> %a, %b
834 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
835 %cmp_bc = icmp ugt <4 x i32> %b, %c
836 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
837 %cmp_ac = icmp ugt <4 x i32> %a, %c
838 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
839 ret <4 x i32> %r
840}
841
842define <4 x i32> @umax_ab_cb(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
843; CHECK-LABEL: umax_ab_cb:
844; CHECK: // %bb.0:
845; CHECK-NEXT: umax v3.4s, v0.4s, v1.4s
846; CHECK-NEXT: umax v1.4s, v2.4s, v1.4s
847; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
848; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
849; CHECK-NEXT: ret
850 %cmp_ab = icmp ugt <4 x i32> %a, %b
851 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
852 %cmp_cb = icmp ugt <4 x i32> %c, %b
853 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
854 %cmp_ac = icmp ugt <4 x i32> %a, %c
855 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
856 ret <4 x i32> %r
857}
858
859define <4 x i32> @umax_bc_ab(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
860; CHECK-LABEL: umax_bc_ab:
861; CHECK: // %bb.0:
862; CHECK-NEXT: umax v3.4s, v1.4s, v2.4s
863; CHECK-NEXT: umax v1.4s, v0.4s, v1.4s
864; CHECK-NEXT: cmhi v0.4s, v2.4s, v0.4s
865; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
866; CHECK-NEXT: ret
867 %cmp_bc = icmp ugt <4 x i32> %b, %c
868 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
869 %cmp_ab = icmp ugt <4 x i32> %a, %b
870 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
871 %cmp_ca = icmp ugt <4 x i32> %c, %a
872 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
873 ret <4 x i32> %r
874}
875
876define <4 x i32> @umax_bc_ba(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
877; CHECK-LABEL: umax_bc_ba:
878; CHECK: // %bb.0:
879; CHECK-NEXT: umax v3.4s, v1.4s, v2.4s
880; CHECK-NEXT: umax v1.4s, v1.4s, v0.4s
881; CHECK-NEXT: cmhi v0.4s, v2.4s, v0.4s
882; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
883; CHECK-NEXT: ret
884 %cmp_bc = icmp ugt <4 x i32> %b, %c
885 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
886 %cmp_ba = icmp ugt <4 x i32> %b, %a
887 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
888 %cmp_ca = icmp ugt <4 x i32> %c, %a
889 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
890 ret <4 x i32> %r
891}
892
893define <4 x i32> @umax_ab_bc_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
894; CHECK-LABEL: umax_ab_bc_swap_pred:
895; CHECK: // %bb.0:
896; CHECK-NEXT: umax v3.4s, v0.4s, v1.4s
897; CHECK-NEXT: umax v1.4s, v1.4s, v2.4s
898; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
899; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
900; CHECK-NEXT: ret
901 %cmp_ab = icmp ugt <4 x i32> %a, %b
902 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
903 %cmp_bc = icmp ugt <4 x i32> %b, %c
904 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
905 %cmp_ac = icmp ult <4 x i32> %c, %a
906 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
907 ret <4 x i32> %r
908}
909
910define <4 x i32> @umax_ab_cb_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
911; CHECK-LABEL: umax_ab_cb_swap_pred:
912; CHECK: // %bb.0:
913; CHECK-NEXT: umax v3.4s, v0.4s, v1.4s
914; CHECK-NEXT: umax v1.4s, v2.4s, v1.4s
915; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
916; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
917; CHECK-NEXT: ret
918 %cmp_ab = icmp ugt <4 x i32> %a, %b
919 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
920 %cmp_cb = icmp ugt <4 x i32> %c, %b
921 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
922 %cmp_ac = icmp ult <4 x i32> %c, %a
923 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
924 ret <4 x i32> %r
925}
926
927define <4 x i32> @umax_bc_ab_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
928; CHECK-LABEL: umax_bc_ab_swap_pred:
929; CHECK: // %bb.0:
930; CHECK-NEXT: umax v3.4s, v1.4s, v2.4s
931; CHECK-NEXT: umax v1.4s, v0.4s, v1.4s
932; CHECK-NEXT: cmhi v0.4s, v2.4s, v0.4s
933; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
934; CHECK-NEXT: ret
935 %cmp_bc = icmp ugt <4 x i32> %b, %c
936 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
937 %cmp_ab = icmp ugt <4 x i32> %a, %b
938 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
939 %cmp_ca = icmp ult <4 x i32> %a, %c
940 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
941 ret <4 x i32> %r
942}
943
944define <4 x i32> @umax_bc_ba_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
945; CHECK-LABEL: umax_bc_ba_swap_pred:
946; CHECK: // %bb.0:
947; CHECK-NEXT: umax v3.4s, v1.4s, v2.4s
948; CHECK-NEXT: umax v1.4s, v1.4s, v0.4s
949; CHECK-NEXT: cmhi v0.4s, v2.4s, v0.4s
950; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
951; CHECK-NEXT: ret
952 %cmp_bc = icmp ugt <4 x i32> %b, %c
953 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
954 %cmp_ba = icmp ugt <4 x i32> %b, %a
955 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
956 %cmp_ca = icmp ult <4 x i32> %a, %c
957 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
958 ret <4 x i32> %r
959}
960
961define <4 x i32> @umax_ab_bc_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
962; CHECK-LABEL: umax_ab_bc_eq_pred:
963; CHECK: // %bb.0:
964; CHECK-NEXT: umax v3.4s, v0.4s, v1.4s
965; CHECK-NEXT: umax v1.4s, v1.4s, v2.4s
966; CHECK-NEXT: cmhs v0.4s, v0.4s, v2.4s
967; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
968; CHECK-NEXT: ret
969 %cmp_ab = icmp ugt <4 x i32> %a, %b
970 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
971 %cmp_bc = icmp ugt <4 x i32> %b, %c
972 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
973 %cmp_ac = icmp uge <4 x i32> %a, %c
974 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
975 ret <4 x i32> %r
976}
977
978define <4 x i32> @umax_ab_cb_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
979; CHECK-LABEL: umax_ab_cb_eq_pred:
980; CHECK: // %bb.0:
981; CHECK-NEXT: umax v3.4s, v0.4s, v1.4s
982; CHECK-NEXT: umax v1.4s, v2.4s, v1.4s
983; CHECK-NEXT: cmhs v0.4s, v0.4s, v2.4s
984; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
985; CHECK-NEXT: ret
986 %cmp_ab = icmp ugt <4 x i32> %a, %b
987 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
988 %cmp_cb = icmp ugt <4 x i32> %c, %b
989 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
990 %cmp_ac = icmp uge <4 x i32> %a, %c
991 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
992 ret <4 x i32> %r
993}
994
995define <4 x i32> @umax_bc_ab_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
996; CHECK-LABEL: umax_bc_ab_eq_pred:
997; CHECK: // %bb.0:
998; CHECK-NEXT: umax v3.4s, v1.4s, v2.4s
999; CHECK-NEXT: umax v1.4s, v0.4s, v1.4s
1000; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
1001; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
1002; CHECK-NEXT: ret
1003 %cmp_bc = icmp ugt <4 x i32> %b, %c
1004 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
1005 %cmp_ab = icmp ugt <4 x i32> %a, %b
1006 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
1007 %cmp_ca = icmp uge <4 x i32> %c, %a
1008 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
1009 ret <4 x i32> %r
1010}
1011
1012define <4 x i32> @umax_bc_ba_eq_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
1013; CHECK-LABEL: umax_bc_ba_eq_pred:
1014; CHECK: // %bb.0:
1015; CHECK-NEXT: umax v3.4s, v1.4s, v2.4s
1016; CHECK-NEXT: umax v1.4s, v1.4s, v0.4s
1017; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
1018; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
1019; CHECK-NEXT: ret
1020 %cmp_bc = icmp ugt <4 x i32> %b, %c
1021 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
1022 %cmp_ba = icmp ugt <4 x i32> %b, %a
1023 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
1024 %cmp_ca = icmp uge <4 x i32> %c, %a
1025 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
1026 ret <4 x i32> %r
1027}
1028
1029define <4 x i32> @umax_ab_bc_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
1030; CHECK-LABEL: umax_ab_bc_eq_swap_pred:
1031; CHECK: // %bb.0:
1032; CHECK-NEXT: umax v3.4s, v0.4s, v1.4s
1033; CHECK-NEXT: umax v1.4s, v1.4s, v2.4s
1034; CHECK-NEXT: cmhs v0.4s, v0.4s, v2.4s
1035; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
1036; CHECK-NEXT: ret
1037 %cmp_ab = icmp ugt <4 x i32> %a, %b
1038 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
1039 %cmp_bc = icmp ugt <4 x i32> %b, %c
1040 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
1041 %cmp_ac = icmp ule <4 x i32> %c, %a
1042 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_bc
1043 ret <4 x i32> %r
1044}
1045
1046define <4 x i32> @umax_ab_cb_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
1047; CHECK-LABEL: umax_ab_cb_eq_swap_pred:
1048; CHECK: // %bb.0:
1049; CHECK-NEXT: umax v3.4s, v0.4s, v1.4s
1050; CHECK-NEXT: umax v1.4s, v2.4s, v1.4s
1051; CHECK-NEXT: cmhs v0.4s, v0.4s, v2.4s
1052; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
1053; CHECK-NEXT: ret
1054 %cmp_ab = icmp ugt <4 x i32> %a, %b
1055 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
1056 %cmp_cb = icmp ugt <4 x i32> %c, %b
1057 %min_cb = select <4 x i1> %cmp_cb, <4 x i32> %c, <4 x i32> %b
1058 %cmp_ac = icmp ule <4 x i32> %c, %a
1059 %r = select <4 x i1> %cmp_ac, <4 x i32> %min_ab, <4 x i32> %min_cb
1060 ret <4 x i32> %r
1061}
1062
1063define <4 x i32> @umax_bc_ab_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
1064; CHECK-LABEL: umax_bc_ab_eq_swap_pred:
1065; CHECK: // %bb.0:
1066; CHECK-NEXT: umax v3.4s, v1.4s, v2.4s
1067; CHECK-NEXT: umax v1.4s, v0.4s, v1.4s
1068; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
1069; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
1070; CHECK-NEXT: ret
1071 %cmp_bc = icmp ugt <4 x i32> %b, %c
1072 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
1073 %cmp_ab = icmp ugt <4 x i32> %a, %b
1074 %min_ab = select <4 x i1> %cmp_ab, <4 x i32> %a, <4 x i32> %b
1075 %cmp_ca = icmp ule <4 x i32> %a, %c
1076 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ab
1077 ret <4 x i32> %r
1078}
1079
1080define <4 x i32> @umax_bc_ba_eq_swap_pred(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
1081; CHECK-LABEL: umax_bc_ba_eq_swap_pred:
1082; CHECK: // %bb.0:
1083; CHECK-NEXT: umax v3.4s, v1.4s, v2.4s
1084; CHECK-NEXT: umax v1.4s, v1.4s, v0.4s
1085; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
1086; CHECK-NEXT: bsl v0.16b, v3.16b, v1.16b
1087; CHECK-NEXT: ret
1088 %cmp_bc = icmp ugt <4 x i32> %b, %c
1089 %min_bc = select <4 x i1> %cmp_bc, <4 x i32> %b, <4 x i32> %c
1090 %cmp_ba = icmp ugt <4 x i32> %b, %a
1091 %min_ba = select <4 x i1> %cmp_ba, <4 x i32> %b, <4 x i32> %a
1092 %cmp_ca = icmp ule <4 x i32> %a, %c
1093 %r = select <4 x i1> %cmp_ca, <4 x i32> %min_bc, <4 x i32> %min_ba
1094 ret <4 x i32> %r
1095}
1096