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gerrit-public.fairphone.software / toolchain / llvm-project / 2b4385846c86078e0012e7bfb2e8dc6476ae8dd0 / . / llvm / test / CodeGen / PowerPC / atomics-regression.ll
blob: c8fb1e74e73f427c7fee322f93ec0e87f0178c01 [file] [log] [blame]
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s -check-prefix=PPC64LE
3
4define i8 @test0(i8* %ptr) {
5; PPC64LE-LABEL: test0:
6; PPC64LE: # BB#0:
7; PPC64LE-NEXT: lbz 3, 0(3)
8; PPC64LE-NEXT: blr
9 %val = load atomic i8, i8* %ptr unordered, align 1
10 ret i8 %val
11}
12
13define i8 @test1(i8* %ptr) {
14; PPC64LE-LABEL: test1:
15; PPC64LE: # BB#0:
16; PPC64LE-NEXT: lbz 3, 0(3)
17; PPC64LE-NEXT: blr
18 %val = load atomic i8, i8* %ptr monotonic, align 1
19 ret i8 %val
20}
21
22define i8 @test2(i8* %ptr) {
23; PPC64LE-LABEL: test2:
24; PPC64LE: # BB#0:
25; PPC64LE-NEXT: lbz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]26; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]27; PPC64LE-NEXT: bne- 7, .+4
28; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]29; PPC64LE-NEXT: blr
30 %val = load atomic i8, i8* %ptr acquire, align 1
31 ret i8 %val
32}
33
34define i8 @test3(i8* %ptr) {
35; PPC64LE-LABEL: test3:
36; PPC64LE: # BB#0:
37; PPC64LE-NEXT: sync
38; PPC64LE-NEXT: ori 2, 2, 0
39; PPC64LE-NEXT: lbz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]40; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]41; PPC64LE-NEXT: bne- 7, .+4
42; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]43; PPC64LE-NEXT: blr
44 %val = load atomic i8, i8* %ptr seq_cst, align 1
45 ret i8 %val
46}
47
48define i16 @test4(i16* %ptr) {
49; PPC64LE-LABEL: test4:
50; PPC64LE: # BB#0:
51; PPC64LE-NEXT: lhz 3, 0(3)
52; PPC64LE-NEXT: blr
53 %val = load atomic i16, i16* %ptr unordered, align 2
54 ret i16 %val
55}
56
57define i16 @test5(i16* %ptr) {
58; PPC64LE-LABEL: test5:
59; PPC64LE: # BB#0:
60; PPC64LE-NEXT: lhz 3, 0(3)
61; PPC64LE-NEXT: blr
62 %val = load atomic i16, i16* %ptr monotonic, align 2
63 ret i16 %val
64}
65
66define i16 @test6(i16* %ptr) {
67; PPC64LE-LABEL: test6:
68; PPC64LE: # BB#0:
69; PPC64LE-NEXT: lhz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]70; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]71; PPC64LE-NEXT: bne- 7, .+4
72; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]73; PPC64LE-NEXT: blr
74 %val = load atomic i16, i16* %ptr acquire, align 2
75 ret i16 %val
76}
77
78define i16 @test7(i16* %ptr) {
79; PPC64LE-LABEL: test7:
80; PPC64LE: # BB#0:
81; PPC64LE-NEXT: sync
82; PPC64LE-NEXT: ori 2, 2, 0
83; PPC64LE-NEXT: lhz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]84; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]85; PPC64LE-NEXT: bne- 7, .+4
86; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]87; PPC64LE-NEXT: blr
88 %val = load atomic i16, i16* %ptr seq_cst, align 2
89 ret i16 %val
90}
91
92define i32 @test8(i32* %ptr) {
93; PPC64LE-LABEL: test8:
94; PPC64LE: # BB#0:
95; PPC64LE-NEXT: lwz 3, 0(3)
96; PPC64LE-NEXT: blr
97 %val = load atomic i32, i32* %ptr unordered, align 4
98 ret i32 %val
99}
100
101define i32 @test9(i32* %ptr) {
102; PPC64LE-LABEL: test9:
103; PPC64LE: # BB#0:
104; PPC64LE-NEXT: lwz 3, 0(3)
105; PPC64LE-NEXT: blr
106 %val = load atomic i32, i32* %ptr monotonic, align 4
107 ret i32 %val
108}
109
110define i32 @test10(i32* %ptr) {
111; PPC64LE-LABEL: test10:
112; PPC64LE: # BB#0:
113; PPC64LE-NEXT: lwz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]114; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]115; PPC64LE-NEXT: bne- 7, .+4
116; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]117; PPC64LE-NEXT: blr
118 %val = load atomic i32, i32* %ptr acquire, align 4
119 ret i32 %val
120}
121
122define i32 @test11(i32* %ptr) {
123; PPC64LE-LABEL: test11:
124; PPC64LE: # BB#0:
125; PPC64LE-NEXT: sync
126; PPC64LE-NEXT: ori 2, 2, 0
127; PPC64LE-NEXT: lwz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]128; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]129; PPC64LE-NEXT: bne- 7, .+4
130; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]131; PPC64LE-NEXT: blr
132 %val = load atomic i32, i32* %ptr seq_cst, align 4
133 ret i32 %val
134}
135
136define i64 @test12(i64* %ptr) {
137; PPC64LE-LABEL: test12:
138; PPC64LE: # BB#0:
139; PPC64LE-NEXT: ld 3, 0(3)
140; PPC64LE-NEXT: blr
141 %val = load atomic i64, i64* %ptr unordered, align 8
142 ret i64 %val
143}
144
145define i64 @test13(i64* %ptr) {
146; PPC64LE-LABEL: test13:
147; PPC64LE: # BB#0:
148; PPC64LE-NEXT: ld 3, 0(3)
149; PPC64LE-NEXT: blr
150 %val = load atomic i64, i64* %ptr monotonic, align 8
151 ret i64 %val
152}
153
154define i64 @test14(i64* %ptr) {
155; PPC64LE-LABEL: test14:
156; PPC64LE: # BB#0:
157; PPC64LE-NEXT: ld 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]158; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]159; PPC64LE-NEXT: bne- 7, .+4
160; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]161; PPC64LE-NEXT: blr
162 %val = load atomic i64, i64* %ptr acquire, align 8
163 ret i64 %val
164}
165
166define i64 @test15(i64* %ptr) {
167; PPC64LE-LABEL: test15:
168; PPC64LE: # BB#0:
169; PPC64LE-NEXT: sync
170; PPC64LE-NEXT: ori 2, 2, 0
171; PPC64LE-NEXT: ld 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]172; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]173; PPC64LE-NEXT: bne- 7, .+4
174; PPC64LE-NEXT: isync
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]175; PPC64LE-NEXT: blr
176 %val = load atomic i64, i64* %ptr seq_cst, align 8
177 ret i64 %val
178}
179
180define void @test16(i8* %ptr, i8 %val) {
181; PPC64LE-LABEL: test16:
182; PPC64LE: # BB#0:
183; PPC64LE-NEXT: stb 4, 0(3)
184; PPC64LE-NEXT: blr
185 store atomic i8 %val, i8* %ptr unordered, align 1
186 ret void
187}
188
189define void @test17(i8* %ptr, i8 %val) {
190; PPC64LE-LABEL: test17:
191; PPC64LE: # BB#0:
192; PPC64LE-NEXT: stb 4, 0(3)
193; PPC64LE-NEXT: blr
194 store atomic i8 %val, i8* %ptr monotonic, align 1
195 ret void
196}
197
198define void @test18(i8* %ptr, i8 %val) {
199; PPC64LE-LABEL: test18:
200; PPC64LE: # BB#0:
201; PPC64LE-NEXT: lwsync
202; PPC64LE-NEXT: stb 4, 0(3)
203; PPC64LE-NEXT: blr
204 store atomic i8 %val, i8* %ptr release, align 1
205 ret void
206}
207
208define void @test19(i8* %ptr, i8 %val) {
209; PPC64LE-LABEL: test19:
210; PPC64LE: # BB#0:
211; PPC64LE-NEXT: sync
212; PPC64LE-NEXT: stb 4, 0(3)
213; PPC64LE-NEXT: blr
214 store atomic i8 %val, i8* %ptr seq_cst, align 1
215 ret void
216}
217
218define void @test20(i16* %ptr, i16 %val) {
219; PPC64LE-LABEL: test20:
220; PPC64LE: # BB#0:
221; PPC64LE-NEXT: sth 4, 0(3)
222; PPC64LE-NEXT: blr
223 store atomic i16 %val, i16* %ptr unordered, align 2
224 ret void
225}
226
227define void @test21(i16* %ptr, i16 %val) {
228; PPC64LE-LABEL: test21:
229; PPC64LE: # BB#0:
230; PPC64LE-NEXT: sth 4, 0(3)
231; PPC64LE-NEXT: blr
232 store atomic i16 %val, i16* %ptr monotonic, align 2
233 ret void
234}
235
236define void @test22(i16* %ptr, i16 %val) {
237; PPC64LE-LABEL: test22:
238; PPC64LE: # BB#0:
239; PPC64LE-NEXT: lwsync
240; PPC64LE-NEXT: sth 4, 0(3)
241; PPC64LE-NEXT: blr
242 store atomic i16 %val, i16* %ptr release, align 2
243 ret void
244}
245
246define void @test23(i16* %ptr, i16 %val) {
247; PPC64LE-LABEL: test23:
248; PPC64LE: # BB#0:
249; PPC64LE-NEXT: sync
250; PPC64LE-NEXT: sth 4, 0(3)
251; PPC64LE-NEXT: blr
252 store atomic i16 %val, i16* %ptr seq_cst, align 2
253 ret void
254}
255
256define void @test24(i32* %ptr, i32 %val) {
257; PPC64LE-LABEL: test24:
258; PPC64LE: # BB#0:
259; PPC64LE-NEXT: stw 4, 0(3)
260; PPC64LE-NEXT: blr
261 store atomic i32 %val, i32* %ptr unordered, align 4
262 ret void
263}
264
265define void @test25(i32* %ptr, i32 %val) {
266; PPC64LE-LABEL: test25:
267; PPC64LE: # BB#0:
268; PPC64LE-NEXT: stw 4, 0(3)
269; PPC64LE-NEXT: blr
270 store atomic i32 %val, i32* %ptr monotonic, align 4
271 ret void
272}
273
274define void @test26(i32* %ptr, i32 %val) {
275; PPC64LE-LABEL: test26:
276; PPC64LE: # BB#0:
277; PPC64LE-NEXT: lwsync
278; PPC64LE-NEXT: stw 4, 0(3)
279; PPC64LE-NEXT: blr
280 store atomic i32 %val, i32* %ptr release, align 4
281 ret void
282}
283
284define void @test27(i32* %ptr, i32 %val) {
285; PPC64LE-LABEL: test27:
286; PPC64LE: # BB#0:
287; PPC64LE-NEXT: sync
288; PPC64LE-NEXT: stw 4, 0(3)
289; PPC64LE-NEXT: blr
290 store atomic i32 %val, i32* %ptr seq_cst, align 4
291 ret void
292}
293
294define void @test28(i64* %ptr, i64 %val) {
295; PPC64LE-LABEL: test28:
296; PPC64LE: # BB#0:
297; PPC64LE-NEXT: std 4, 0(3)
298; PPC64LE-NEXT: blr
299 store atomic i64 %val, i64* %ptr unordered, align 8
300 ret void
301}
302
303define void @test29(i64* %ptr, i64 %val) {
304; PPC64LE-LABEL: test29:
305; PPC64LE: # BB#0:
306; PPC64LE-NEXT: std 4, 0(3)
307; PPC64LE-NEXT: blr
308 store atomic i64 %val, i64* %ptr monotonic, align 8
309 ret void
310}
311
312define void @test30(i64* %ptr, i64 %val) {
313; PPC64LE-LABEL: test30:
314; PPC64LE: # BB#0:
315; PPC64LE-NEXT: lwsync
316; PPC64LE-NEXT: std 4, 0(3)
317; PPC64LE-NEXT: blr
318 store atomic i64 %val, i64* %ptr release, align 8
319 ret void
320}
321
322define void @test31(i64* %ptr, i64 %val) {
323; PPC64LE-LABEL: test31:
324; PPC64LE: # BB#0:
325; PPC64LE-NEXT: sync
326; PPC64LE-NEXT: std 4, 0(3)
327; PPC64LE-NEXT: blr
328 store atomic i64 %val, i64* %ptr seq_cst, align 8
329 ret void
330}
331
332define void @test32() {
333; PPC64LE-LABEL: test32:
334; PPC64LE: # BB#0:
335; PPC64LE-NEXT: lwsync
336; PPC64LE-NEXT: blr
337 fence acquire
338 ret void
339}
340
341define void @test33() {
342; PPC64LE-LABEL: test33:
343; PPC64LE: # BB#0:
344; PPC64LE-NEXT: lwsync
345; PPC64LE-NEXT: blr
346 fence release
347 ret void
348}
349
350define void @test34() {
351; PPC64LE-LABEL: test34:
352; PPC64LE: # BB#0:
353; PPC64LE-NEXT: lwsync
354; PPC64LE-NEXT: blr
355 fence acq_rel
356 ret void
357}
358
359define void @test35() {
360; PPC64LE-LABEL: test35:
361; PPC64LE: # BB#0:
362; PPC64LE-NEXT: sync
363; PPC64LE-NEXT: blr
364 fence seq_cst
365 ret void
366}
367
368define void @test36() {
369; PPC64LE-LABEL: test36:
370; PPC64LE: # BB#0:
371; PPC64LE-NEXT: lwsync
372; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]373 fence syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]374 ret void
375}
376
377define void @test37() {
378; PPC64LE-LABEL: test37:
379; PPC64LE: # BB#0:
380; PPC64LE-NEXT: lwsync
381; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]382 fence syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]383 ret void
384}
385
386define void @test38() {
387; PPC64LE-LABEL: test38:
388; PPC64LE: # BB#0:
389; PPC64LE-NEXT: lwsync
390; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]391 fence syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]392 ret void
393}
394
395define void @test39() {
396; PPC64LE-LABEL: test39:
397; PPC64LE: # BB#0:
398; PPC64LE-NEXT: sync
399; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]400 fence syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]401 ret void
402}
403
404define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
405; PPC64LE-LABEL: test40:
406; PPC64LE: # BB#0:
407; PPC64LE-NEXT: b .LBB40_2
408; PPC64LE-NEXT: .p2align 5
409; PPC64LE-NEXT: .LBB40_1:
410; PPC64LE-NEXT: stbcx. 5, 0, 3
411; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]412; PPC64LE-NEXT: .LBB40_2:
413; PPC64LE-NEXT: lbarx 6, 0, 3
414; PPC64LE-NEXT: cmpw 4, 6
415; PPC64LE-NEXT: beq 0, .LBB40_1
416; PPC64LE-NEXT: # BB#3:
417; PPC64LE-NEXT: stbcx. 6, 0, 3
418; PPC64LE-NEXT: blr
419 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
420 ret void
421}
422
423define void @test41(i8* %ptr, i8 %cmp, i8 %val) {
424; PPC64LE-LABEL: test41:
425; PPC64LE: # BB#0:
426; PPC64LE-NEXT: .LBB41_1:
427; PPC64LE-NEXT: lbarx 6, 0, 3
428; PPC64LE-NEXT: cmpw 4, 6
429; PPC64LE-NEXT: bne 0, .LBB41_4
430; PPC64LE-NEXT: # BB#2:
431; PPC64LE-NEXT: stbcx. 5, 0, 3
432; PPC64LE-NEXT: bne 0, .LBB41_1
433; PPC64LE-NEXT: # BB#3:
434; PPC64LE-NEXT: lwsync
435; PPC64LE-NEXT: blr
436; PPC64LE-NEXT: .LBB41_4:
437; PPC64LE-NEXT: stbcx. 6, 0, 3
438; PPC64LE-NEXT: lwsync
439; PPC64LE-NEXT: blr
440 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic
441 ret void
442}
443
444define void @test42(i8* %ptr, i8 %cmp, i8 %val) {
445; PPC64LE-LABEL: test42:
446; PPC64LE: # BB#0:
447; PPC64LE-NEXT: .LBB42_1:
448; PPC64LE-NEXT: lbarx 6, 0, 3
449; PPC64LE-NEXT: cmpw 4, 6
450; PPC64LE-NEXT: bne 0, .LBB42_4
451; PPC64LE-NEXT: # BB#2:
452; PPC64LE-NEXT: stbcx. 5, 0, 3
453; PPC64LE-NEXT: bne 0, .LBB42_1
454; PPC64LE-NEXT: # BB#3:
455; PPC64LE-NEXT: lwsync
456; PPC64LE-NEXT: blr
457; PPC64LE-NEXT: .LBB42_4:
458; PPC64LE-NEXT: stbcx. 6, 0, 3
459; PPC64LE-NEXT: lwsync
460; PPC64LE-NEXT: blr
461 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire
462 ret void
463}
464
465define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
466; PPC64LE-LABEL: test43:
467; PPC64LE: # BB#0:
468; PPC64LE-NEXT: lwsync
469; PPC64LE-NEXT: b .LBB43_2
470; PPC64LE-NEXT: .p2align 5
471; PPC64LE-NEXT: .LBB43_1:
472; PPC64LE-NEXT: stbcx. 5, 0, 3
473; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]474; PPC64LE-NEXT: .LBB43_2:
475; PPC64LE-NEXT: lbarx 6, 0, 3
476; PPC64LE-NEXT: cmpw 4, 6
477; PPC64LE-NEXT: beq 0, .LBB43_1
478; PPC64LE-NEXT: # BB#3:
479; PPC64LE-NEXT: stbcx. 6, 0, 3
480; PPC64LE-NEXT: blr
481 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic
482 ret void
483}
484
485define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
486; PPC64LE-LABEL: test44:
487; PPC64LE: # BB#0:
488; PPC64LE-NEXT: lwsync
489; PPC64LE-NEXT: b .LBB44_2
490; PPC64LE-NEXT: .p2align 5
491; PPC64LE-NEXT: .LBB44_1:
492; PPC64LE-NEXT: stbcx. 5, 0, 3
493; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]494; PPC64LE-NEXT: .LBB44_2:
495; PPC64LE-NEXT: lbarx 6, 0, 3
496; PPC64LE-NEXT: cmpw 4, 6
497; PPC64LE-NEXT: beq 0, .LBB44_1
498; PPC64LE-NEXT: # BB#3:
499; PPC64LE-NEXT: stbcx. 6, 0, 3
500; PPC64LE-NEXT: blr
501 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire
502 ret void
503}
504
505define void @test45(i8* %ptr, i8 %cmp, i8 %val) {
506; PPC64LE-LABEL: test45:
507; PPC64LE: # BB#0:
508; PPC64LE-NEXT: lwsync
509; PPC64LE-NEXT: .LBB45_1:
510; PPC64LE-NEXT: lbarx 6, 0, 3
511; PPC64LE-NEXT: cmpw 4, 6
512; PPC64LE-NEXT: bne 0, .LBB45_4
513; PPC64LE-NEXT: # BB#2:
514; PPC64LE-NEXT: stbcx. 5, 0, 3
515; PPC64LE-NEXT: bne 0, .LBB45_1
516; PPC64LE-NEXT: # BB#3:
517; PPC64LE-NEXT: lwsync
518; PPC64LE-NEXT: blr
519; PPC64LE-NEXT: .LBB45_4:
520; PPC64LE-NEXT: stbcx. 6, 0, 3
521; PPC64LE-NEXT: lwsync
522; PPC64LE-NEXT: blr
523 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic
524 ret void
525}
526
527define void @test46(i8* %ptr, i8 %cmp, i8 %val) {
528; PPC64LE-LABEL: test46:
529; PPC64LE: # BB#0:
530; PPC64LE-NEXT: lwsync
531; PPC64LE-NEXT: .LBB46_1:
532; PPC64LE-NEXT: lbarx 6, 0, 3
533; PPC64LE-NEXT: cmpw 4, 6
534; PPC64LE-NEXT: bne 0, .LBB46_4
535; PPC64LE-NEXT: # BB#2:
536; PPC64LE-NEXT: stbcx. 5, 0, 3
537; PPC64LE-NEXT: bne 0, .LBB46_1
538; PPC64LE-NEXT: # BB#3:
539; PPC64LE-NEXT: lwsync
540; PPC64LE-NEXT: blr
541; PPC64LE-NEXT: .LBB46_4:
542; PPC64LE-NEXT: stbcx. 6, 0, 3
543; PPC64LE-NEXT: lwsync
544; PPC64LE-NEXT: blr
545 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire
546 ret void
547}
548
549define void @test47(i8* %ptr, i8 %cmp, i8 %val) {
550; PPC64LE-LABEL: test47:
551; PPC64LE: # BB#0:
552; PPC64LE-NEXT: sync
553; PPC64LE-NEXT: .LBB47_1:
554; PPC64LE-NEXT: lbarx 6, 0, 3
555; PPC64LE-NEXT: cmpw 4, 6
556; PPC64LE-NEXT: bne 0, .LBB47_4
557; PPC64LE-NEXT: # BB#2:
558; PPC64LE-NEXT: stbcx. 5, 0, 3
559; PPC64LE-NEXT: bne 0, .LBB47_1
560; PPC64LE-NEXT: # BB#3:
561; PPC64LE-NEXT: lwsync
562; PPC64LE-NEXT: blr
563; PPC64LE-NEXT: .LBB47_4:
564; PPC64LE-NEXT: stbcx. 6, 0, 3
565; PPC64LE-NEXT: lwsync
566; PPC64LE-NEXT: blr
567 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic
568 ret void
569}
570
571define void @test48(i8* %ptr, i8 %cmp, i8 %val) {
572; PPC64LE-LABEL: test48:
573; PPC64LE: # BB#0:
574; PPC64LE-NEXT: sync
575; PPC64LE-NEXT: .LBB48_1:
576; PPC64LE-NEXT: lbarx 6, 0, 3
577; PPC64LE-NEXT: cmpw 4, 6
578; PPC64LE-NEXT: bne 0, .LBB48_4
579; PPC64LE-NEXT: # BB#2:
580; PPC64LE-NEXT: stbcx. 5, 0, 3
581; PPC64LE-NEXT: bne 0, .LBB48_1
582; PPC64LE-NEXT: # BB#3:
583; PPC64LE-NEXT: lwsync
584; PPC64LE-NEXT: blr
585; PPC64LE-NEXT: .LBB48_4:
586; PPC64LE-NEXT: stbcx. 6, 0, 3
587; PPC64LE-NEXT: lwsync
588; PPC64LE-NEXT: blr
589 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire
590 ret void
591}
592
593define void @test49(i8* %ptr, i8 %cmp, i8 %val) {
594; PPC64LE-LABEL: test49:
595; PPC64LE: # BB#0:
596; PPC64LE-NEXT: sync
597; PPC64LE-NEXT: .LBB49_1:
598; PPC64LE-NEXT: lbarx 6, 0, 3
599; PPC64LE-NEXT: cmpw 4, 6
600; PPC64LE-NEXT: bne 0, .LBB49_4
601; PPC64LE-NEXT: # BB#2:
602; PPC64LE-NEXT: stbcx. 5, 0, 3
603; PPC64LE-NEXT: bne 0, .LBB49_1
604; PPC64LE-NEXT: # BB#3:
605; PPC64LE-NEXT: lwsync
606; PPC64LE-NEXT: blr
607; PPC64LE-NEXT: .LBB49_4:
608; PPC64LE-NEXT: stbcx. 6, 0, 3
609; PPC64LE-NEXT: lwsync
610; PPC64LE-NEXT: blr
611 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst
612 ret void
613}
614
615define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
616; PPC64LE-LABEL: test50:
617; PPC64LE: # BB#0:
618; PPC64LE-NEXT: b .LBB50_2
619; PPC64LE-NEXT: .p2align 5
620; PPC64LE-NEXT: .LBB50_1:
621; PPC64LE-NEXT: sthcx. 5, 0, 3
622; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]623; PPC64LE-NEXT: .LBB50_2:
624; PPC64LE-NEXT: lharx 6, 0, 3
625; PPC64LE-NEXT: cmpw 4, 6
626; PPC64LE-NEXT: beq 0, .LBB50_1
627; PPC64LE-NEXT: # BB#3:
628; PPC64LE-NEXT: sthcx. 6, 0, 3
629; PPC64LE-NEXT: blr
630 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic
631 ret void
632}
633
634define void @test51(i16* %ptr, i16 %cmp, i16 %val) {
635; PPC64LE-LABEL: test51:
636; PPC64LE: # BB#0:
637; PPC64LE-NEXT: .LBB51_1:
638; PPC64LE-NEXT: lharx 6, 0, 3
639; PPC64LE-NEXT: cmpw 4, 6
640; PPC64LE-NEXT: bne 0, .LBB51_4
641; PPC64LE-NEXT: # BB#2:
642; PPC64LE-NEXT: sthcx. 5, 0, 3
643; PPC64LE-NEXT: bne 0, .LBB51_1
644; PPC64LE-NEXT: # BB#3:
645; PPC64LE-NEXT: lwsync
646; PPC64LE-NEXT: blr
647; PPC64LE-NEXT: .LBB51_4:
648; PPC64LE-NEXT: sthcx. 6, 0, 3
649; PPC64LE-NEXT: lwsync
650; PPC64LE-NEXT: blr
651 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic
652 ret void
653}
654
655define void @test52(i16* %ptr, i16 %cmp, i16 %val) {
656; PPC64LE-LABEL: test52:
657; PPC64LE: # BB#0:
658; PPC64LE-NEXT: .LBB52_1:
659; PPC64LE-NEXT: lharx 6, 0, 3
660; PPC64LE-NEXT: cmpw 4, 6
661; PPC64LE-NEXT: bne 0, .LBB52_4
662; PPC64LE-NEXT: # BB#2:
663; PPC64LE-NEXT: sthcx. 5, 0, 3
664; PPC64LE-NEXT: bne 0, .LBB52_1
665; PPC64LE-NEXT: # BB#3:
666; PPC64LE-NEXT: lwsync
667; PPC64LE-NEXT: blr
668; PPC64LE-NEXT: .LBB52_4:
669; PPC64LE-NEXT: sthcx. 6, 0, 3
670; PPC64LE-NEXT: lwsync
671; PPC64LE-NEXT: blr
672 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire
673 ret void
674}
675
676define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
677; PPC64LE-LABEL: test53:
678; PPC64LE: # BB#0:
679; PPC64LE-NEXT: lwsync
680; PPC64LE-NEXT: b .LBB53_2
681; PPC64LE-NEXT: .p2align 5
682; PPC64LE-NEXT: .LBB53_1:
683; PPC64LE-NEXT: sthcx. 5, 0, 3
684; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]685; PPC64LE-NEXT: .LBB53_2:
686; PPC64LE-NEXT: lharx 6, 0, 3
687; PPC64LE-NEXT: cmpw 4, 6
688; PPC64LE-NEXT: beq 0, .LBB53_1
689; PPC64LE-NEXT: # BB#3:
690; PPC64LE-NEXT: sthcx. 6, 0, 3
691; PPC64LE-NEXT: blr
692 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic
693 ret void
694}
695
696define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
697; PPC64LE-LABEL: test54:
698; PPC64LE: # BB#0:
699; PPC64LE-NEXT: lwsync
700; PPC64LE-NEXT: b .LBB54_2
701; PPC64LE-NEXT: .p2align 5
702; PPC64LE-NEXT: .LBB54_1:
703; PPC64LE-NEXT: sthcx. 5, 0, 3
704; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]705; PPC64LE-NEXT: .LBB54_2:
706; PPC64LE-NEXT: lharx 6, 0, 3
707; PPC64LE-NEXT: cmpw 4, 6
708; PPC64LE-NEXT: beq 0, .LBB54_1
709; PPC64LE-NEXT: # BB#3:
710; PPC64LE-NEXT: sthcx. 6, 0, 3
711; PPC64LE-NEXT: blr
712 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire
713 ret void
714}
715
716define void @test55(i16* %ptr, i16 %cmp, i16 %val) {
717; PPC64LE-LABEL: test55:
718; PPC64LE: # BB#0:
719; PPC64LE-NEXT: lwsync
720; PPC64LE-NEXT: .LBB55_1:
721; PPC64LE-NEXT: lharx 6, 0, 3
722; PPC64LE-NEXT: cmpw 4, 6
723; PPC64LE-NEXT: bne 0, .LBB55_4
724; PPC64LE-NEXT: # BB#2:
725; PPC64LE-NEXT: sthcx. 5, 0, 3
726; PPC64LE-NEXT: bne 0, .LBB55_1
727; PPC64LE-NEXT: # BB#3:
728; PPC64LE-NEXT: lwsync
729; PPC64LE-NEXT: blr
730; PPC64LE-NEXT: .LBB55_4:
731; PPC64LE-NEXT: sthcx. 6, 0, 3
732; PPC64LE-NEXT: lwsync
733; PPC64LE-NEXT: blr
734 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic
735 ret void
736}
737
738define void @test56(i16* %ptr, i16 %cmp, i16 %val) {
739; PPC64LE-LABEL: test56:
740; PPC64LE: # BB#0:
741; PPC64LE-NEXT: lwsync
742; PPC64LE-NEXT: .LBB56_1:
743; PPC64LE-NEXT: lharx 6, 0, 3
744; PPC64LE-NEXT: cmpw 4, 6
745; PPC64LE-NEXT: bne 0, .LBB56_4
746; PPC64LE-NEXT: # BB#2:
747; PPC64LE-NEXT: sthcx. 5, 0, 3
748; PPC64LE-NEXT: bne 0, .LBB56_1
749; PPC64LE-NEXT: # BB#3:
750; PPC64LE-NEXT: lwsync
751; PPC64LE-NEXT: blr
752; PPC64LE-NEXT: .LBB56_4:
753; PPC64LE-NEXT: sthcx. 6, 0, 3
754; PPC64LE-NEXT: lwsync
755; PPC64LE-NEXT: blr
756 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire
757 ret void
758}
759
760define void @test57(i16* %ptr, i16 %cmp, i16 %val) {
761; PPC64LE-LABEL: test57:
762; PPC64LE: # BB#0:
763; PPC64LE-NEXT: sync
764; PPC64LE-NEXT: .LBB57_1:
765; PPC64LE-NEXT: lharx 6, 0, 3
766; PPC64LE-NEXT: cmpw 4, 6
767; PPC64LE-NEXT: bne 0, .LBB57_4
768; PPC64LE-NEXT: # BB#2:
769; PPC64LE-NEXT: sthcx. 5, 0, 3
770; PPC64LE-NEXT: bne 0, .LBB57_1
771; PPC64LE-NEXT: # BB#3:
772; PPC64LE-NEXT: lwsync
773; PPC64LE-NEXT: blr
774; PPC64LE-NEXT: .LBB57_4:
775; PPC64LE-NEXT: sthcx. 6, 0, 3
776; PPC64LE-NEXT: lwsync
777; PPC64LE-NEXT: blr
778 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic
779 ret void
780}
781
782define void @test58(i16* %ptr, i16 %cmp, i16 %val) {
783; PPC64LE-LABEL: test58:
784; PPC64LE: # BB#0:
785; PPC64LE-NEXT: sync
786; PPC64LE-NEXT: .LBB58_1:
787; PPC64LE-NEXT: lharx 6, 0, 3
788; PPC64LE-NEXT: cmpw 4, 6
789; PPC64LE-NEXT: bne 0, .LBB58_4
790; PPC64LE-NEXT: # BB#2:
791; PPC64LE-NEXT: sthcx. 5, 0, 3
792; PPC64LE-NEXT: bne 0, .LBB58_1
793; PPC64LE-NEXT: # BB#3:
794; PPC64LE-NEXT: lwsync
795; PPC64LE-NEXT: blr
796; PPC64LE-NEXT: .LBB58_4:
797; PPC64LE-NEXT: sthcx. 6, 0, 3
798; PPC64LE-NEXT: lwsync
799; PPC64LE-NEXT: blr
800 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire
801 ret void
802}
803
804define void @test59(i16* %ptr, i16 %cmp, i16 %val) {
805; PPC64LE-LABEL: test59:
806; PPC64LE: # BB#0:
807; PPC64LE-NEXT: sync
808; PPC64LE-NEXT: .LBB59_1:
809; PPC64LE-NEXT: lharx 6, 0, 3
810; PPC64LE-NEXT: cmpw 4, 6
811; PPC64LE-NEXT: bne 0, .LBB59_4
812; PPC64LE-NEXT: # BB#2:
813; PPC64LE-NEXT: sthcx. 5, 0, 3
814; PPC64LE-NEXT: bne 0, .LBB59_1
815; PPC64LE-NEXT: # BB#3:
816; PPC64LE-NEXT: lwsync
817; PPC64LE-NEXT: blr
818; PPC64LE-NEXT: .LBB59_4:
819; PPC64LE-NEXT: sthcx. 6, 0, 3
820; PPC64LE-NEXT: lwsync
821; PPC64LE-NEXT: blr
822 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst
823 ret void
824}
825
826define void @test60(i32* %ptr, i32 %cmp, i32 %val) {
827; PPC64LE-LABEL: test60:
828; PPC64LE: # BB#0:
829; PPC64LE-NEXT: b .LBB60_2
830; PPC64LE-NEXT: .p2align 5
831; PPC64LE-NEXT: .LBB60_1:
832; PPC64LE-NEXT: stwcx. 5, 0, 3
833; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]834; PPC64LE-NEXT: .LBB60_2:
835; PPC64LE-NEXT: lwarx 6, 0, 3
836; PPC64LE-NEXT: cmpw 4, 6
837; PPC64LE-NEXT: beq 0, .LBB60_1
838; PPC64LE-NEXT: # BB#3:
839; PPC64LE-NEXT: stwcx. 6, 0, 3
840; PPC64LE-NEXT: blr
841 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic
842 ret void
843}
844
845define void @test61(i32* %ptr, i32 %cmp, i32 %val) {
846; PPC64LE-LABEL: test61:
847; PPC64LE: # BB#0:
848; PPC64LE-NEXT: .LBB61_1:
849; PPC64LE-NEXT: lwarx 6, 0, 3
850; PPC64LE-NEXT: cmpw 4, 6
851; PPC64LE-NEXT: bne 0, .LBB61_4
852; PPC64LE-NEXT: # BB#2:
853; PPC64LE-NEXT: stwcx. 5, 0, 3
854; PPC64LE-NEXT: bne 0, .LBB61_1
855; PPC64LE-NEXT: # BB#3:
856; PPC64LE-NEXT: lwsync
857; PPC64LE-NEXT: blr
858; PPC64LE-NEXT: .LBB61_4:
859; PPC64LE-NEXT: stwcx. 6, 0, 3
860; PPC64LE-NEXT: lwsync
861; PPC64LE-NEXT: blr
862 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic
863 ret void
864}
865
866define void @test62(i32* %ptr, i32 %cmp, i32 %val) {
867; PPC64LE-LABEL: test62:
868; PPC64LE: # BB#0:
869; PPC64LE-NEXT: .LBB62_1:
870; PPC64LE-NEXT: lwarx 6, 0, 3
871; PPC64LE-NEXT: cmpw 4, 6
872; PPC64LE-NEXT: bne 0, .LBB62_4
873; PPC64LE-NEXT: # BB#2:
874; PPC64LE-NEXT: stwcx. 5, 0, 3
875; PPC64LE-NEXT: bne 0, .LBB62_1
876; PPC64LE-NEXT: # BB#3:
877; PPC64LE-NEXT: lwsync
878; PPC64LE-NEXT: blr
879; PPC64LE-NEXT: .LBB62_4:
880; PPC64LE-NEXT: stwcx. 6, 0, 3
881; PPC64LE-NEXT: lwsync
882; PPC64LE-NEXT: blr
883 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire
884 ret void
885}
886
887define void @test63(i32* %ptr, i32 %cmp, i32 %val) {
888; PPC64LE-LABEL: test63:
889; PPC64LE: # BB#0:
890; PPC64LE-NEXT: lwsync
891; PPC64LE-NEXT: b .LBB63_2
892; PPC64LE-NEXT: .p2align 5
893; PPC64LE-NEXT: .LBB63_1:
894; PPC64LE-NEXT: stwcx. 5, 0, 3
895; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]896; PPC64LE-NEXT: .LBB63_2:
897; PPC64LE-NEXT: lwarx 6, 0, 3
898; PPC64LE-NEXT: cmpw 4, 6
899; PPC64LE-NEXT: beq 0, .LBB63_1
900; PPC64LE-NEXT: # BB#3:
901; PPC64LE-NEXT: stwcx. 6, 0, 3
902; PPC64LE-NEXT: blr
903 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic
904 ret void
905}
906
907define void @test64(i32* %ptr, i32 %cmp, i32 %val) {
908; PPC64LE-LABEL: test64:
909; PPC64LE: # BB#0:
910; PPC64LE-NEXT: lwsync
911; PPC64LE-NEXT: b .LBB64_2
912; PPC64LE-NEXT: .p2align 5
913; PPC64LE-NEXT: .LBB64_1:
914; PPC64LE-NEXT: stwcx. 5, 0, 3
915; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]916; PPC64LE-NEXT: .LBB64_2:
917; PPC64LE-NEXT: lwarx 6, 0, 3
918; PPC64LE-NEXT: cmpw 4, 6
919; PPC64LE-NEXT: beq 0, .LBB64_1
920; PPC64LE-NEXT: # BB#3:
921; PPC64LE-NEXT: stwcx. 6, 0, 3
922; PPC64LE-NEXT: blr
923 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire
924 ret void
925}
926
927define void @test65(i32* %ptr, i32 %cmp, i32 %val) {
928; PPC64LE-LABEL: test65:
929; PPC64LE: # BB#0:
930; PPC64LE-NEXT: lwsync
931; PPC64LE-NEXT: .LBB65_1:
932; PPC64LE-NEXT: lwarx 6, 0, 3
933; PPC64LE-NEXT: cmpw 4, 6
934; PPC64LE-NEXT: bne 0, .LBB65_4
935; PPC64LE-NEXT: # BB#2:
936; PPC64LE-NEXT: stwcx. 5, 0, 3
937; PPC64LE-NEXT: bne 0, .LBB65_1
938; PPC64LE-NEXT: # BB#3:
939; PPC64LE-NEXT: lwsync
940; PPC64LE-NEXT: blr
941; PPC64LE-NEXT: .LBB65_4:
942; PPC64LE-NEXT: stwcx. 6, 0, 3
943; PPC64LE-NEXT: lwsync
944; PPC64LE-NEXT: blr
945 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic
946 ret void
947}
948
949define void @test66(i32* %ptr, i32 %cmp, i32 %val) {
950; PPC64LE-LABEL: test66:
951; PPC64LE: # BB#0:
952; PPC64LE-NEXT: lwsync
953; PPC64LE-NEXT: .LBB66_1:
954; PPC64LE-NEXT: lwarx 6, 0, 3
955; PPC64LE-NEXT: cmpw 4, 6
956; PPC64LE-NEXT: bne 0, .LBB66_4
957; PPC64LE-NEXT: # BB#2:
958; PPC64LE-NEXT: stwcx. 5, 0, 3
959; PPC64LE-NEXT: bne 0, .LBB66_1
960; PPC64LE-NEXT: # BB#3:
961; PPC64LE-NEXT: lwsync
962; PPC64LE-NEXT: blr
963; PPC64LE-NEXT: .LBB66_4:
964; PPC64LE-NEXT: stwcx. 6, 0, 3
965; PPC64LE-NEXT: lwsync
966; PPC64LE-NEXT: blr
967 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire
968 ret void
969}
970
971define void @test67(i32* %ptr, i32 %cmp, i32 %val) {
972; PPC64LE-LABEL: test67:
973; PPC64LE: # BB#0:
974; PPC64LE-NEXT: sync
975; PPC64LE-NEXT: .LBB67_1:
976; PPC64LE-NEXT: lwarx 6, 0, 3
977; PPC64LE-NEXT: cmpw 4, 6
978; PPC64LE-NEXT: bne 0, .LBB67_4
979; PPC64LE-NEXT: # BB#2:
980; PPC64LE-NEXT: stwcx. 5, 0, 3
981; PPC64LE-NEXT: bne 0, .LBB67_1
982; PPC64LE-NEXT: # BB#3:
983; PPC64LE-NEXT: lwsync
984; PPC64LE-NEXT: blr
985; PPC64LE-NEXT: .LBB67_4:
986; PPC64LE-NEXT: stwcx. 6, 0, 3
987; PPC64LE-NEXT: lwsync
988; PPC64LE-NEXT: blr
989 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic
990 ret void
991}
992
993define void @test68(i32* %ptr, i32 %cmp, i32 %val) {
994; PPC64LE-LABEL: test68:
995; PPC64LE: # BB#0:
996; PPC64LE-NEXT: sync
997; PPC64LE-NEXT: .LBB68_1:
998; PPC64LE-NEXT: lwarx 6, 0, 3
999; PPC64LE-NEXT: cmpw 4, 6
1000; PPC64LE-NEXT: bne 0, .LBB68_4
1001; PPC64LE-NEXT: # BB#2:
1002; PPC64LE-NEXT: stwcx. 5, 0, 3
1003; PPC64LE-NEXT: bne 0, .LBB68_1
1004; PPC64LE-NEXT: # BB#3:
1005; PPC64LE-NEXT: lwsync
1006; PPC64LE-NEXT: blr
1007; PPC64LE-NEXT: .LBB68_4:
1008; PPC64LE-NEXT: stwcx. 6, 0, 3
1009; PPC64LE-NEXT: lwsync
1010; PPC64LE-NEXT: blr
1011 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire
1012 ret void
1013}
1014
1015define void @test69(i32* %ptr, i32 %cmp, i32 %val) {
1016; PPC64LE-LABEL: test69:
1017; PPC64LE: # BB#0:
1018; PPC64LE-NEXT: sync
1019; PPC64LE-NEXT: .LBB69_1:
1020; PPC64LE-NEXT: lwarx 6, 0, 3
1021; PPC64LE-NEXT: cmpw 4, 6
1022; PPC64LE-NEXT: bne 0, .LBB69_4
1023; PPC64LE-NEXT: # BB#2:
1024; PPC64LE-NEXT: stwcx. 5, 0, 3
1025; PPC64LE-NEXT: bne 0, .LBB69_1
1026; PPC64LE-NEXT: # BB#3:
1027; PPC64LE-NEXT: lwsync
1028; PPC64LE-NEXT: blr
1029; PPC64LE-NEXT: .LBB69_4:
1030; PPC64LE-NEXT: stwcx. 6, 0, 3
1031; PPC64LE-NEXT: lwsync
1032; PPC64LE-NEXT: blr
1033 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
1034 ret void
1035}
1036
1037define void @test70(i64* %ptr, i64 %cmp, i64 %val) {
1038; PPC64LE-LABEL: test70:
1039; PPC64LE: # BB#0:
1040; PPC64LE-NEXT: b .LBB70_2
1041; PPC64LE-NEXT: .p2align 5
1042; PPC64LE-NEXT: .LBB70_1:
1043; PPC64LE-NEXT: stdcx. 5, 0, 3
1044; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1045; PPC64LE-NEXT: .LBB70_2:
1046; PPC64LE-NEXT: ldarx 6, 0, 3
1047; PPC64LE-NEXT: cmpd 4, 6
1048; PPC64LE-NEXT: beq 0, .LBB70_1
1049; PPC64LE-NEXT: # BB#3:
1050; PPC64LE-NEXT: stdcx. 6, 0, 3
1051; PPC64LE-NEXT: blr
1052 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic
1053 ret void
1054}
1055
1056define void @test71(i64* %ptr, i64 %cmp, i64 %val) {
1057; PPC64LE-LABEL: test71:
1058; PPC64LE: # BB#0:
1059; PPC64LE-NEXT: .LBB71_1:
1060; PPC64LE-NEXT: ldarx 6, 0, 3
1061; PPC64LE-NEXT: cmpd 4, 6
1062; PPC64LE-NEXT: bne 0, .LBB71_4
1063; PPC64LE-NEXT: # BB#2:
1064; PPC64LE-NEXT: stdcx. 5, 0, 3
1065; PPC64LE-NEXT: bne 0, .LBB71_1
1066; PPC64LE-NEXT: # BB#3:
1067; PPC64LE-NEXT: lwsync
1068; PPC64LE-NEXT: blr
1069; PPC64LE-NEXT: .LBB71_4:
1070; PPC64LE-NEXT: stdcx. 6, 0, 3
1071; PPC64LE-NEXT: lwsync
1072; PPC64LE-NEXT: blr
1073 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic
1074 ret void
1075}
1076
1077define void @test72(i64* %ptr, i64 %cmp, i64 %val) {
1078; PPC64LE-LABEL: test72:
1079; PPC64LE: # BB#0:
1080; PPC64LE-NEXT: .LBB72_1:
1081; PPC64LE-NEXT: ldarx 6, 0, 3
1082; PPC64LE-NEXT: cmpd 4, 6
1083; PPC64LE-NEXT: bne 0, .LBB72_4
1084; PPC64LE-NEXT: # BB#2:
1085; PPC64LE-NEXT: stdcx. 5, 0, 3
1086; PPC64LE-NEXT: bne 0, .LBB72_1
1087; PPC64LE-NEXT: # BB#3:
1088; PPC64LE-NEXT: lwsync
1089; PPC64LE-NEXT: blr
1090; PPC64LE-NEXT: .LBB72_4:
1091; PPC64LE-NEXT: stdcx. 6, 0, 3
1092; PPC64LE-NEXT: lwsync
1093; PPC64LE-NEXT: blr
1094 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire
1095 ret void
1096}
1097
1098define void @test73(i64* %ptr, i64 %cmp, i64 %val) {
1099; PPC64LE-LABEL: test73:
1100; PPC64LE: # BB#0:
1101; PPC64LE-NEXT: lwsync
1102; PPC64LE-NEXT: b .LBB73_2
1103; PPC64LE-NEXT: .p2align 5
1104; PPC64LE-NEXT: .LBB73_1:
1105; PPC64LE-NEXT: stdcx. 5, 0, 3
1106; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1107; PPC64LE-NEXT: .LBB73_2:
1108; PPC64LE-NEXT: ldarx 6, 0, 3
1109; PPC64LE-NEXT: cmpd 4, 6
1110; PPC64LE-NEXT: beq 0, .LBB73_1
1111; PPC64LE-NEXT: # BB#3:
1112; PPC64LE-NEXT: stdcx. 6, 0, 3
1113; PPC64LE-NEXT: blr
1114 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic
1115 ret void
1116}
1117
1118define void @test74(i64* %ptr, i64 %cmp, i64 %val) {
1119; PPC64LE-LABEL: test74:
1120; PPC64LE: # BB#0:
1121; PPC64LE-NEXT: lwsync
1122; PPC64LE-NEXT: b .LBB74_2
1123; PPC64LE-NEXT: .p2align 5
1124; PPC64LE-NEXT: .LBB74_1:
1125; PPC64LE-NEXT: stdcx. 5, 0, 3
1126; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1127; PPC64LE-NEXT: .LBB74_2:
1128; PPC64LE-NEXT: ldarx 6, 0, 3
1129; PPC64LE-NEXT: cmpd 4, 6
1130; PPC64LE-NEXT: beq 0, .LBB74_1
1131; PPC64LE-NEXT: # BB#3:
1132; PPC64LE-NEXT: stdcx. 6, 0, 3
1133; PPC64LE-NEXT: blr
1134 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire
1135 ret void
1136}
1137
1138define void @test75(i64* %ptr, i64 %cmp, i64 %val) {
1139; PPC64LE-LABEL: test75:
1140; PPC64LE: # BB#0:
1141; PPC64LE-NEXT: lwsync
1142; PPC64LE-NEXT: .LBB75_1:
1143; PPC64LE-NEXT: ldarx 6, 0, 3
1144; PPC64LE-NEXT: cmpd 4, 6
1145; PPC64LE-NEXT: bne 0, .LBB75_4
1146; PPC64LE-NEXT: # BB#2:
1147; PPC64LE-NEXT: stdcx. 5, 0, 3
1148; PPC64LE-NEXT: bne 0, .LBB75_1
1149; PPC64LE-NEXT: # BB#3:
1150; PPC64LE-NEXT: lwsync
1151; PPC64LE-NEXT: blr
1152; PPC64LE-NEXT: .LBB75_4:
1153; PPC64LE-NEXT: stdcx. 6, 0, 3
1154; PPC64LE-NEXT: lwsync
1155; PPC64LE-NEXT: blr
1156 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic
1157 ret void
1158}
1159
1160define void @test76(i64* %ptr, i64 %cmp, i64 %val) {
1161; PPC64LE-LABEL: test76:
1162; PPC64LE: # BB#0:
1163; PPC64LE-NEXT: lwsync
1164; PPC64LE-NEXT: .LBB76_1:
1165; PPC64LE-NEXT: ldarx 6, 0, 3
1166; PPC64LE-NEXT: cmpd 4, 6
1167; PPC64LE-NEXT: bne 0, .LBB76_4
1168; PPC64LE-NEXT: # BB#2:
1169; PPC64LE-NEXT: stdcx. 5, 0, 3
1170; PPC64LE-NEXT: bne 0, .LBB76_1
1171; PPC64LE-NEXT: # BB#3:
1172; PPC64LE-NEXT: lwsync
1173; PPC64LE-NEXT: blr
1174; PPC64LE-NEXT: .LBB76_4:
1175; PPC64LE-NEXT: stdcx. 6, 0, 3
1176; PPC64LE-NEXT: lwsync
1177; PPC64LE-NEXT: blr
1178 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire
1179 ret void
1180}
1181
1182define void @test77(i64* %ptr, i64 %cmp, i64 %val) {
1183; PPC64LE-LABEL: test77:
1184; PPC64LE: # BB#0:
1185; PPC64LE-NEXT: sync
1186; PPC64LE-NEXT: .LBB77_1:
1187; PPC64LE-NEXT: ldarx 6, 0, 3
1188; PPC64LE-NEXT: cmpd 4, 6
1189; PPC64LE-NEXT: bne 0, .LBB77_4
1190; PPC64LE-NEXT: # BB#2:
1191; PPC64LE-NEXT: stdcx. 5, 0, 3
1192; PPC64LE-NEXT: bne 0, .LBB77_1
1193; PPC64LE-NEXT: # BB#3:
1194; PPC64LE-NEXT: lwsync
1195; PPC64LE-NEXT: blr
1196; PPC64LE-NEXT: .LBB77_4:
1197; PPC64LE-NEXT: stdcx. 6, 0, 3
1198; PPC64LE-NEXT: lwsync
1199; PPC64LE-NEXT: blr
1200 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic
1201 ret void
1202}
1203
1204define void @test78(i64* %ptr, i64 %cmp, i64 %val) {
1205; PPC64LE-LABEL: test78:
1206; PPC64LE: # BB#0:
1207; PPC64LE-NEXT: sync
1208; PPC64LE-NEXT: .LBB78_1:
1209; PPC64LE-NEXT: ldarx 6, 0, 3
1210; PPC64LE-NEXT: cmpd 4, 6
1211; PPC64LE-NEXT: bne 0, .LBB78_4
1212; PPC64LE-NEXT: # BB#2:
1213; PPC64LE-NEXT: stdcx. 5, 0, 3
1214; PPC64LE-NEXT: bne 0, .LBB78_1
1215; PPC64LE-NEXT: # BB#3:
1216; PPC64LE-NEXT: lwsync
1217; PPC64LE-NEXT: blr
1218; PPC64LE-NEXT: .LBB78_4:
1219; PPC64LE-NEXT: stdcx. 6, 0, 3
1220; PPC64LE-NEXT: lwsync
1221; PPC64LE-NEXT: blr
1222 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire
1223 ret void
1224}
1225
1226define void @test79(i64* %ptr, i64 %cmp, i64 %val) {
1227; PPC64LE-LABEL: test79:
1228; PPC64LE: # BB#0:
1229; PPC64LE-NEXT: sync
1230; PPC64LE-NEXT: .LBB79_1:
1231; PPC64LE-NEXT: ldarx 6, 0, 3
1232; PPC64LE-NEXT: cmpd 4, 6
1233; PPC64LE-NEXT: bne 0, .LBB79_4
1234; PPC64LE-NEXT: # BB#2:
1235; PPC64LE-NEXT: stdcx. 5, 0, 3
1236; PPC64LE-NEXT: bne 0, .LBB79_1
1237; PPC64LE-NEXT: # BB#3:
1238; PPC64LE-NEXT: lwsync
1239; PPC64LE-NEXT: blr
1240; PPC64LE-NEXT: .LBB79_4:
1241; PPC64LE-NEXT: stdcx. 6, 0, 3
1242; PPC64LE-NEXT: lwsync
1243; PPC64LE-NEXT: blr
1244 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst
1245 ret void
1246}
1247
1248define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
1249; PPC64LE-LABEL: test80:
1250; PPC64LE: # BB#0:
1251; PPC64LE-NEXT: b .LBB80_2
1252; PPC64LE-NEXT: .p2align 5
1253; PPC64LE-NEXT: .LBB80_1:
1254; PPC64LE-NEXT: stbcx. 5, 0, 3
1255; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1256; PPC64LE-NEXT: .LBB80_2:
1257; PPC64LE-NEXT: lbarx 6, 0, 3
1258; PPC64LE-NEXT: cmpw 4, 6
1259; PPC64LE-NEXT: beq 0, .LBB80_1
1260; PPC64LE-NEXT: # BB#3:
1261; PPC64LE-NEXT: stbcx. 6, 0, 3
1262; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1263 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1264 ret void
1265}
1266
1267define void @test81(i8* %ptr, i8 %cmp, i8 %val) {
1268; PPC64LE-LABEL: test81:
1269; PPC64LE: # BB#0:
1270; PPC64LE-NEXT: .LBB81_1:
1271; PPC64LE-NEXT: lbarx 6, 0, 3
1272; PPC64LE-NEXT: cmpw 4, 6
1273; PPC64LE-NEXT: bne 0, .LBB81_4
1274; PPC64LE-NEXT: # BB#2:
1275; PPC64LE-NEXT: stbcx. 5, 0, 3
1276; PPC64LE-NEXT: bne 0, .LBB81_1
1277; PPC64LE-NEXT: # BB#3:
1278; PPC64LE-NEXT: lwsync
1279; PPC64LE-NEXT: blr
1280; PPC64LE-NEXT: .LBB81_4:
1281; PPC64LE-NEXT: stbcx. 6, 0, 3
1282; PPC64LE-NEXT: lwsync
1283; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1284 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1285 ret void
1286}
1287
1288define void @test82(i8* %ptr, i8 %cmp, i8 %val) {
1289; PPC64LE-LABEL: test82:
1290; PPC64LE: # BB#0:
1291; PPC64LE-NEXT: .LBB82_1:
1292; PPC64LE-NEXT: lbarx 6, 0, 3
1293; PPC64LE-NEXT: cmpw 4, 6
1294; PPC64LE-NEXT: bne 0, .LBB82_4
1295; PPC64LE-NEXT: # BB#2:
1296; PPC64LE-NEXT: stbcx. 5, 0, 3
1297; PPC64LE-NEXT: bne 0, .LBB82_1
1298; PPC64LE-NEXT: # BB#3:
1299; PPC64LE-NEXT: lwsync
1300; PPC64LE-NEXT: blr
1301; PPC64LE-NEXT: .LBB82_4:
1302; PPC64LE-NEXT: stbcx. 6, 0, 3
1303; PPC64LE-NEXT: lwsync
1304; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1305 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1306 ret void
1307}
1308
1309define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
1310; PPC64LE-LABEL: test83:
1311; PPC64LE: # BB#0:
1312; PPC64LE-NEXT: lwsync
1313; PPC64LE-NEXT: b .LBB83_2
1314; PPC64LE-NEXT: .p2align 5
1315; PPC64LE-NEXT: .LBB83_1:
1316; PPC64LE-NEXT: stbcx. 5, 0, 3
1317; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1318; PPC64LE-NEXT: .LBB83_2:
1319; PPC64LE-NEXT: lbarx 6, 0, 3
1320; PPC64LE-NEXT: cmpw 4, 6
1321; PPC64LE-NEXT: beq 0, .LBB83_1
1322; PPC64LE-NEXT: # BB#3:
1323; PPC64LE-NEXT: stbcx. 6, 0, 3
1324; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1325 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1326 ret void
1327}
1328
1329define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
1330; PPC64LE-LABEL: test84:
1331; PPC64LE: # BB#0:
1332; PPC64LE-NEXT: lwsync
1333; PPC64LE-NEXT: b .LBB84_2
1334; PPC64LE-NEXT: .p2align 5
1335; PPC64LE-NEXT: .LBB84_1:
1336; PPC64LE-NEXT: stbcx. 5, 0, 3
1337; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1338; PPC64LE-NEXT: .LBB84_2:
1339; PPC64LE-NEXT: lbarx 6, 0, 3
1340; PPC64LE-NEXT: cmpw 4, 6
1341; PPC64LE-NEXT: beq 0, .LBB84_1
1342; PPC64LE-NEXT: # BB#3:
1343; PPC64LE-NEXT: stbcx. 6, 0, 3
1344; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1345 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1346 ret void
1347}
1348
1349define void @test85(i8* %ptr, i8 %cmp, i8 %val) {
1350; PPC64LE-LABEL: test85:
1351; PPC64LE: # BB#0:
1352; PPC64LE-NEXT: lwsync
1353; PPC64LE-NEXT: .LBB85_1:
1354; PPC64LE-NEXT: lbarx 6, 0, 3
1355; PPC64LE-NEXT: cmpw 4, 6
1356; PPC64LE-NEXT: bne 0, .LBB85_4
1357; PPC64LE-NEXT: # BB#2:
1358; PPC64LE-NEXT: stbcx. 5, 0, 3
1359; PPC64LE-NEXT: bne 0, .LBB85_1
1360; PPC64LE-NEXT: # BB#3:
1361; PPC64LE-NEXT: lwsync
1362; PPC64LE-NEXT: blr
1363; PPC64LE-NEXT: .LBB85_4:
1364; PPC64LE-NEXT: stbcx. 6, 0, 3
1365; PPC64LE-NEXT: lwsync
1366; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1367 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1368 ret void
1369}
1370
1371define void @test86(i8* %ptr, i8 %cmp, i8 %val) {
1372; PPC64LE-LABEL: test86:
1373; PPC64LE: # BB#0:
1374; PPC64LE-NEXT: lwsync
1375; PPC64LE-NEXT: .LBB86_1:
1376; PPC64LE-NEXT: lbarx 6, 0, 3
1377; PPC64LE-NEXT: cmpw 4, 6
1378; PPC64LE-NEXT: bne 0, .LBB86_4
1379; PPC64LE-NEXT: # BB#2:
1380; PPC64LE-NEXT: stbcx. 5, 0, 3
1381; PPC64LE-NEXT: bne 0, .LBB86_1
1382; PPC64LE-NEXT: # BB#3:
1383; PPC64LE-NEXT: lwsync
1384; PPC64LE-NEXT: blr
1385; PPC64LE-NEXT: .LBB86_4:
1386; PPC64LE-NEXT: stbcx. 6, 0, 3
1387; PPC64LE-NEXT: lwsync
1388; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1389 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1390 ret void
1391}
1392
1393define void @test87(i8* %ptr, i8 %cmp, i8 %val) {
1394; PPC64LE-LABEL: test87:
1395; PPC64LE: # BB#0:
1396; PPC64LE-NEXT: sync
1397; PPC64LE-NEXT: .LBB87_1:
1398; PPC64LE-NEXT: lbarx 6, 0, 3
1399; PPC64LE-NEXT: cmpw 4, 6
1400; PPC64LE-NEXT: bne 0, .LBB87_4
1401; PPC64LE-NEXT: # BB#2:
1402; PPC64LE-NEXT: stbcx. 5, 0, 3
1403; PPC64LE-NEXT: bne 0, .LBB87_1
1404; PPC64LE-NEXT: # BB#3:
1405; PPC64LE-NEXT: lwsync
1406; PPC64LE-NEXT: blr
1407; PPC64LE-NEXT: .LBB87_4:
1408; PPC64LE-NEXT: stbcx. 6, 0, 3
1409; PPC64LE-NEXT: lwsync
1410; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1411 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1412 ret void
1413}
1414
1415define void @test88(i8* %ptr, i8 %cmp, i8 %val) {
1416; PPC64LE-LABEL: test88:
1417; PPC64LE: # BB#0:
1418; PPC64LE-NEXT: sync
1419; PPC64LE-NEXT: .LBB88_1:
1420; PPC64LE-NEXT: lbarx 6, 0, 3
1421; PPC64LE-NEXT: cmpw 4, 6
1422; PPC64LE-NEXT: bne 0, .LBB88_4
1423; PPC64LE-NEXT: # BB#2:
1424; PPC64LE-NEXT: stbcx. 5, 0, 3
1425; PPC64LE-NEXT: bne 0, .LBB88_1
1426; PPC64LE-NEXT: # BB#3:
1427; PPC64LE-NEXT: lwsync
1428; PPC64LE-NEXT: blr
1429; PPC64LE-NEXT: .LBB88_4:
1430; PPC64LE-NEXT: stbcx. 6, 0, 3
1431; PPC64LE-NEXT: lwsync
1432; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1433 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1434 ret void
1435}
1436
1437define void @test89(i8* %ptr, i8 %cmp, i8 %val) {
1438; PPC64LE-LABEL: test89:
1439; PPC64LE: # BB#0:
1440; PPC64LE-NEXT: sync
1441; PPC64LE-NEXT: .LBB89_1:
1442; PPC64LE-NEXT: lbarx 6, 0, 3
1443; PPC64LE-NEXT: cmpw 4, 6
1444; PPC64LE-NEXT: bne 0, .LBB89_4
1445; PPC64LE-NEXT: # BB#2:
1446; PPC64LE-NEXT: stbcx. 5, 0, 3
1447; PPC64LE-NEXT: bne 0, .LBB89_1
1448; PPC64LE-NEXT: # BB#3:
1449; PPC64LE-NEXT: lwsync
1450; PPC64LE-NEXT: blr
1451; PPC64LE-NEXT: .LBB89_4:
1452; PPC64LE-NEXT: stbcx. 6, 0, 3
1453; PPC64LE-NEXT: lwsync
1454; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1455 %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1456 ret void
1457}
1458
1459define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
1460; PPC64LE-LABEL: test90:
1461; PPC64LE: # BB#0:
1462; PPC64LE-NEXT: b .LBB90_2
1463; PPC64LE-NEXT: .p2align 5
1464; PPC64LE-NEXT: .LBB90_1:
1465; PPC64LE-NEXT: sthcx. 5, 0, 3
1466; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1467; PPC64LE-NEXT: .LBB90_2:
1468; PPC64LE-NEXT: lharx 6, 0, 3
1469; PPC64LE-NEXT: cmpw 4, 6
1470; PPC64LE-NEXT: beq 0, .LBB90_1
1471; PPC64LE-NEXT: # BB#3:
1472; PPC64LE-NEXT: sthcx. 6, 0, 3
1473; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1474 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1475 ret void
1476}
1477
1478define void @test91(i16* %ptr, i16 %cmp, i16 %val) {
1479; PPC64LE-LABEL: test91:
1480; PPC64LE: # BB#0:
1481; PPC64LE-NEXT: .LBB91_1:
1482; PPC64LE-NEXT: lharx 6, 0, 3
1483; PPC64LE-NEXT: cmpw 4, 6
1484; PPC64LE-NEXT: bne 0, .LBB91_4
1485; PPC64LE-NEXT: # BB#2:
1486; PPC64LE-NEXT: sthcx. 5, 0, 3
1487; PPC64LE-NEXT: bne 0, .LBB91_1
1488; PPC64LE-NEXT: # BB#3:
1489; PPC64LE-NEXT: lwsync
1490; PPC64LE-NEXT: blr
1491; PPC64LE-NEXT: .LBB91_4:
1492; PPC64LE-NEXT: sthcx. 6, 0, 3
1493; PPC64LE-NEXT: lwsync
1494; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1495 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1496 ret void
1497}
1498
1499define void @test92(i16* %ptr, i16 %cmp, i16 %val) {
1500; PPC64LE-LABEL: test92:
1501; PPC64LE: # BB#0:
1502; PPC64LE-NEXT: .LBB92_1:
1503; PPC64LE-NEXT: lharx 6, 0, 3
1504; PPC64LE-NEXT: cmpw 4, 6
1505; PPC64LE-NEXT: bne 0, .LBB92_4
1506; PPC64LE-NEXT: # BB#2:
1507; PPC64LE-NEXT: sthcx. 5, 0, 3
1508; PPC64LE-NEXT: bne 0, .LBB92_1
1509; PPC64LE-NEXT: # BB#3:
1510; PPC64LE-NEXT: lwsync
1511; PPC64LE-NEXT: blr
1512; PPC64LE-NEXT: .LBB92_4:
1513; PPC64LE-NEXT: sthcx. 6, 0, 3
1514; PPC64LE-NEXT: lwsync
1515; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1516 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1517 ret void
1518}
1519
1520define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
1521; PPC64LE-LABEL: test93:
1522; PPC64LE: # BB#0:
1523; PPC64LE-NEXT: lwsync
1524; PPC64LE-NEXT: b .LBB93_2
1525; PPC64LE-NEXT: .p2align 5
1526; PPC64LE-NEXT: .LBB93_1:
1527; PPC64LE-NEXT: sthcx. 5, 0, 3
1528; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1529; PPC64LE-NEXT: .LBB93_2:
1530; PPC64LE-NEXT: lharx 6, 0, 3
1531; PPC64LE-NEXT: cmpw 4, 6
1532; PPC64LE-NEXT: beq 0, .LBB93_1
1533; PPC64LE-NEXT: # BB#3:
1534; PPC64LE-NEXT: sthcx. 6, 0, 3
1535; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1536 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1537 ret void
1538}
1539
1540define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
1541; PPC64LE-LABEL: test94:
1542; PPC64LE: # BB#0:
1543; PPC64LE-NEXT: lwsync
1544; PPC64LE-NEXT: b .LBB94_2
1545; PPC64LE-NEXT: .p2align 5
1546; PPC64LE-NEXT: .LBB94_1:
1547; PPC64LE-NEXT: sthcx. 5, 0, 3
1548; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1549; PPC64LE-NEXT: .LBB94_2:
1550; PPC64LE-NEXT: lharx 6, 0, 3
1551; PPC64LE-NEXT: cmpw 4, 6
1552; PPC64LE-NEXT: beq 0, .LBB94_1
1553; PPC64LE-NEXT: # BB#3:
1554; PPC64LE-NEXT: sthcx. 6, 0, 3
1555; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1556 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1557 ret void
1558}
1559
1560define void @test95(i16* %ptr, i16 %cmp, i16 %val) {
1561; PPC64LE-LABEL: test95:
1562; PPC64LE: # BB#0:
1563; PPC64LE-NEXT: lwsync
1564; PPC64LE-NEXT: .LBB95_1:
1565; PPC64LE-NEXT: lharx 6, 0, 3
1566; PPC64LE-NEXT: cmpw 4, 6
1567; PPC64LE-NEXT: bne 0, .LBB95_4
1568; PPC64LE-NEXT: # BB#2:
1569; PPC64LE-NEXT: sthcx. 5, 0, 3
1570; PPC64LE-NEXT: bne 0, .LBB95_1
1571; PPC64LE-NEXT: # BB#3:
1572; PPC64LE-NEXT: lwsync
1573; PPC64LE-NEXT: blr
1574; PPC64LE-NEXT: .LBB95_4:
1575; PPC64LE-NEXT: sthcx. 6, 0, 3
1576; PPC64LE-NEXT: lwsync
1577; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1578 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1579 ret void
1580}
1581
1582define void @test96(i16* %ptr, i16 %cmp, i16 %val) {
1583; PPC64LE-LABEL: test96:
1584; PPC64LE: # BB#0:
1585; PPC64LE-NEXT: lwsync
1586; PPC64LE-NEXT: .LBB96_1:
1587; PPC64LE-NEXT: lharx 6, 0, 3
1588; PPC64LE-NEXT: cmpw 4, 6
1589; PPC64LE-NEXT: bne 0, .LBB96_4
1590; PPC64LE-NEXT: # BB#2:
1591; PPC64LE-NEXT: sthcx. 5, 0, 3
1592; PPC64LE-NEXT: bne 0, .LBB96_1
1593; PPC64LE-NEXT: # BB#3:
1594; PPC64LE-NEXT: lwsync
1595; PPC64LE-NEXT: blr
1596; PPC64LE-NEXT: .LBB96_4:
1597; PPC64LE-NEXT: sthcx. 6, 0, 3
1598; PPC64LE-NEXT: lwsync
1599; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1600 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1601 ret void
1602}
1603
1604define void @test97(i16* %ptr, i16 %cmp, i16 %val) {
1605; PPC64LE-LABEL: test97:
1606; PPC64LE: # BB#0:
1607; PPC64LE-NEXT: sync
1608; PPC64LE-NEXT: .LBB97_1:
1609; PPC64LE-NEXT: lharx 6, 0, 3
1610; PPC64LE-NEXT: cmpw 4, 6
1611; PPC64LE-NEXT: bne 0, .LBB97_4
1612; PPC64LE-NEXT: # BB#2:
1613; PPC64LE-NEXT: sthcx. 5, 0, 3
1614; PPC64LE-NEXT: bne 0, .LBB97_1
1615; PPC64LE-NEXT: # BB#3:
1616; PPC64LE-NEXT: lwsync
1617; PPC64LE-NEXT: blr
1618; PPC64LE-NEXT: .LBB97_4:
1619; PPC64LE-NEXT: sthcx. 6, 0, 3
1620; PPC64LE-NEXT: lwsync
1621; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1622 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1623 ret void
1624}
1625
1626define void @test98(i16* %ptr, i16 %cmp, i16 %val) {
1627; PPC64LE-LABEL: test98:
1628; PPC64LE: # BB#0:
1629; PPC64LE-NEXT: sync
1630; PPC64LE-NEXT: .LBB98_1:
1631; PPC64LE-NEXT: lharx 6, 0, 3
1632; PPC64LE-NEXT: cmpw 4, 6
1633; PPC64LE-NEXT: bne 0, .LBB98_4
1634; PPC64LE-NEXT: # BB#2:
1635; PPC64LE-NEXT: sthcx. 5, 0, 3
1636; PPC64LE-NEXT: bne 0, .LBB98_1
1637; PPC64LE-NEXT: # BB#3:
1638; PPC64LE-NEXT: lwsync
1639; PPC64LE-NEXT: blr
1640; PPC64LE-NEXT: .LBB98_4:
1641; PPC64LE-NEXT: sthcx. 6, 0, 3
1642; PPC64LE-NEXT: lwsync
1643; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1644 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1645 ret void
1646}
1647
1648define void @test99(i16* %ptr, i16 %cmp, i16 %val) {
1649; PPC64LE-LABEL: test99:
1650; PPC64LE: # BB#0:
1651; PPC64LE-NEXT: sync
1652; PPC64LE-NEXT: .LBB99_1:
1653; PPC64LE-NEXT: lharx 6, 0, 3
1654; PPC64LE-NEXT: cmpw 4, 6
1655; PPC64LE-NEXT: bne 0, .LBB99_4
1656; PPC64LE-NEXT: # BB#2:
1657; PPC64LE-NEXT: sthcx. 5, 0, 3
1658; PPC64LE-NEXT: bne 0, .LBB99_1
1659; PPC64LE-NEXT: # BB#3:
1660; PPC64LE-NEXT: lwsync
1661; PPC64LE-NEXT: blr
1662; PPC64LE-NEXT: .LBB99_4:
1663; PPC64LE-NEXT: sthcx. 6, 0, 3
1664; PPC64LE-NEXT: lwsync
1665; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1666 %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1667 ret void
1668}
1669
1670define void @test100(i32* %ptr, i32 %cmp, i32 %val) {
1671; PPC64LE-LABEL: test100:
1672; PPC64LE: # BB#0:
1673; PPC64LE-NEXT: b .LBB100_2
1674; PPC64LE-NEXT: .p2align 5
1675; PPC64LE-NEXT: .LBB100_1:
1676; PPC64LE-NEXT: stwcx. 5, 0, 3
1677; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1678; PPC64LE-NEXT: .LBB100_2:
1679; PPC64LE-NEXT: lwarx 6, 0, 3
1680; PPC64LE-NEXT: cmpw 4, 6
1681; PPC64LE-NEXT: beq 0, .LBB100_1
1682; PPC64LE-NEXT: # BB#3:
1683; PPC64LE-NEXT: stwcx. 6, 0, 3
1684; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1685 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") monotonic monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1686 ret void
1687}
1688
1689define void @test101(i32* %ptr, i32 %cmp, i32 %val) {
1690; PPC64LE-LABEL: test101:
1691; PPC64LE: # BB#0:
1692; PPC64LE-NEXT: .LBB101_1:
1693; PPC64LE-NEXT: lwarx 6, 0, 3
1694; PPC64LE-NEXT: cmpw 4, 6
1695; PPC64LE-NEXT: bne 0, .LBB101_4
1696; PPC64LE-NEXT: # BB#2:
1697; PPC64LE-NEXT: stwcx. 5, 0, 3
1698; PPC64LE-NEXT: bne 0, .LBB101_1
1699; PPC64LE-NEXT: # BB#3:
1700; PPC64LE-NEXT: lwsync
1701; PPC64LE-NEXT: blr
1702; PPC64LE-NEXT: .LBB101_4:
1703; PPC64LE-NEXT: stwcx. 6, 0, 3
1704; PPC64LE-NEXT: lwsync
1705; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1706 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acquire monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1707 ret void
1708}
1709
1710define void @test102(i32* %ptr, i32 %cmp, i32 %val) {
1711; PPC64LE-LABEL: test102:
1712; PPC64LE: # BB#0:
1713; PPC64LE-NEXT: .LBB102_1:
1714; PPC64LE-NEXT: lwarx 6, 0, 3
1715; PPC64LE-NEXT: cmpw 4, 6
1716; PPC64LE-NEXT: bne 0, .LBB102_4
1717; PPC64LE-NEXT: # BB#2:
1718; PPC64LE-NEXT: stwcx. 5, 0, 3
1719; PPC64LE-NEXT: bne 0, .LBB102_1
1720; PPC64LE-NEXT: # BB#3:
1721; PPC64LE-NEXT: lwsync
1722; PPC64LE-NEXT: blr
1723; PPC64LE-NEXT: .LBB102_4:
1724; PPC64LE-NEXT: stwcx. 6, 0, 3
1725; PPC64LE-NEXT: lwsync
1726; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1727 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acquire acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1728 ret void
1729}
1730
1731define void @test103(i32* %ptr, i32 %cmp, i32 %val) {
1732; PPC64LE-LABEL: test103:
1733; PPC64LE: # BB#0:
1734; PPC64LE-NEXT: lwsync
1735; PPC64LE-NEXT: b .LBB103_2
1736; PPC64LE-NEXT: .p2align 5
1737; PPC64LE-NEXT: .LBB103_1:
1738; PPC64LE-NEXT: stwcx. 5, 0, 3
1739; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1740; PPC64LE-NEXT: .LBB103_2:
1741; PPC64LE-NEXT: lwarx 6, 0, 3
1742; PPC64LE-NEXT: cmpw 4, 6
1743; PPC64LE-NEXT: beq 0, .LBB103_1
1744; PPC64LE-NEXT: # BB#3:
1745; PPC64LE-NEXT: stwcx. 6, 0, 3
1746; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1747 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1748 ret void
1749}
1750
1751define void @test104(i32* %ptr, i32 %cmp, i32 %val) {
1752; PPC64LE-LABEL: test104:
1753; PPC64LE: # BB#0:
1754; PPC64LE-NEXT: lwsync
1755; PPC64LE-NEXT: b .LBB104_2
1756; PPC64LE-NEXT: .p2align 5
1757; PPC64LE-NEXT: .LBB104_1:
1758; PPC64LE-NEXT: stwcx. 5, 0, 3
1759; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1760; PPC64LE-NEXT: .LBB104_2:
1761; PPC64LE-NEXT: lwarx 6, 0, 3
1762; PPC64LE-NEXT: cmpw 4, 6
1763; PPC64LE-NEXT: beq 0, .LBB104_1
1764; PPC64LE-NEXT: # BB#3:
1765; PPC64LE-NEXT: stwcx. 6, 0, 3
1766; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1767 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") release acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1768 ret void
1769}
1770
1771define void @test105(i32* %ptr, i32 %cmp, i32 %val) {
1772; PPC64LE-LABEL: test105:
1773; PPC64LE: # BB#0:
1774; PPC64LE-NEXT: lwsync
1775; PPC64LE-NEXT: .LBB105_1:
1776; PPC64LE-NEXT: lwarx 6, 0, 3
1777; PPC64LE-NEXT: cmpw 4, 6
1778; PPC64LE-NEXT: bne 0, .LBB105_4
1779; PPC64LE-NEXT: # BB#2:
1780; PPC64LE-NEXT: stwcx. 5, 0, 3
1781; PPC64LE-NEXT: bne 0, .LBB105_1
1782; PPC64LE-NEXT: # BB#3:
1783; PPC64LE-NEXT: lwsync
1784; PPC64LE-NEXT: blr
1785; PPC64LE-NEXT: .LBB105_4:
1786; PPC64LE-NEXT: stwcx. 6, 0, 3
1787; PPC64LE-NEXT: lwsync
1788; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1789 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acq_rel monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1790 ret void
1791}
1792
1793define void @test106(i32* %ptr, i32 %cmp, i32 %val) {
1794; PPC64LE-LABEL: test106:
1795; PPC64LE: # BB#0:
1796; PPC64LE-NEXT: lwsync
1797; PPC64LE-NEXT: .LBB106_1:
1798; PPC64LE-NEXT: lwarx 6, 0, 3
1799; PPC64LE-NEXT: cmpw 4, 6
1800; PPC64LE-NEXT: bne 0, .LBB106_4
1801; PPC64LE-NEXT: # BB#2:
1802; PPC64LE-NEXT: stwcx. 5, 0, 3
1803; PPC64LE-NEXT: bne 0, .LBB106_1
1804; PPC64LE-NEXT: # BB#3:
1805; PPC64LE-NEXT: lwsync
1806; PPC64LE-NEXT: blr
1807; PPC64LE-NEXT: .LBB106_4:
1808; PPC64LE-NEXT: stwcx. 6, 0, 3
1809; PPC64LE-NEXT: lwsync
1810; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1811 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") acq_rel acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1812 ret void
1813}
1814
1815define void @test107(i32* %ptr, i32 %cmp, i32 %val) {
1816; PPC64LE-LABEL: test107:
1817; PPC64LE: # BB#0:
1818; PPC64LE-NEXT: sync
1819; PPC64LE-NEXT: .LBB107_1:
1820; PPC64LE-NEXT: lwarx 6, 0, 3
1821; PPC64LE-NEXT: cmpw 4, 6
1822; PPC64LE-NEXT: bne 0, .LBB107_4
1823; PPC64LE-NEXT: # BB#2:
1824; PPC64LE-NEXT: stwcx. 5, 0, 3
1825; PPC64LE-NEXT: bne 0, .LBB107_1
1826; PPC64LE-NEXT: # BB#3:
1827; PPC64LE-NEXT: lwsync
1828; PPC64LE-NEXT: blr
1829; PPC64LE-NEXT: .LBB107_4:
1830; PPC64LE-NEXT: stwcx. 6, 0, 3
1831; PPC64LE-NEXT: lwsync
1832; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1833 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1834 ret void
1835}
1836
1837define void @test108(i32* %ptr, i32 %cmp, i32 %val) {
1838; PPC64LE-LABEL: test108:
1839; PPC64LE: # BB#0:
1840; PPC64LE-NEXT: sync
1841; PPC64LE-NEXT: .LBB108_1:
1842; PPC64LE-NEXT: lwarx 6, 0, 3
1843; PPC64LE-NEXT: cmpw 4, 6
1844; PPC64LE-NEXT: bne 0, .LBB108_4
1845; PPC64LE-NEXT: # BB#2:
1846; PPC64LE-NEXT: stwcx. 5, 0, 3
1847; PPC64LE-NEXT: bne 0, .LBB108_1
1848; PPC64LE-NEXT: # BB#3:
1849; PPC64LE-NEXT: lwsync
1850; PPC64LE-NEXT: blr
1851; PPC64LE-NEXT: .LBB108_4:
1852; PPC64LE-NEXT: stwcx. 6, 0, 3
1853; PPC64LE-NEXT: lwsync
1854; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1855 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1856 ret void
1857}
1858
1859define void @test109(i32* %ptr, i32 %cmp, i32 %val) {
1860; PPC64LE-LABEL: test109:
1861; PPC64LE: # BB#0:
1862; PPC64LE-NEXT: sync
1863; PPC64LE-NEXT: .LBB109_1:
1864; PPC64LE-NEXT: lwarx 6, 0, 3
1865; PPC64LE-NEXT: cmpw 4, 6
1866; PPC64LE-NEXT: bne 0, .LBB109_4
1867; PPC64LE-NEXT: # BB#2:
1868; PPC64LE-NEXT: stwcx. 5, 0, 3
1869; PPC64LE-NEXT: bne 0, .LBB109_1
1870; PPC64LE-NEXT: # BB#3:
1871; PPC64LE-NEXT: lwsync
1872; PPC64LE-NEXT: blr
1873; PPC64LE-NEXT: .LBB109_4:
1874; PPC64LE-NEXT: stwcx. 6, 0, 3
1875; PPC64LE-NEXT: lwsync
1876; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1877 %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val syncscope("singlethread") seq_cst seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1878 ret void
1879}
1880
1881define void @test110(i64* %ptr, i64 %cmp, i64 %val) {
1882; PPC64LE-LABEL: test110:
1883; PPC64LE: # BB#0:
1884; PPC64LE-NEXT: b .LBB110_2
1885; PPC64LE-NEXT: .p2align 5
1886; PPC64LE-NEXT: .LBB110_1:
1887; PPC64LE-NEXT: stdcx. 5, 0, 3
1888; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1889; PPC64LE-NEXT: .LBB110_2:
1890; PPC64LE-NEXT: ldarx 6, 0, 3
1891; PPC64LE-NEXT: cmpd 4, 6
1892; PPC64LE-NEXT: beq 0, .LBB110_1
1893; PPC64LE-NEXT: # BB#3:
1894; PPC64LE-NEXT: stdcx. 6, 0, 3
1895; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1896 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") monotonic monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1897 ret void
1898}
1899
1900define void @test111(i64* %ptr, i64 %cmp, i64 %val) {
1901; PPC64LE-LABEL: test111:
1902; PPC64LE: # BB#0:
1903; PPC64LE-NEXT: .LBB111_1:
1904; PPC64LE-NEXT: ldarx 6, 0, 3
1905; PPC64LE-NEXT: cmpd 4, 6
1906; PPC64LE-NEXT: bne 0, .LBB111_4
1907; PPC64LE-NEXT: # BB#2:
1908; PPC64LE-NEXT: stdcx. 5, 0, 3
1909; PPC64LE-NEXT: bne 0, .LBB111_1
1910; PPC64LE-NEXT: # BB#3:
1911; PPC64LE-NEXT: lwsync
1912; PPC64LE-NEXT: blr
1913; PPC64LE-NEXT: .LBB111_4:
1914; PPC64LE-NEXT: stdcx. 6, 0, 3
1915; PPC64LE-NEXT: lwsync
1916; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1917 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acquire monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1918 ret void
1919}
1920
1921define void @test112(i64* %ptr, i64 %cmp, i64 %val) {
1922; PPC64LE-LABEL: test112:
1923; PPC64LE: # BB#0:
1924; PPC64LE-NEXT: .LBB112_1:
1925; PPC64LE-NEXT: ldarx 6, 0, 3
1926; PPC64LE-NEXT: cmpd 4, 6
1927; PPC64LE-NEXT: bne 0, .LBB112_4
1928; PPC64LE-NEXT: # BB#2:
1929; PPC64LE-NEXT: stdcx. 5, 0, 3
1930; PPC64LE-NEXT: bne 0, .LBB112_1
1931; PPC64LE-NEXT: # BB#3:
1932; PPC64LE-NEXT: lwsync
1933; PPC64LE-NEXT: blr
1934; PPC64LE-NEXT: .LBB112_4:
1935; PPC64LE-NEXT: stdcx. 6, 0, 3
1936; PPC64LE-NEXT: lwsync
1937; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1938 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acquire acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1939 ret void
1940}
1941
1942define void @test113(i64* %ptr, i64 %cmp, i64 %val) {
1943; PPC64LE-LABEL: test113:
1944; PPC64LE: # BB#0:
1945; PPC64LE-NEXT: lwsync
1946; PPC64LE-NEXT: b .LBB113_2
1947; PPC64LE-NEXT: .p2align 5
1948; PPC64LE-NEXT: .LBB113_1:
1949; PPC64LE-NEXT: stdcx. 5, 0, 3
1950; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1951; PPC64LE-NEXT: .LBB113_2:
1952; PPC64LE-NEXT: ldarx 6, 0, 3
1953; PPC64LE-NEXT: cmpd 4, 6
1954; PPC64LE-NEXT: beq 0, .LBB113_1
1955; PPC64LE-NEXT: # BB#3:
1956; PPC64LE-NEXT: stdcx. 6, 0, 3
1957; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1958 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1959 ret void
1960}
1961
1962define void @test114(i64* %ptr, i64 %cmp, i64 %val) {
1963; PPC64LE-LABEL: test114:
1964; PPC64LE: # BB#0:
1965; PPC64LE-NEXT: lwsync
1966; PPC64LE-NEXT: b .LBB114_2
1967; PPC64LE-NEXT: .p2align 5
1968; PPC64LE-NEXT: .LBB114_1:
1969; PPC64LE-NEXT: stdcx. 5, 0, 3
1970; PPC64LE-NEXT: beqlr 0
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1971; PPC64LE-NEXT: .LBB114_2:
1972; PPC64LE-NEXT: ldarx 6, 0, 3
1973; PPC64LE-NEXT: cmpd 4, 6
1974; PPC64LE-NEXT: beq 0, .LBB114_1
1975; PPC64LE-NEXT: # BB#3:
1976; PPC64LE-NEXT: stdcx. 6, 0, 3
1977; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]1978 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") release acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]1979 ret void
1980}
1981
1982define void @test115(i64* %ptr, i64 %cmp, i64 %val) {
1983; PPC64LE-LABEL: test115:
1984; PPC64LE: # BB#0:
1985; PPC64LE-NEXT: lwsync
1986; PPC64LE-NEXT: .LBB115_1:
1987; PPC64LE-NEXT: ldarx 6, 0, 3
1988; PPC64LE-NEXT: cmpd 4, 6
1989; PPC64LE-NEXT: bne 0, .LBB115_4
1990; PPC64LE-NEXT: # BB#2:
1991; PPC64LE-NEXT: stdcx. 5, 0, 3
1992; PPC64LE-NEXT: bne 0, .LBB115_1
1993; PPC64LE-NEXT: # BB#3:
1994; PPC64LE-NEXT: lwsync
1995; PPC64LE-NEXT: blr
1996; PPC64LE-NEXT: .LBB115_4:
1997; PPC64LE-NEXT: stdcx. 6, 0, 3
1998; PPC64LE-NEXT: lwsync
1999; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]2000 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acq_rel monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2001 ret void
2002}
2003
2004define void @test116(i64* %ptr, i64 %cmp, i64 %val) {
2005; PPC64LE-LABEL: test116:
2006; PPC64LE: # BB#0:
2007; PPC64LE-NEXT: lwsync
2008; PPC64LE-NEXT: .LBB116_1:
2009; PPC64LE-NEXT: ldarx 6, 0, 3
2010; PPC64LE-NEXT: cmpd 4, 6
2011; PPC64LE-NEXT: bne 0, .LBB116_4
2012; PPC64LE-NEXT: # BB#2:
2013; PPC64LE-NEXT: stdcx. 5, 0, 3
2014; PPC64LE-NEXT: bne 0, .LBB116_1
2015; PPC64LE-NEXT: # BB#3:
2016; PPC64LE-NEXT: lwsync
2017; PPC64LE-NEXT: blr
2018; PPC64LE-NEXT: .LBB116_4:
2019; PPC64LE-NEXT: stdcx. 6, 0, 3
2020; PPC64LE-NEXT: lwsync
2021; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]2022 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") acq_rel acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2023 ret void
2024}
2025
2026define void @test117(i64* %ptr, i64 %cmp, i64 %val) {
2027; PPC64LE-LABEL: test117:
2028; PPC64LE: # BB#0:
2029; PPC64LE-NEXT: sync
2030; PPC64LE-NEXT: .LBB117_1:
2031; PPC64LE-NEXT: ldarx 6, 0, 3
2032; PPC64LE-NEXT: cmpd 4, 6
2033; PPC64LE-NEXT: bne 0, .LBB117_4
2034; PPC64LE-NEXT: # BB#2:
2035; PPC64LE-NEXT: stdcx. 5, 0, 3
2036; PPC64LE-NEXT: bne 0, .LBB117_1
2037; PPC64LE-NEXT: # BB#3:
2038; PPC64LE-NEXT: lwsync
2039; PPC64LE-NEXT: blr
2040; PPC64LE-NEXT: .LBB117_4:
2041; PPC64LE-NEXT: stdcx. 6, 0, 3
2042; PPC64LE-NEXT: lwsync
2043; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]2044 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2045 ret void
2046}
2047
2048define void @test118(i64* %ptr, i64 %cmp, i64 %val) {
2049; PPC64LE-LABEL: test118:
2050; PPC64LE: # BB#0:
2051; PPC64LE-NEXT: sync
2052; PPC64LE-NEXT: .LBB118_1:
2053; PPC64LE-NEXT: ldarx 6, 0, 3
2054; PPC64LE-NEXT: cmpd 4, 6
2055; PPC64LE-NEXT: bne 0, .LBB118_4
2056; PPC64LE-NEXT: # BB#2:
2057; PPC64LE-NEXT: stdcx. 5, 0, 3
2058; PPC64LE-NEXT: bne 0, .LBB118_1
2059; PPC64LE-NEXT: # BB#3:
2060; PPC64LE-NEXT: lwsync
2061; PPC64LE-NEXT: blr
2062; PPC64LE-NEXT: .LBB118_4:
2063; PPC64LE-NEXT: stdcx. 6, 0, 3
2064; PPC64LE-NEXT: lwsync
2065; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]2066 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2067 ret void
2068}
2069
2070define void @test119(i64* %ptr, i64 %cmp, i64 %val) {
2071; PPC64LE-LABEL: test119:
2072; PPC64LE: # BB#0:
2073; PPC64LE-NEXT: sync
2074; PPC64LE-NEXT: .LBB119_1:
2075; PPC64LE-NEXT: ldarx 6, 0, 3
2076; PPC64LE-NEXT: cmpd 4, 6
2077; PPC64LE-NEXT: bne 0, .LBB119_4
2078; PPC64LE-NEXT: # BB#2:
2079; PPC64LE-NEXT: stdcx. 5, 0, 3
2080; PPC64LE-NEXT: bne 0, .LBB119_1
2081; PPC64LE-NEXT: # BB#3:
2082; PPC64LE-NEXT: lwsync
2083; PPC64LE-NEXT: blr
2084; PPC64LE-NEXT: .LBB119_4:
2085; PPC64LE-NEXT: stdcx. 6, 0, 3
2086; PPC64LE-NEXT: lwsync
2087; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]2088 %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val syncscope("singlethread") seq_cst seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]2089 ret void
2090}
2091
2092define i8 @test120(i8* %ptr, i8 %val) {
2093; PPC64LE-LABEL: test120:
2094; PPC64LE: # BB#0:
2095; PPC64LE-NEXT: .LBB120_1:
2096; PPC64LE-NEXT: lbarx 5, 0, 3
2097; PPC64LE-NEXT: stbcx. 4, 0, 3
2098; PPC64LE-NEXT: bne 0, .LBB120_1
2099; PPC64LE-NEXT: # BB#2:
2100; PPC64LE-NEXT: mr 3, 5
2101; PPC64LE-NEXT: blr
2102 %ret = atomicrmw xchg i8* %ptr, i8 %val monotonic
2103 ret i8 %ret
2104}
2105
2106define i8 @test121(i8* %ptr, i8 %val) {
2107; PPC64LE-LABEL: test121:
2108; PPC64LE: # BB#0:
2109; PPC64LE-NEXT: mr 5, 3
2110; PPC64LE-NEXT: .LBB121_1:
2111; PPC64LE-NEXT: lbarx 3, 0, 5
2112; PPC64LE-NEXT: stbcx. 4, 0, 5
2113; PPC64LE-NEXT: bne 0, .LBB121_1
2114; PPC64LE-NEXT: # BB#2:
2115; PPC64LE-NEXT: lwsync
2116; PPC64LE-NEXT: blr
2117 %ret = atomicrmw xchg i8* %ptr, i8 %val acquire
2118 ret i8 %ret
2119}
2120
2121define i8 @test122(i8* %ptr, i8 %val) {
2122; PPC64LE-LABEL: test122:
2123; PPC64LE: # BB#0:
2124; PPC64LE-NEXT: lwsync
2125; PPC64LE-NEXT: .LBB122_1:
2126; PPC64LE-NEXT: lbarx 5, 0, 3
2127; PPC64LE-NEXT: stbcx. 4, 0, 3
2128; PPC64LE-NEXT: bne 0, .LBB122_1
2129; PPC64LE-NEXT: # BB#2:
2130; PPC64LE-NEXT: mr 3, 5
2131; PPC64LE-NEXT: blr
2132 %ret = atomicrmw xchg i8* %ptr, i8 %val release
2133 ret i8 %ret
2134}
2135
2136define i8 @test123(i8* %ptr, i8 %val) {
2137; PPC64LE-LABEL: test123:
2138; PPC64LE: # BB#0:
2139; PPC64LE-NEXT: lwsync
2140; PPC64LE-NEXT: .LBB123_1:
2141; PPC64LE-NEXT: lbarx 5, 0, 3
2142; PPC64LE-NEXT: stbcx. 4, 0, 3
2143; PPC64LE-NEXT: bne 0, .LBB123_1
2144; PPC64LE-NEXT: # BB#2:
2145; PPC64LE-NEXT: mr 3, 5
2146; PPC64LE-NEXT: lwsync
2147; PPC64LE-NEXT: blr
2148 %ret = atomicrmw xchg i8* %ptr, i8 %val acq_rel
2149 ret i8 %ret
2150}
2151
2152define i8 @test124(i8* %ptr, i8 %val) {
2153; PPC64LE-LABEL: test124:
2154; PPC64LE: # BB#0:
2155; PPC64LE-NEXT: sync
2156; PPC64LE-NEXT: .LBB124_1:
2157; PPC64LE-NEXT: lbarx 5, 0, 3
2158; PPC64LE-NEXT: stbcx. 4, 0, 3
2159; PPC64LE-NEXT: bne 0, .LBB124_1
2160; PPC64LE-NEXT: # BB#2:
2161; PPC64LE-NEXT: mr 3, 5
2162; PPC64LE-NEXT: lwsync
2163; PPC64LE-NEXT: blr
2164 %ret = atomicrmw xchg i8* %ptr, i8 %val seq_cst
2165 ret i8 %ret
2166}
2167
2168define i16 @test125(i16* %ptr, i16 %val) {
2169; PPC64LE-LABEL: test125:
2170; PPC64LE: # BB#0:
2171; PPC64LE-NEXT: .LBB125_1:
2172; PPC64LE-NEXT: lharx 5, 0, 3
2173; PPC64LE-NEXT: sthcx. 4, 0, 3
2174; PPC64LE-NEXT: bne 0, .LBB125_1
2175; PPC64LE-NEXT: # BB#2:
2176; PPC64LE-NEXT: mr 3, 5
2177; PPC64LE-NEXT: blr
2178 %ret = atomicrmw xchg i16* %ptr, i16 %val monotonic
2179 ret i16 %ret
2180}
2181
2182define i16 @test126(i16* %ptr, i16 %val) {
2183; PPC64LE-LABEL: test126:
2184; PPC64LE: # BB#0:
2185; PPC64LE-NEXT: mr 5, 3
2186; PPC64LE-NEXT: .LBB126_1:
2187; PPC64LE-NEXT: lharx 3, 0, 5
2188; PPC64LE-NEXT: sthcx. 4, 0, 5
2189; PPC64LE-NEXT: bne 0, .LBB126_1
2190; PPC64LE-NEXT: # BB#2:
2191; PPC64LE-NEXT: lwsync
2192; PPC64LE-NEXT: blr
2193 %ret = atomicrmw xchg i16* %ptr, i16 %val acquire
2194 ret i16 %ret
2195}
2196
2197define i16 @test127(i16* %ptr, i16 %val) {
2198; PPC64LE-LABEL: test127:
2199; PPC64LE: # BB#0:
2200; PPC64LE-NEXT: lwsync
2201; PPC64LE-NEXT: .LBB127_1:
2202; PPC64LE-NEXT: lharx 5, 0, 3
2203; PPC64LE-NEXT: sthcx. 4, 0, 3
2204; PPC64LE-NEXT: bne 0, .LBB127_1
2205; PPC64LE-NEXT: # BB#2:
2206; PPC64LE-NEXT: mr 3, 5
2207; PPC64LE-NEXT: blr
2208 %ret = atomicrmw xchg i16* %ptr, i16 %val release
2209 ret i16 %ret
2210}
2211
2212define i16 @test128(i16* %ptr, i16 %val) {
2213; PPC64LE-LABEL: test128:
2214; PPC64LE: # BB#0:
2215; PPC64LE-NEXT: lwsync
2216; PPC64LE-NEXT: .LBB128_1:
2217; PPC64LE-NEXT: lharx 5, 0, 3
2218; PPC64LE-NEXT: sthcx. 4, 0, 3
2219; PPC64LE-NEXT: bne 0, .LBB128_1
2220; PPC64LE-NEXT: # BB#2:
2221; PPC64LE-NEXT: mr 3, 5
2222; PPC64LE-NEXT: lwsync
2223; PPC64LE-NEXT: blr
2224 %ret = atomicrmw xchg i16* %ptr, i16 %val acq_rel
2225 ret i16 %ret
2226}
2227
2228define i16 @test129(i16* %ptr, i16 %val) {
2229; PPC64LE-LABEL: test129:
2230; PPC64LE: # BB#0:
2231; PPC64LE-NEXT: sync
2232; PPC64LE-NEXT: .LBB129_1:
2233; PPC64LE-NEXT: lharx 5, 0, 3
2234; PPC64LE-NEXT: sthcx. 4, 0, 3
2235; PPC64LE-NEXT: bne 0, .LBB129_1
2236; PPC64LE-NEXT: # BB#2:
2237; PPC64LE-NEXT: mr 3, 5
2238; PPC64LE-NEXT: lwsync
2239; PPC64LE-NEXT: blr
2240 %ret = atomicrmw xchg i16* %ptr, i16 %val seq_cst
2241 ret i16 %ret
2242}
2243
2244define i32 @test130(i32* %ptr, i32 %val) {
2245; PPC64LE-LABEL: test130:
2246; PPC64LE: # BB#0:
2247; PPC64LE-NEXT: .LBB130_1:
2248; PPC64LE-NEXT: lwarx 5, 0, 3
2249; PPC64LE-NEXT: stwcx. 4, 0, 3
2250; PPC64LE-NEXT: bne 0, .LBB130_1
2251; PPC64LE-NEXT: # BB#2:
2252; PPC64LE-NEXT: mr 3, 5
2253; PPC64LE-NEXT: blr
2254 %ret = atomicrmw xchg i32* %ptr, i32 %val monotonic
2255 ret i32 %ret
2256}
2257
2258define i32 @test131(i32* %ptr, i32 %val) {
2259; PPC64LE-LABEL: test131:
2260; PPC64LE: # BB#0:
2261; PPC64LE-NEXT: mr 5, 3
2262; PPC64LE-NEXT: .LBB131_1:
2263; PPC64LE-NEXT: lwarx 3, 0, 5
2264; PPC64LE-NEXT: stwcx. 4, 0, 5
2265; PPC64LE-NEXT: bne 0, .LBB131_1
2266; PPC64LE-NEXT: # BB#2:
2267; PPC64LE-NEXT: lwsync
2268; PPC64LE-NEXT: blr
2269 %ret = atomicrmw xchg i32* %ptr, i32 %val acquire
2270 ret i32 %ret
2271}
2272
2273define i32 @test132(i32* %ptr, i32 %val) {
2274; PPC64LE-LABEL: test132:
2275; PPC64LE: # BB#0:
2276; PPC64LE-NEXT: lwsync
2277; PPC64LE-NEXT: .LBB132_1:
2278; PPC64LE-NEXT: lwarx 5, 0, 3
2279; PPC64LE-NEXT: stwcx. 4, 0, 3
2280; PPC64LE-NEXT: bne 0, .LBB132_1
2281; PPC64LE-NEXT: # BB#2:
2282; PPC64LE-NEXT: mr 3, 5
2283; PPC64LE-NEXT: blr
2284 %ret = atomicrmw xchg i32* %ptr, i32 %val release
2285 ret i32 %ret
2286}
2287
2288define i32 @test133(i32* %ptr, i32 %val) {
2289; PPC64LE-LABEL: test133:
2290; PPC64LE: # BB#0:
2291; PPC64LE-NEXT: lwsync
2292; PPC64LE-NEXT: .LBB133_1:
2293; PPC64LE-NEXT: lwarx 5, 0, 3
2294; PPC64LE-NEXT: stwcx. 4, 0, 3
2295; PPC64LE-NEXT: bne 0, .LBB133_1
2296; PPC64LE-NEXT: # BB#2:
2297; PPC64LE-NEXT: mr 3, 5
2298; PPC64LE-NEXT: lwsync
2299; PPC64LE-NEXT: blr
2300 %ret = atomicrmw xchg i32* %ptr, i32 %val acq_rel
2301 ret i32 %ret
2302}
2303
2304define i32 @test134(i32* %ptr, i32 %val) {
2305; PPC64LE-LABEL: test134:
2306; PPC64LE: # BB#0:
2307; PPC64LE-NEXT: sync
2308; PPC64LE-NEXT: .LBB134_1:
2309; PPC64LE-NEXT: lwarx 5, 0, 3
2310; PPC64LE-NEXT: stwcx. 4, 0, 3
2311; PPC64LE-NEXT: bne 0, .LBB134_1
2312; PPC64LE-NEXT: # BB#2:
2313; PPC64LE-NEXT: mr 3, 5
2314; PPC64LE-NEXT: lwsync
2315; PPC64LE-NEXT: blr
2316 %ret = atomicrmw xchg i32* %ptr, i32 %val seq_cst
2317 ret i32 %ret
2318}
2319
2320define i64 @test135(i64* %ptr, i64 %val) {
2321; PPC64LE-LABEL: test135:
2322; PPC64LE: # BB#0:
2323; PPC64LE-NEXT: .LBB135_1:
2324; PPC64LE-NEXT: ldarx 5, 0, 3
2325; PPC64LE-NEXT: stdcx. 4, 0, 3
2326; PPC64LE-NEXT: bne 0, .LBB135_1
2327; PPC64LE-NEXT: # BB#2:
2328; PPC64LE-NEXT: mr 3, 5
2329; PPC64LE-NEXT: blr
2330 %ret = atomicrmw xchg i64* %ptr, i64 %val monotonic
2331 ret i64 %ret
2332}
2333
2334define i64 @test136(i64* %ptr, i64 %val) {
2335; PPC64LE-LABEL: test136:
2336; PPC64LE: # BB#0:
2337; PPC64LE-NEXT: mr 5, 3
2338; PPC64LE-NEXT: .LBB136_1:
2339; PPC64LE-NEXT: ldarx 3, 0, 5
2340; PPC64LE-NEXT: stdcx. 4, 0, 5
2341; PPC64LE-NEXT: bne 0, .LBB136_1
2342; PPC64LE-NEXT: # BB#2:
2343; PPC64LE-NEXT: lwsync
2344; PPC64LE-NEXT: blr
2345 %ret = atomicrmw xchg i64* %ptr, i64 %val acquire
2346 ret i64 %ret
2347}
2348
2349define i64 @test137(i64* %ptr, i64 %val) {
2350; PPC64LE-LABEL: test137:
2351; PPC64LE: # BB#0:
2352; PPC64LE-NEXT: lwsync
2353; PPC64LE-NEXT: .LBB137_1:
2354; PPC64LE-NEXT: ldarx 5, 0, 3
2355; PPC64LE-NEXT: stdcx. 4, 0, 3
2356; PPC64LE-NEXT: bne 0, .LBB137_1
2357; PPC64LE-NEXT: # BB#2:
2358; PPC64LE-NEXT: mr 3, 5
2359; PPC64LE-NEXT: blr
2360 %ret = atomicrmw xchg i64* %ptr, i64 %val release
2361 ret i64 %ret
2362}
2363
2364define i64 @test138(i64* %ptr, i64 %val) {
2365; PPC64LE-LABEL: test138:
2366; PPC64LE: # BB#0:
2367; PPC64LE-NEXT: lwsync
2368; PPC64LE-NEXT: .LBB138_1:
2369; PPC64LE-NEXT: ldarx 5, 0, 3
2370; PPC64LE-NEXT: stdcx. 4, 0, 3
2371; PPC64LE-NEXT: bne 0, .LBB138_1
2372; PPC64LE-NEXT: # BB#2:
2373; PPC64LE-NEXT: mr 3, 5
2374; PPC64LE-NEXT: lwsync
2375; PPC64LE-NEXT: blr
2376 %ret = atomicrmw xchg i64* %ptr, i64 %val acq_rel
2377 ret i64 %ret
2378}
2379
2380define i64 @test139(i64* %ptr, i64 %val) {
2381; PPC64LE-LABEL: test139:
2382; PPC64LE: # BB#0:
2383; PPC64LE-NEXT: sync
2384; PPC64LE-NEXT: .LBB139_1:
2385; PPC64LE-NEXT: ldarx 5, 0, 3
2386; PPC64LE-NEXT: stdcx. 4, 0, 3
2387; PPC64LE-NEXT: bne 0, .LBB139_1
2388; PPC64LE-NEXT: # BB#2:
2389; PPC64LE-NEXT: mr 3, 5
2390; PPC64LE-NEXT: lwsync
2391; PPC64LE-NEXT: blr
2392 %ret = atomicrmw xchg i64* %ptr, i64 %val seq_cst
2393 ret i64 %ret
2394}
2395
2396define i8 @test140(i8* %ptr, i8 %val) {
2397; PPC64LE-LABEL: test140:
2398; PPC64LE: # BB#0:
2399; PPC64LE-NEXT: .LBB140_1:
2400; PPC64LE-NEXT: lbarx 5, 0, 3
2401; PPC64LE-NEXT: add 6, 4, 5
2402; PPC64LE-NEXT: stbcx. 6, 0, 3
2403; PPC64LE-NEXT: bne 0, .LBB140_1
2404; PPC64LE-NEXT: # BB#2:
2405; PPC64LE-NEXT: mr 3, 5
2406; PPC64LE-NEXT: blr
2407 %ret = atomicrmw add i8* %ptr, i8 %val monotonic
2408 ret i8 %ret
2409}
2410
2411define i8 @test141(i8* %ptr, i8 %val) {
2412; PPC64LE-LABEL: test141:
2413; PPC64LE: # BB#0:
2414; PPC64LE-NEXT: mr 5, 3
2415; PPC64LE-NEXT: .LBB141_1:
2416; PPC64LE-NEXT: lbarx 3, 0, 5
2417; PPC64LE-NEXT: add 6, 4, 3
2418; PPC64LE-NEXT: stbcx. 6, 0, 5
2419; PPC64LE-NEXT: bne 0, .LBB141_1
2420; PPC64LE-NEXT: # BB#2:
2421; PPC64LE-NEXT: lwsync
2422; PPC64LE-NEXT: blr
2423 %ret = atomicrmw add i8* %ptr, i8 %val acquire
2424 ret i8 %ret
2425}
2426
2427define i8 @test142(i8* %ptr, i8 %val) {
2428; PPC64LE-LABEL: test142:
2429; PPC64LE: # BB#0:
2430; PPC64LE-NEXT: lwsync
2431; PPC64LE-NEXT: .LBB142_1:
2432; PPC64LE-NEXT: lbarx 5, 0, 3
2433; PPC64LE-NEXT: add 6, 4, 5
2434; PPC64LE-NEXT: stbcx. 6, 0, 3
2435; PPC64LE-NEXT: bne 0, .LBB142_1
2436; PPC64LE-NEXT: # BB#2:
2437; PPC64LE-NEXT: mr 3, 5
2438; PPC64LE-NEXT: blr
2439 %ret = atomicrmw add i8* %ptr, i8 %val release
2440 ret i8 %ret
2441}
2442
2443define i8 @test143(i8* %ptr, i8 %val) {
2444; PPC64LE-LABEL: test143:
2445; PPC64LE: # BB#0:
2446; PPC64LE-NEXT: lwsync
2447; PPC64LE-NEXT: .LBB143_1:
2448; PPC64LE-NEXT: lbarx 5, 0, 3
2449; PPC64LE-NEXT: add 6, 4, 5
2450; PPC64LE-NEXT: stbcx. 6, 0, 3
2451; PPC64LE-NEXT: bne 0, .LBB143_1
2452; PPC64LE-NEXT: # BB#2:
2453; PPC64LE-NEXT: mr 3, 5
2454; PPC64LE-NEXT: lwsync
2455; PPC64LE-NEXT: blr
2456 %ret = atomicrmw add i8* %ptr, i8 %val acq_rel
2457 ret i8 %ret
2458}
2459
2460define i8 @test144(i8* %ptr, i8 %val) {
2461; PPC64LE-LABEL: test144:
2462; PPC64LE: # BB#0:
2463; PPC64LE-NEXT: sync
2464; PPC64LE-NEXT: .LBB144_1:
2465; PPC64LE-NEXT: lbarx 5, 0, 3
2466; PPC64LE-NEXT: add 6, 4, 5
2467; PPC64LE-NEXT: stbcx. 6, 0, 3
2468; PPC64LE-NEXT: bne 0, .LBB144_1
2469; PPC64LE-NEXT: # BB#2:
2470; PPC64LE-NEXT: mr 3, 5
2471; PPC64LE-NEXT: lwsync
2472; PPC64LE-NEXT: blr
2473 %ret = atomicrmw add i8* %ptr, i8 %val seq_cst
2474 ret i8 %ret
2475}
2476
2477define i16 @test145(i16* %ptr, i16 %val) {
2478; PPC64LE-LABEL: test145:
2479; PPC64LE: # BB#0:
2480; PPC64LE-NEXT: .LBB145_1:
2481; PPC64LE-NEXT: lharx 5, 0, 3
2482; PPC64LE-NEXT: add 6, 4, 5
2483; PPC64LE-NEXT: sthcx. 6, 0, 3
2484; PPC64LE-NEXT: bne 0, .LBB145_1
2485; PPC64LE-NEXT: # BB#2:
2486; PPC64LE-NEXT: mr 3, 5
2487; PPC64LE-NEXT: blr
2488 %ret = atomicrmw add i16* %ptr, i16 %val monotonic
2489 ret i16 %ret
2490}
2491
2492define i16 @test146(i16* %ptr, i16 %val) {
2493; PPC64LE-LABEL: test146:
2494; PPC64LE: # BB#0:
2495; PPC64LE-NEXT: mr 5, 3
2496; PPC64LE-NEXT: .LBB146_1:
2497; PPC64LE-NEXT: lharx 3, 0, 5
2498; PPC64LE-NEXT: add 6, 4, 3
2499; PPC64LE-NEXT: sthcx. 6, 0, 5
2500; PPC64LE-NEXT: bne 0, .LBB146_1
2501; PPC64LE-NEXT: # BB#2:
2502; PPC64LE-NEXT: lwsync
2503; PPC64LE-NEXT: blr
2504 %ret = atomicrmw add i16* %ptr, i16 %val acquire
2505 ret i16 %ret
2506}
2507
2508define i16 @test147(i16* %ptr, i16 %val) {
2509; PPC64LE-LABEL: test147:
2510; PPC64LE: # BB#0:
2511; PPC64LE-NEXT: lwsync
2512; PPC64LE-NEXT: .LBB147_1:
2513; PPC64LE-NEXT: lharx 5, 0, 3
2514; PPC64LE-NEXT: add 6, 4, 5
2515; PPC64LE-NEXT: sthcx. 6, 0, 3
2516; PPC64LE-NEXT: bne 0, .LBB147_1
2517; PPC64LE-NEXT: # BB#2:
2518; PPC64LE-NEXT: mr 3, 5
2519; PPC64LE-NEXT: blr
2520 %ret = atomicrmw add i16* %ptr, i16 %val release
2521 ret i16 %ret
2522}
2523
2524define i16 @test148(i16* %ptr, i16 %val) {
2525; PPC64LE-LABEL: test148:
2526; PPC64LE: # BB#0:
2527; PPC64LE-NEXT: lwsync
2528; PPC64LE-NEXT: .LBB148_1:
2529; PPC64LE-NEXT: lharx 5, 0, 3
2530; PPC64LE-NEXT: add 6, 4, 5
2531; PPC64LE-NEXT: sthcx. 6, 0, 3
2532; PPC64LE-NEXT: bne 0, .LBB148_1
2533; PPC64LE-NEXT: # BB#2:
2534; PPC64LE-NEXT: mr 3, 5
2535; PPC64LE-NEXT: lwsync
2536; PPC64LE-NEXT: blr
2537 %ret = atomicrmw add i16* %ptr, i16 %val acq_rel
2538 ret i16 %ret
2539}
2540
2541define i16 @test149(i16* %ptr, i16 %val) {
2542; PPC64LE-LABEL: test149:
2543; PPC64LE: # BB#0:
2544; PPC64LE-NEXT: sync
2545; PPC64LE-NEXT: .LBB149_1:
2546; PPC64LE-NEXT: lharx 5, 0, 3
2547; PPC64LE-NEXT: add 6, 4, 5
2548; PPC64LE-NEXT: sthcx. 6, 0, 3
2549; PPC64LE-NEXT: bne 0, .LBB149_1
2550; PPC64LE-NEXT: # BB#2:
2551; PPC64LE-NEXT: mr 3, 5
2552; PPC64LE-NEXT: lwsync
2553; PPC64LE-NEXT: blr
2554 %ret = atomicrmw add i16* %ptr, i16 %val seq_cst
2555 ret i16 %ret
2556}
2557
2558define i32 @test150(i32* %ptr, i32 %val) {
2559; PPC64LE-LABEL: test150:
2560; PPC64LE: # BB#0:
2561; PPC64LE-NEXT: .LBB150_1:
2562; PPC64LE-NEXT: lwarx 5, 0, 3
2563; PPC64LE-NEXT: add 6, 4, 5
2564; PPC64LE-NEXT: stwcx. 6, 0, 3
2565; PPC64LE-NEXT: bne 0, .LBB150_1
2566; PPC64LE-NEXT: # BB#2:
2567; PPC64LE-NEXT: mr 3, 5
2568; PPC64LE-NEXT: blr
2569 %ret = atomicrmw add i32* %ptr, i32 %val monotonic
2570 ret i32 %ret
2571}
2572
2573define i32 @test151(i32* %ptr, i32 %val) {
2574; PPC64LE-LABEL: test151:
2575; PPC64LE: # BB#0:
2576; PPC64LE-NEXT: mr 5, 3
2577; PPC64LE-NEXT: .LBB151_1:
2578; PPC64LE-NEXT: lwarx 3, 0, 5
2579; PPC64LE-NEXT: add 6, 4, 3
2580; PPC64LE-NEXT: stwcx. 6, 0, 5
2581; PPC64LE-NEXT: bne 0, .LBB151_1
2582; PPC64LE-NEXT: # BB#2:
2583; PPC64LE-NEXT: lwsync
2584; PPC64LE-NEXT: blr
2585 %ret = atomicrmw add i32* %ptr, i32 %val acquire
2586 ret i32 %ret
2587}
2588
2589define i32 @test152(i32* %ptr, i32 %val) {
2590; PPC64LE-LABEL: test152:
2591; PPC64LE: # BB#0:
2592; PPC64LE-NEXT: lwsync
2593; PPC64LE-NEXT: .LBB152_1:
2594; PPC64LE-NEXT: lwarx 5, 0, 3
2595; PPC64LE-NEXT: add 6, 4, 5
2596; PPC64LE-NEXT: stwcx. 6, 0, 3
2597; PPC64LE-NEXT: bne 0, .LBB152_1
2598; PPC64LE-NEXT: # BB#2:
2599; PPC64LE-NEXT: mr 3, 5
2600; PPC64LE-NEXT: blr
2601 %ret = atomicrmw add i32* %ptr, i32 %val release
2602 ret i32 %ret
2603}
2604
2605define i32 @test153(i32* %ptr, i32 %val) {
2606; PPC64LE-LABEL: test153:
2607; PPC64LE: # BB#0:
2608; PPC64LE-NEXT: lwsync
2609; PPC64LE-NEXT: .LBB153_1:
2610; PPC64LE-NEXT: lwarx 5, 0, 3
2611; PPC64LE-NEXT: add 6, 4, 5
2612; PPC64LE-NEXT: stwcx. 6, 0, 3
2613; PPC64LE-NEXT: bne 0, .LBB153_1
2614; PPC64LE-NEXT: # BB#2:
2615; PPC64LE-NEXT: mr 3, 5
2616; PPC64LE-NEXT: lwsync
2617; PPC64LE-NEXT: blr
2618 %ret = atomicrmw add i32* %ptr, i32 %val acq_rel
2619 ret i32 %ret
2620}
2621
2622define i32 @test154(i32* %ptr, i32 %val) {
2623; PPC64LE-LABEL: test154:
2624; PPC64LE: # BB#0:
2625; PPC64LE-NEXT: sync
2626; PPC64LE-NEXT: .LBB154_1:
2627; PPC64LE-NEXT: lwarx 5, 0, 3
2628; PPC64LE-NEXT: add 6, 4, 5
2629; PPC64LE-NEXT: stwcx. 6, 0, 3
2630; PPC64LE-NEXT: bne 0, .LBB154_1
2631; PPC64LE-NEXT: # BB#2:
2632; PPC64LE-NEXT: mr 3, 5
2633; PPC64LE-NEXT: lwsync
2634; PPC64LE-NEXT: blr
2635 %ret = atomicrmw add i32* %ptr, i32 %val seq_cst
2636 ret i32 %ret
2637}
2638
2639define i64 @test155(i64* %ptr, i64 %val) {
2640; PPC64LE-LABEL: test155:
2641; PPC64LE: # BB#0:
2642; PPC64LE-NEXT: .LBB155_1:
2643; PPC64LE-NEXT: ldarx 5, 0, 3
2644; PPC64LE-NEXT: add 6, 4, 5
2645; PPC64LE-NEXT: stdcx. 6, 0, 3
2646; PPC64LE-NEXT: bne 0, .LBB155_1
2647; PPC64LE-NEXT: # BB#2:
2648; PPC64LE-NEXT: mr 3, 5
2649; PPC64LE-NEXT: blr
2650 %ret = atomicrmw add i64* %ptr, i64 %val monotonic
2651 ret i64 %ret
2652}
2653
2654define i64 @test156(i64* %ptr, i64 %val) {
2655; PPC64LE-LABEL: test156:
2656; PPC64LE: # BB#0:
2657; PPC64LE-NEXT: mr 5, 3
2658; PPC64LE-NEXT: .LBB156_1:
2659; PPC64LE-NEXT: ldarx 3, 0, 5
2660; PPC64LE-NEXT: add 6, 4, 3
2661; PPC64LE-NEXT: stdcx. 6, 0, 5
2662; PPC64LE-NEXT: bne 0, .LBB156_1
2663; PPC64LE-NEXT: # BB#2:
2664; PPC64LE-NEXT: lwsync
2665; PPC64LE-NEXT: blr
2666 %ret = atomicrmw add i64* %ptr, i64 %val acquire
2667 ret i64 %ret
2668}
2669
2670define i64 @test157(i64* %ptr, i64 %val) {
2671; PPC64LE-LABEL: test157:
2672; PPC64LE: # BB#0:
2673; PPC64LE-NEXT: lwsync
2674; PPC64LE-NEXT: .LBB157_1:
2675; PPC64LE-NEXT: ldarx 5, 0, 3
2676; PPC64LE-NEXT: add 6, 4, 5
2677; PPC64LE-NEXT: stdcx. 6, 0, 3
2678; PPC64LE-NEXT: bne 0, .LBB157_1
2679; PPC64LE-NEXT: # BB#2:
2680; PPC64LE-NEXT: mr 3, 5
2681; PPC64LE-NEXT: blr
2682 %ret = atomicrmw add i64* %ptr, i64 %val release
2683 ret i64 %ret
2684}
2685
2686define i64 @test158(i64* %ptr, i64 %val) {
2687; PPC64LE-LABEL: test158:
2688; PPC64LE: # BB#0:
2689; PPC64LE-NEXT: lwsync
2690; PPC64LE-NEXT: .LBB158_1:
2691; PPC64LE-NEXT: ldarx 5, 0, 3
2692; PPC64LE-NEXT: add 6, 4, 5
2693; PPC64LE-NEXT: stdcx. 6, 0, 3
2694; PPC64LE-NEXT: bne 0, .LBB158_1
2695; PPC64LE-NEXT: # BB#2:
2696; PPC64LE-NEXT: mr 3, 5
2697; PPC64LE-NEXT: lwsync
2698; PPC64LE-NEXT: blr
2699 %ret = atomicrmw add i64* %ptr, i64 %val acq_rel
2700 ret i64 %ret
2701}
2702
2703define i64 @test159(i64* %ptr, i64 %val) {
2704; PPC64LE-LABEL: test159:
2705; PPC64LE: # BB#0:
2706; PPC64LE-NEXT: sync
2707; PPC64LE-NEXT: .LBB159_1:
2708; PPC64LE-NEXT: ldarx 5, 0, 3
2709; PPC64LE-NEXT: add 6, 4, 5
2710; PPC64LE-NEXT: stdcx. 6, 0, 3
2711; PPC64LE-NEXT: bne 0, .LBB159_1
2712; PPC64LE-NEXT: # BB#2:
2713; PPC64LE-NEXT: mr 3, 5
2714; PPC64LE-NEXT: lwsync
2715; PPC64LE-NEXT: blr
2716 %ret = atomicrmw add i64* %ptr, i64 %val seq_cst
2717 ret i64 %ret
2718}
2719
2720define i8 @test160(i8* %ptr, i8 %val) {
2721; PPC64LE-LABEL: test160:
2722; PPC64LE: # BB#0:
2723; PPC64LE-NEXT: .LBB160_1:
2724; PPC64LE-NEXT: lbarx 5, 0, 3
2725; PPC64LE-NEXT: subf 6, 4, 5
2726; PPC64LE-NEXT: stbcx. 6, 0, 3
2727; PPC64LE-NEXT: bne 0, .LBB160_1
2728; PPC64LE-NEXT: # BB#2:
2729; PPC64LE-NEXT: mr 3, 5
2730; PPC64LE-NEXT: blr
2731 %ret = atomicrmw sub i8* %ptr, i8 %val monotonic
2732 ret i8 %ret
2733}
2734
2735define i8 @test161(i8* %ptr, i8 %val) {
2736; PPC64LE-LABEL: test161:
2737; PPC64LE: # BB#0:
2738; PPC64LE-NEXT: mr 5, 3
2739; PPC64LE-NEXT: .LBB161_1:
2740; PPC64LE-NEXT: lbarx 3, 0, 5
2741; PPC64LE-NEXT: subf 6, 4, 3
2742; PPC64LE-NEXT: stbcx. 6, 0, 5
2743; PPC64LE-NEXT: bne 0, .LBB161_1
2744; PPC64LE-NEXT: # BB#2:
2745; PPC64LE-NEXT: lwsync
2746; PPC64LE-NEXT: blr
2747 %ret = atomicrmw sub i8* %ptr, i8 %val acquire
2748 ret i8 %ret
2749}
2750
2751define i8 @test162(i8* %ptr, i8 %val) {
2752; PPC64LE-LABEL: test162:
2753; PPC64LE: # BB#0:
2754; PPC64LE-NEXT: lwsync
2755; PPC64LE-NEXT: .LBB162_1:
2756; PPC64LE-NEXT: lbarx 5, 0, 3
2757; PPC64LE-NEXT: subf 6, 4, 5
2758; PPC64LE-NEXT: stbcx. 6, 0, 3
2759; PPC64LE-NEXT: bne 0, .LBB162_1
2760; PPC64LE-NEXT: # BB#2:
2761; PPC64LE-NEXT: mr 3, 5
2762; PPC64LE-NEXT: blr
2763 %ret = atomicrmw sub i8* %ptr, i8 %val release
2764 ret i8 %ret
2765}
2766
2767define i8 @test163(i8* %ptr, i8 %val) {
2768; PPC64LE-LABEL: test163:
2769; PPC64LE: # BB#0:
2770; PPC64LE-NEXT: lwsync
2771; PPC64LE-NEXT: .LBB163_1:
2772; PPC64LE-NEXT: lbarx 5, 0, 3
2773; PPC64LE-NEXT: subf 6, 4, 5
2774; PPC64LE-NEXT: stbcx. 6, 0, 3
2775; PPC64LE-NEXT: bne 0, .LBB163_1
2776; PPC64LE-NEXT: # BB#2:
2777; PPC64LE-NEXT: mr 3, 5
2778; PPC64LE-NEXT: lwsync
2779; PPC64LE-NEXT: blr
2780 %ret = atomicrmw sub i8* %ptr, i8 %val acq_rel
2781 ret i8 %ret
2782}
2783
2784define i8 @test164(i8* %ptr, i8 %val) {
2785; PPC64LE-LABEL: test164:
2786; PPC64LE: # BB#0:
2787; PPC64LE-NEXT: sync
2788; PPC64LE-NEXT: .LBB164_1:
2789; PPC64LE-NEXT: lbarx 5, 0, 3
2790; PPC64LE-NEXT: subf 6, 4, 5
2791; PPC64LE-NEXT: stbcx. 6, 0, 3
2792; PPC64LE-NEXT: bne 0, .LBB164_1
2793; PPC64LE-NEXT: # BB#2:
2794; PPC64LE-NEXT: mr 3, 5
2795; PPC64LE-NEXT: lwsync
2796; PPC64LE-NEXT: blr
2797 %ret = atomicrmw sub i8* %ptr, i8 %val seq_cst
2798 ret i8 %ret
2799}
2800
2801define i16 @test165(i16* %ptr, i16 %val) {
2802; PPC64LE-LABEL: test165:
2803; PPC64LE: # BB#0:
2804; PPC64LE-NEXT: .LBB165_1:
2805; PPC64LE-NEXT: lharx 5, 0, 3
2806; PPC64LE-NEXT: subf 6, 4, 5
2807; PPC64LE-NEXT: sthcx. 6, 0, 3
2808; PPC64LE-NEXT: bne 0, .LBB165_1
2809; PPC64LE-NEXT: # BB#2:
2810; PPC64LE-NEXT: mr 3, 5
2811; PPC64LE-NEXT: blr
2812 %ret = atomicrmw sub i16* %ptr, i16 %val monotonic
2813 ret i16 %ret
2814}
2815
2816define i16 @test166(i16* %ptr, i16 %val) {
2817; PPC64LE-LABEL: test166:
2818; PPC64LE: # BB#0:
2819; PPC64LE-NEXT: mr 5, 3
2820; PPC64LE-NEXT: .LBB166_1:
2821; PPC64LE-NEXT: lharx 3, 0, 5
2822; PPC64LE-NEXT: subf 6, 4, 3
2823; PPC64LE-NEXT: sthcx. 6, 0, 5
2824; PPC64LE-NEXT: bne 0, .LBB166_1
2825; PPC64LE-NEXT: # BB#2:
2826; PPC64LE-NEXT: lwsync
2827; PPC64LE-NEXT: blr
2828 %ret = atomicrmw sub i16* %ptr, i16 %val acquire
2829 ret i16 %ret
2830}
2831
2832define i16 @test167(i16* %ptr, i16 %val) {
2833; PPC64LE-LABEL: test167:
2834; PPC64LE: # BB#0:
2835; PPC64LE-NEXT: lwsync
2836; PPC64LE-NEXT: .LBB167_1:
2837; PPC64LE-NEXT: lharx 5, 0, 3
2838; PPC64LE-NEXT: subf 6, 4, 5
2839; PPC64LE-NEXT: sthcx. 6, 0, 3
2840; PPC64LE-NEXT: bne 0, .LBB167_1
2841; PPC64LE-NEXT: # BB#2:
2842; PPC64LE-NEXT: mr 3, 5
2843; PPC64LE-NEXT: blr
2844 %ret = atomicrmw sub i16* %ptr, i16 %val release
2845 ret i16 %ret
2846}
2847
2848define i16 @test168(i16* %ptr, i16 %val) {
2849; PPC64LE-LABEL: test168:
2850; PPC64LE: # BB#0:
2851; PPC64LE-NEXT: lwsync
2852; PPC64LE-NEXT: .LBB168_1:
2853; PPC64LE-NEXT: lharx 5, 0, 3
2854; PPC64LE-NEXT: subf 6, 4, 5
2855; PPC64LE-NEXT: sthcx. 6, 0, 3
2856; PPC64LE-NEXT: bne 0, .LBB168_1
2857; PPC64LE-NEXT: # BB#2:
2858; PPC64LE-NEXT: mr 3, 5
2859; PPC64LE-NEXT: lwsync
2860; PPC64LE-NEXT: blr
2861 %ret = atomicrmw sub i16* %ptr, i16 %val acq_rel
2862 ret i16 %ret
2863}
2864
2865define i16 @test169(i16* %ptr, i16 %val) {
2866; PPC64LE-LABEL: test169:
2867; PPC64LE: # BB#0:
2868; PPC64LE-NEXT: sync
2869; PPC64LE-NEXT: .LBB169_1:
2870; PPC64LE-NEXT: lharx 5, 0, 3
2871; PPC64LE-NEXT: subf 6, 4, 5
2872; PPC64LE-NEXT: sthcx. 6, 0, 3
2873; PPC64LE-NEXT: bne 0, .LBB169_1
2874; PPC64LE-NEXT: # BB#2:
2875; PPC64LE-NEXT: mr 3, 5
2876; PPC64LE-NEXT: lwsync
2877; PPC64LE-NEXT: blr
2878 %ret = atomicrmw sub i16* %ptr, i16 %val seq_cst
2879 ret i16 %ret
2880}
2881
2882define i32 @test170(i32* %ptr, i32 %val) {
2883; PPC64LE-LABEL: test170:
2884; PPC64LE: # BB#0:
2885; PPC64LE-NEXT: .LBB170_1:
2886; PPC64LE-NEXT: lwarx 5, 0, 3
2887; PPC64LE-NEXT: subf 6, 4, 5
2888; PPC64LE-NEXT: stwcx. 6, 0, 3
2889; PPC64LE-NEXT: bne 0, .LBB170_1
2890; PPC64LE-NEXT: # BB#2:
2891; PPC64LE-NEXT: mr 3, 5
2892; PPC64LE-NEXT: blr
2893 %ret = atomicrmw sub i32* %ptr, i32 %val monotonic
2894 ret i32 %ret
2895}
2896
2897define i32 @test171(i32* %ptr, i32 %val) {
2898; PPC64LE-LABEL: test171:
2899; PPC64LE: # BB#0:
2900; PPC64LE-NEXT: mr 5, 3
2901; PPC64LE-NEXT: .LBB171_1:
2902; PPC64LE-NEXT: lwarx 3, 0, 5
2903; PPC64LE-NEXT: subf 6, 4, 3
2904; PPC64LE-NEXT: stwcx. 6, 0, 5
2905; PPC64LE-NEXT: bne 0, .LBB171_1
2906; PPC64LE-NEXT: # BB#2:
2907; PPC64LE-NEXT: lwsync
2908; PPC64LE-NEXT: blr
2909 %ret = atomicrmw sub i32* %ptr, i32 %val acquire
2910 ret i32 %ret
2911}
2912
2913define i32 @test172(i32* %ptr, i32 %val) {
2914; PPC64LE-LABEL: test172:
2915; PPC64LE: # BB#0:
2916; PPC64LE-NEXT: lwsync
2917; PPC64LE-NEXT: .LBB172_1:
2918; PPC64LE-NEXT: lwarx 5, 0, 3
2919; PPC64LE-NEXT: subf 6, 4, 5
2920; PPC64LE-NEXT: stwcx. 6, 0, 3
2921; PPC64LE-NEXT: bne 0, .LBB172_1
2922; PPC64LE-NEXT: # BB#2:
2923; PPC64LE-NEXT: mr 3, 5
2924; PPC64LE-NEXT: blr
2925 %ret = atomicrmw sub i32* %ptr, i32 %val release
2926 ret i32 %ret
2927}
2928
2929define i32 @test173(i32* %ptr, i32 %val) {
2930; PPC64LE-LABEL: test173:
2931; PPC64LE: # BB#0:
2932; PPC64LE-NEXT: lwsync
2933; PPC64LE-NEXT: .LBB173_1:
2934; PPC64LE-NEXT: lwarx 5, 0, 3
2935; PPC64LE-NEXT: subf 6, 4, 5
2936; PPC64LE-NEXT: stwcx. 6, 0, 3
2937; PPC64LE-NEXT: bne 0, .LBB173_1
2938; PPC64LE-NEXT: # BB#2:
2939; PPC64LE-NEXT: mr 3, 5
2940; PPC64LE-NEXT: lwsync
2941; PPC64LE-NEXT: blr
2942 %ret = atomicrmw sub i32* %ptr, i32 %val acq_rel
2943 ret i32 %ret
2944}
2945
2946define i32 @test174(i32* %ptr, i32 %val) {
2947; PPC64LE-LABEL: test174:
2948; PPC64LE: # BB#0:
2949; PPC64LE-NEXT: sync
2950; PPC64LE-NEXT: .LBB174_1:
2951; PPC64LE-NEXT: lwarx 5, 0, 3
2952; PPC64LE-NEXT: subf 6, 4, 5
2953; PPC64LE-NEXT: stwcx. 6, 0, 3
2954; PPC64LE-NEXT: bne 0, .LBB174_1
2955; PPC64LE-NEXT: # BB#2:
2956; PPC64LE-NEXT: mr 3, 5
2957; PPC64LE-NEXT: lwsync
2958; PPC64LE-NEXT: blr
2959 %ret = atomicrmw sub i32* %ptr, i32 %val seq_cst
2960 ret i32 %ret
2961}
2962
2963define i64 @test175(i64* %ptr, i64 %val) {
2964; PPC64LE-LABEL: test175:
2965; PPC64LE: # BB#0:
2966; PPC64LE-NEXT: .LBB175_1:
2967; PPC64LE-NEXT: ldarx 5, 0, 3
2968; PPC64LE-NEXT: sub 6, 5, 4
2969; PPC64LE-NEXT: stdcx. 6, 0, 3
2970; PPC64LE-NEXT: bne 0, .LBB175_1
2971; PPC64LE-NEXT: # BB#2:
2972; PPC64LE-NEXT: mr 3, 5
2973; PPC64LE-NEXT: blr
2974 %ret = atomicrmw sub i64* %ptr, i64 %val monotonic
2975 ret i64 %ret
2976}
2977
2978define i64 @test176(i64* %ptr, i64 %val) {
2979; PPC64LE-LABEL: test176:
2980; PPC64LE: # BB#0:
2981; PPC64LE-NEXT: mr 5, 3
2982; PPC64LE-NEXT: .LBB176_1:
2983; PPC64LE-NEXT: ldarx 3, 0, 5
2984; PPC64LE-NEXT: sub 6, 3, 4
2985; PPC64LE-NEXT: stdcx. 6, 0, 5
2986; PPC64LE-NEXT: bne 0, .LBB176_1
2987; PPC64LE-NEXT: # BB#2:
2988; PPC64LE-NEXT: lwsync
2989; PPC64LE-NEXT: blr
2990 %ret = atomicrmw sub i64* %ptr, i64 %val acquire
2991 ret i64 %ret
2992}
2993
2994define i64 @test177(i64* %ptr, i64 %val) {
2995; PPC64LE-LABEL: test177:
2996; PPC64LE: # BB#0:
2997; PPC64LE-NEXT: lwsync
2998; PPC64LE-NEXT: .LBB177_1:
2999; PPC64LE-NEXT: ldarx 5, 0, 3
3000; PPC64LE-NEXT: sub 6, 5, 4
3001; PPC64LE-NEXT: stdcx. 6, 0, 3
3002; PPC64LE-NEXT: bne 0, .LBB177_1
3003; PPC64LE-NEXT: # BB#2:
3004; PPC64LE-NEXT: mr 3, 5
3005; PPC64LE-NEXT: blr
3006 %ret = atomicrmw sub i64* %ptr, i64 %val release
3007 ret i64 %ret
3008}
3009
3010define i64 @test178(i64* %ptr, i64 %val) {
3011; PPC64LE-LABEL: test178:
3012; PPC64LE: # BB#0:
3013; PPC64LE-NEXT: lwsync
3014; PPC64LE-NEXT: .LBB178_1:
3015; PPC64LE-NEXT: ldarx 5, 0, 3
3016; PPC64LE-NEXT: sub 6, 5, 4
3017; PPC64LE-NEXT: stdcx. 6, 0, 3
3018; PPC64LE-NEXT: bne 0, .LBB178_1
3019; PPC64LE-NEXT: # BB#2:
3020; PPC64LE-NEXT: mr 3, 5
3021; PPC64LE-NEXT: lwsync
3022; PPC64LE-NEXT: blr
3023 %ret = atomicrmw sub i64* %ptr, i64 %val acq_rel
3024 ret i64 %ret
3025}
3026
3027define i64 @test179(i64* %ptr, i64 %val) {
3028; PPC64LE-LABEL: test179:
3029; PPC64LE: # BB#0:
3030; PPC64LE-NEXT: sync
3031; PPC64LE-NEXT: .LBB179_1:
3032; PPC64LE-NEXT: ldarx 5, 0, 3
3033; PPC64LE-NEXT: sub 6, 5, 4
3034; PPC64LE-NEXT: stdcx. 6, 0, 3
3035; PPC64LE-NEXT: bne 0, .LBB179_1
3036; PPC64LE-NEXT: # BB#2:
3037; PPC64LE-NEXT: mr 3, 5
3038; PPC64LE-NEXT: lwsync
3039; PPC64LE-NEXT: blr
3040 %ret = atomicrmw sub i64* %ptr, i64 %val seq_cst
3041 ret i64 %ret
3042}
3043
3044define i8 @test180(i8* %ptr, i8 %val) {
3045; PPC64LE-LABEL: test180:
3046; PPC64LE: # BB#0:
3047; PPC64LE-NEXT: .LBB180_1:
3048; PPC64LE-NEXT: lbarx 5, 0, 3
3049; PPC64LE-NEXT: and 6, 4, 5
3050; PPC64LE-NEXT: stbcx. 6, 0, 3
3051; PPC64LE-NEXT: bne 0, .LBB180_1
3052; PPC64LE-NEXT: # BB#2:
3053; PPC64LE-NEXT: mr 3, 5
3054; PPC64LE-NEXT: blr
3055 %ret = atomicrmw and i8* %ptr, i8 %val monotonic
3056 ret i8 %ret
3057}
3058
3059define i8 @test181(i8* %ptr, i8 %val) {
3060; PPC64LE-LABEL: test181:
3061; PPC64LE: # BB#0:
3062; PPC64LE-NEXT: mr 5, 3
3063; PPC64LE-NEXT: .LBB181_1:
3064; PPC64LE-NEXT: lbarx 3, 0, 5
3065; PPC64LE-NEXT: and 6, 4, 3
3066; PPC64LE-NEXT: stbcx. 6, 0, 5
3067; PPC64LE-NEXT: bne 0, .LBB181_1
3068; PPC64LE-NEXT: # BB#2:
3069; PPC64LE-NEXT: lwsync
3070; PPC64LE-NEXT: blr
3071 %ret = atomicrmw and i8* %ptr, i8 %val acquire
3072 ret i8 %ret
3073}
3074
3075define i8 @test182(i8* %ptr, i8 %val) {
3076; PPC64LE-LABEL: test182:
3077; PPC64LE: # BB#0:
3078; PPC64LE-NEXT: lwsync
3079; PPC64LE-NEXT: .LBB182_1:
3080; PPC64LE-NEXT: lbarx 5, 0, 3
3081; PPC64LE-NEXT: and 6, 4, 5
3082; PPC64LE-NEXT: stbcx. 6, 0, 3
3083; PPC64LE-NEXT: bne 0, .LBB182_1
3084; PPC64LE-NEXT: # BB#2:
3085; PPC64LE-NEXT: mr 3, 5
3086; PPC64LE-NEXT: blr
3087 %ret = atomicrmw and i8* %ptr, i8 %val release
3088 ret i8 %ret
3089}
3090
3091define i8 @test183(i8* %ptr, i8 %val) {
3092; PPC64LE-LABEL: test183:
3093; PPC64LE: # BB#0:
3094; PPC64LE-NEXT: lwsync
3095; PPC64LE-NEXT: .LBB183_1:
3096; PPC64LE-NEXT: lbarx 5, 0, 3
3097; PPC64LE-NEXT: and 6, 4, 5
3098; PPC64LE-NEXT: stbcx. 6, 0, 3
3099; PPC64LE-NEXT: bne 0, .LBB183_1
3100; PPC64LE-NEXT: # BB#2:
3101; PPC64LE-NEXT: mr 3, 5
3102; PPC64LE-NEXT: lwsync
3103; PPC64LE-NEXT: blr
3104 %ret = atomicrmw and i8* %ptr, i8 %val acq_rel
3105 ret i8 %ret
3106}
3107
3108define i8 @test184(i8* %ptr, i8 %val) {
3109; PPC64LE-LABEL: test184:
3110; PPC64LE: # BB#0:
3111; PPC64LE-NEXT: sync
3112; PPC64LE-NEXT: .LBB184_1:
3113; PPC64LE-NEXT: lbarx 5, 0, 3
3114; PPC64LE-NEXT: and 6, 4, 5
3115; PPC64LE-NEXT: stbcx. 6, 0, 3
3116; PPC64LE-NEXT: bne 0, .LBB184_1
3117; PPC64LE-NEXT: # BB#2:
3118; PPC64LE-NEXT: mr 3, 5
3119; PPC64LE-NEXT: lwsync
3120; PPC64LE-NEXT: blr
3121 %ret = atomicrmw and i8* %ptr, i8 %val seq_cst
3122 ret i8 %ret
3123}
3124
3125define i16 @test185(i16* %ptr, i16 %val) {
3126; PPC64LE-LABEL: test185:
3127; PPC64LE: # BB#0:
3128; PPC64LE-NEXT: .LBB185_1:
3129; PPC64LE-NEXT: lharx 5, 0, 3
3130; PPC64LE-NEXT: and 6, 4, 5
3131; PPC64LE-NEXT: sthcx. 6, 0, 3
3132; PPC64LE-NEXT: bne 0, .LBB185_1
3133; PPC64LE-NEXT: # BB#2:
3134; PPC64LE-NEXT: mr 3, 5
3135; PPC64LE-NEXT: blr
3136 %ret = atomicrmw and i16* %ptr, i16 %val monotonic
3137 ret i16 %ret
3138}
3139
3140define i16 @test186(i16* %ptr, i16 %val) {
3141; PPC64LE-LABEL: test186:
3142; PPC64LE: # BB#0:
3143; PPC64LE-NEXT: mr 5, 3
3144; PPC64LE-NEXT: .LBB186_1:
3145; PPC64LE-NEXT: lharx 3, 0, 5
3146; PPC64LE-NEXT: and 6, 4, 3
3147; PPC64LE-NEXT: sthcx. 6, 0, 5
3148; PPC64LE-NEXT: bne 0, .LBB186_1
3149; PPC64LE-NEXT: # BB#2:
3150; PPC64LE-NEXT: lwsync
3151; PPC64LE-NEXT: blr
3152 %ret = atomicrmw and i16* %ptr, i16 %val acquire
3153 ret i16 %ret
3154}
3155
3156define i16 @test187(i16* %ptr, i16 %val) {
3157; PPC64LE-LABEL: test187:
3158; PPC64LE: # BB#0:
3159; PPC64LE-NEXT: lwsync
3160; PPC64LE-NEXT: .LBB187_1:
3161; PPC64LE-NEXT: lharx 5, 0, 3
3162; PPC64LE-NEXT: and 6, 4, 5
3163; PPC64LE-NEXT: sthcx. 6, 0, 3
3164; PPC64LE-NEXT: bne 0, .LBB187_1
3165; PPC64LE-NEXT: # BB#2:
3166; PPC64LE-NEXT: mr 3, 5
3167; PPC64LE-NEXT: blr
3168 %ret = atomicrmw and i16* %ptr, i16 %val release
3169 ret i16 %ret
3170}
3171
3172define i16 @test188(i16* %ptr, i16 %val) {
3173; PPC64LE-LABEL: test188:
3174; PPC64LE: # BB#0:
3175; PPC64LE-NEXT: lwsync
3176; PPC64LE-NEXT: .LBB188_1:
3177; PPC64LE-NEXT: lharx 5, 0, 3
3178; PPC64LE-NEXT: and 6, 4, 5
3179; PPC64LE-NEXT: sthcx. 6, 0, 3
3180; PPC64LE-NEXT: bne 0, .LBB188_1
3181; PPC64LE-NEXT: # BB#2:
3182; PPC64LE-NEXT: mr 3, 5
3183; PPC64LE-NEXT: lwsync
3184; PPC64LE-NEXT: blr
3185 %ret = atomicrmw and i16* %ptr, i16 %val acq_rel
3186 ret i16 %ret
3187}
3188
3189define i16 @test189(i16* %ptr, i16 %val) {
3190; PPC64LE-LABEL: test189:
3191; PPC64LE: # BB#0:
3192; PPC64LE-NEXT: sync
3193; PPC64LE-NEXT: .LBB189_1:
3194; PPC64LE-NEXT: lharx 5, 0, 3
3195; PPC64LE-NEXT: and 6, 4, 5
3196; PPC64LE-NEXT: sthcx. 6, 0, 3
3197; PPC64LE-NEXT: bne 0, .LBB189_1
3198; PPC64LE-NEXT: # BB#2:
3199; PPC64LE-NEXT: mr 3, 5
3200; PPC64LE-NEXT: lwsync
3201; PPC64LE-NEXT: blr
3202 %ret = atomicrmw and i16* %ptr, i16 %val seq_cst
3203 ret i16 %ret
3204}
3205
3206define i32 @test190(i32* %ptr, i32 %val) {
3207; PPC64LE-LABEL: test190:
3208; PPC64LE: # BB#0:
3209; PPC64LE-NEXT: .LBB190_1:
3210; PPC64LE-NEXT: lwarx 5, 0, 3
3211; PPC64LE-NEXT: and 6, 4, 5
3212; PPC64LE-NEXT: stwcx. 6, 0, 3
3213; PPC64LE-NEXT: bne 0, .LBB190_1
3214; PPC64LE-NEXT: # BB#2:
3215; PPC64LE-NEXT: mr 3, 5
3216; PPC64LE-NEXT: blr
3217 %ret = atomicrmw and i32* %ptr, i32 %val monotonic
3218 ret i32 %ret
3219}
3220
3221define i32 @test191(i32* %ptr, i32 %val) {
3222; PPC64LE-LABEL: test191:
3223; PPC64LE: # BB#0:
3224; PPC64LE-NEXT: mr 5, 3
3225; PPC64LE-NEXT: .LBB191_1:
3226; PPC64LE-NEXT: lwarx 3, 0, 5
3227; PPC64LE-NEXT: and 6, 4, 3
3228; PPC64LE-NEXT: stwcx. 6, 0, 5
3229; PPC64LE-NEXT: bne 0, .LBB191_1
3230; PPC64LE-NEXT: # BB#2:
3231; PPC64LE-NEXT: lwsync
3232; PPC64LE-NEXT: blr
3233 %ret = atomicrmw and i32* %ptr, i32 %val acquire
3234 ret i32 %ret
3235}
3236
3237define i32 @test192(i32* %ptr, i32 %val) {
3238; PPC64LE-LABEL: test192:
3239; PPC64LE: # BB#0:
3240; PPC64LE-NEXT: lwsync
3241; PPC64LE-NEXT: .LBB192_1:
3242; PPC64LE-NEXT: lwarx 5, 0, 3
3243; PPC64LE-NEXT: and 6, 4, 5
3244; PPC64LE-NEXT: stwcx. 6, 0, 3
3245; PPC64LE-NEXT: bne 0, .LBB192_1
3246; PPC64LE-NEXT: # BB#2:
3247; PPC64LE-NEXT: mr 3, 5
3248; PPC64LE-NEXT: blr
3249 %ret = atomicrmw and i32* %ptr, i32 %val release
3250 ret i32 %ret
3251}
3252
3253define i32 @test193(i32* %ptr, i32 %val) {
3254; PPC64LE-LABEL: test193:
3255; PPC64LE: # BB#0:
3256; PPC64LE-NEXT: lwsync
3257; PPC64LE-NEXT: .LBB193_1:
3258; PPC64LE-NEXT: lwarx 5, 0, 3
3259; PPC64LE-NEXT: and 6, 4, 5
3260; PPC64LE-NEXT: stwcx. 6, 0, 3
3261; PPC64LE-NEXT: bne 0, .LBB193_1
3262; PPC64LE-NEXT: # BB#2:
3263; PPC64LE-NEXT: mr 3, 5
3264; PPC64LE-NEXT: lwsync
3265; PPC64LE-NEXT: blr
3266 %ret = atomicrmw and i32* %ptr, i32 %val acq_rel
3267 ret i32 %ret
3268}
3269
3270define i32 @test194(i32* %ptr, i32 %val) {
3271; PPC64LE-LABEL: test194:
3272; PPC64LE: # BB#0:
3273; PPC64LE-NEXT: sync
3274; PPC64LE-NEXT: .LBB194_1:
3275; PPC64LE-NEXT: lwarx 5, 0, 3
3276; PPC64LE-NEXT: and 6, 4, 5
3277; PPC64LE-NEXT: stwcx. 6, 0, 3
3278; PPC64LE-NEXT: bne 0, .LBB194_1
3279; PPC64LE-NEXT: # BB#2:
3280; PPC64LE-NEXT: mr 3, 5
3281; PPC64LE-NEXT: lwsync
3282; PPC64LE-NEXT: blr
3283 %ret = atomicrmw and i32* %ptr, i32 %val seq_cst
3284 ret i32 %ret
3285}
3286
3287define i64 @test195(i64* %ptr, i64 %val) {
3288; PPC64LE-LABEL: test195:
3289; PPC64LE: # BB#0:
3290; PPC64LE-NEXT: .LBB195_1:
3291; PPC64LE-NEXT: ldarx 5, 0, 3
3292; PPC64LE-NEXT: and 6, 4, 5
3293; PPC64LE-NEXT: stdcx. 6, 0, 3
3294; PPC64LE-NEXT: bne 0, .LBB195_1
3295; PPC64LE-NEXT: # BB#2:
3296; PPC64LE-NEXT: mr 3, 5
3297; PPC64LE-NEXT: blr
3298 %ret = atomicrmw and i64* %ptr, i64 %val monotonic
3299 ret i64 %ret
3300}
3301
3302define i64 @test196(i64* %ptr, i64 %val) {
3303; PPC64LE-LABEL: test196:
3304; PPC64LE: # BB#0:
3305; PPC64LE-NEXT: mr 5, 3
3306; PPC64LE-NEXT: .LBB196_1:
3307; PPC64LE-NEXT: ldarx 3, 0, 5
3308; PPC64LE-NEXT: and 6, 4, 3
3309; PPC64LE-NEXT: stdcx. 6, 0, 5
3310; PPC64LE-NEXT: bne 0, .LBB196_1
3311; PPC64LE-NEXT: # BB#2:
3312; PPC64LE-NEXT: lwsync
3313; PPC64LE-NEXT: blr
3314 %ret = atomicrmw and i64* %ptr, i64 %val acquire
3315 ret i64 %ret
3316}
3317
3318define i64 @test197(i64* %ptr, i64 %val) {
3319; PPC64LE-LABEL: test197:
3320; PPC64LE: # BB#0:
3321; PPC64LE-NEXT: lwsync
3322; PPC64LE-NEXT: .LBB197_1:
3323; PPC64LE-NEXT: ldarx 5, 0, 3
3324; PPC64LE-NEXT: and 6, 4, 5
3325; PPC64LE-NEXT: stdcx. 6, 0, 3
3326; PPC64LE-NEXT: bne 0, .LBB197_1
3327; PPC64LE-NEXT: # BB#2:
3328; PPC64LE-NEXT: mr 3, 5
3329; PPC64LE-NEXT: blr
3330 %ret = atomicrmw and i64* %ptr, i64 %val release
3331 ret i64 %ret
3332}
3333
3334define i64 @test198(i64* %ptr, i64 %val) {
3335; PPC64LE-LABEL: test198:
3336; PPC64LE: # BB#0:
3337; PPC64LE-NEXT: lwsync
3338; PPC64LE-NEXT: .LBB198_1:
3339; PPC64LE-NEXT: ldarx 5, 0, 3
3340; PPC64LE-NEXT: and 6, 4, 5
3341; PPC64LE-NEXT: stdcx. 6, 0, 3
3342; PPC64LE-NEXT: bne 0, .LBB198_1
3343; PPC64LE-NEXT: # BB#2:
3344; PPC64LE-NEXT: mr 3, 5
3345; PPC64LE-NEXT: lwsync
3346; PPC64LE-NEXT: blr
3347 %ret = atomicrmw and i64* %ptr, i64 %val acq_rel
3348 ret i64 %ret
3349}
3350
3351define i64 @test199(i64* %ptr, i64 %val) {
3352; PPC64LE-LABEL: test199:
3353; PPC64LE: # BB#0:
3354; PPC64LE-NEXT: sync
3355; PPC64LE-NEXT: .LBB199_1:
3356; PPC64LE-NEXT: ldarx 5, 0, 3
3357; PPC64LE-NEXT: and 6, 4, 5
3358; PPC64LE-NEXT: stdcx. 6, 0, 3
3359; PPC64LE-NEXT: bne 0, .LBB199_1
3360; PPC64LE-NEXT: # BB#2:
3361; PPC64LE-NEXT: mr 3, 5
3362; PPC64LE-NEXT: lwsync
3363; PPC64LE-NEXT: blr
3364 %ret = atomicrmw and i64* %ptr, i64 %val seq_cst
3365 ret i64 %ret
3366}
3367
3368define i8 @test200(i8* %ptr, i8 %val) {
3369; PPC64LE-LABEL: test200:
3370; PPC64LE: # BB#0:
3371; PPC64LE-NEXT: .LBB200_1:
3372; PPC64LE-NEXT: lbarx 5, 0, 3
3373; PPC64LE-NEXT: nand 6, 4, 5
3374; PPC64LE-NEXT: stbcx. 6, 0, 3
3375; PPC64LE-NEXT: bne 0, .LBB200_1
3376; PPC64LE-NEXT: # BB#2:
3377; PPC64LE-NEXT: mr 3, 5
3378; PPC64LE-NEXT: blr
3379 %ret = atomicrmw nand i8* %ptr, i8 %val monotonic
3380 ret i8 %ret
3381}
3382
3383define i8 @test201(i8* %ptr, i8 %val) {
3384; PPC64LE-LABEL: test201:
3385; PPC64LE: # BB#0:
3386; PPC64LE-NEXT: mr 5, 3
3387; PPC64LE-NEXT: .LBB201_1:
3388; PPC64LE-NEXT: lbarx 3, 0, 5
3389; PPC64LE-NEXT: nand 6, 4, 3
3390; PPC64LE-NEXT: stbcx. 6, 0, 5
3391; PPC64LE-NEXT: bne 0, .LBB201_1
3392; PPC64LE-NEXT: # BB#2:
3393; PPC64LE-NEXT: lwsync
3394; PPC64LE-NEXT: blr
3395 %ret = atomicrmw nand i8* %ptr, i8 %val acquire
3396 ret i8 %ret
3397}
3398
3399define i8 @test202(i8* %ptr, i8 %val) {
3400; PPC64LE-LABEL: test202:
3401; PPC64LE: # BB#0:
3402; PPC64LE-NEXT: lwsync
3403; PPC64LE-NEXT: .LBB202_1:
3404; PPC64LE-NEXT: lbarx 5, 0, 3
3405; PPC64LE-NEXT: nand 6, 4, 5
3406; PPC64LE-NEXT: stbcx. 6, 0, 3
3407; PPC64LE-NEXT: bne 0, .LBB202_1
3408; PPC64LE-NEXT: # BB#2:
3409; PPC64LE-NEXT: mr 3, 5
3410; PPC64LE-NEXT: blr
3411 %ret = atomicrmw nand i8* %ptr, i8 %val release
3412 ret i8 %ret
3413}
3414
3415define i8 @test203(i8* %ptr, i8 %val) {
3416; PPC64LE-LABEL: test203:
3417; PPC64LE: # BB#0:
3418; PPC64LE-NEXT: lwsync
3419; PPC64LE-NEXT: .LBB203_1:
3420; PPC64LE-NEXT: lbarx 5, 0, 3
3421; PPC64LE-NEXT: nand 6, 4, 5
3422; PPC64LE-NEXT: stbcx. 6, 0, 3
3423; PPC64LE-NEXT: bne 0, .LBB203_1
3424; PPC64LE-NEXT: # BB#2:
3425; PPC64LE-NEXT: mr 3, 5
3426; PPC64LE-NEXT: lwsync
3427; PPC64LE-NEXT: blr
3428 %ret = atomicrmw nand i8* %ptr, i8 %val acq_rel
3429 ret i8 %ret
3430}
3431
3432define i8 @test204(i8* %ptr, i8 %val) {
3433; PPC64LE-LABEL: test204:
3434; PPC64LE: # BB#0:
3435; PPC64LE-NEXT: sync
3436; PPC64LE-NEXT: .LBB204_1:
3437; PPC64LE-NEXT: lbarx 5, 0, 3
3438; PPC64LE-NEXT: nand 6, 4, 5
3439; PPC64LE-NEXT: stbcx. 6, 0, 3
3440; PPC64LE-NEXT: bne 0, .LBB204_1
3441; PPC64LE-NEXT: # BB#2:
3442; PPC64LE-NEXT: mr 3, 5
3443; PPC64LE-NEXT: lwsync
3444; PPC64LE-NEXT: blr
3445 %ret = atomicrmw nand i8* %ptr, i8 %val seq_cst
3446 ret i8 %ret
3447}
3448
3449define i16 @test205(i16* %ptr, i16 %val) {
3450; PPC64LE-LABEL: test205:
3451; PPC64LE: # BB#0:
3452; PPC64LE-NEXT: .LBB205_1:
3453; PPC64LE-NEXT: lharx 5, 0, 3
3454; PPC64LE-NEXT: nand 6, 4, 5
3455; PPC64LE-NEXT: sthcx. 6, 0, 3
3456; PPC64LE-NEXT: bne 0, .LBB205_1
3457; PPC64LE-NEXT: # BB#2:
3458; PPC64LE-NEXT: mr 3, 5
3459; PPC64LE-NEXT: blr
3460 %ret = atomicrmw nand i16* %ptr, i16 %val monotonic
3461 ret i16 %ret
3462}
3463
3464define i16 @test206(i16* %ptr, i16 %val) {
3465; PPC64LE-LABEL: test206:
3466; PPC64LE: # BB#0:
3467; PPC64LE-NEXT: mr 5, 3
3468; PPC64LE-NEXT: .LBB206_1:
3469; PPC64LE-NEXT: lharx 3, 0, 5
3470; PPC64LE-NEXT: nand 6, 4, 3
3471; PPC64LE-NEXT: sthcx. 6, 0, 5
3472; PPC64LE-NEXT: bne 0, .LBB206_1
3473; PPC64LE-NEXT: # BB#2:
3474; PPC64LE-NEXT: lwsync
3475; PPC64LE-NEXT: blr
3476 %ret = atomicrmw nand i16* %ptr, i16 %val acquire
3477 ret i16 %ret
3478}
3479
3480define i16 @test207(i16* %ptr, i16 %val) {
3481; PPC64LE-LABEL: test207:
3482; PPC64LE: # BB#0:
3483; PPC64LE-NEXT: lwsync
3484; PPC64LE-NEXT: .LBB207_1:
3485; PPC64LE-NEXT: lharx 5, 0, 3
3486; PPC64LE-NEXT: nand 6, 4, 5
3487; PPC64LE-NEXT: sthcx. 6, 0, 3
3488; PPC64LE-NEXT: bne 0, .LBB207_1
3489; PPC64LE-NEXT: # BB#2:
3490; PPC64LE-NEXT: mr 3, 5
3491; PPC64LE-NEXT: blr
3492 %ret = atomicrmw nand i16* %ptr, i16 %val release
3493 ret i16 %ret
3494}
3495
3496define i16 @test208(i16* %ptr, i16 %val) {
3497; PPC64LE-LABEL: test208:
3498; PPC64LE: # BB#0:
3499; PPC64LE-NEXT: lwsync
3500; PPC64LE-NEXT: .LBB208_1:
3501; PPC64LE-NEXT: lharx 5, 0, 3
3502; PPC64LE-NEXT: nand 6, 4, 5
3503; PPC64LE-NEXT: sthcx. 6, 0, 3
3504; PPC64LE-NEXT: bne 0, .LBB208_1
3505; PPC64LE-NEXT: # BB#2:
3506; PPC64LE-NEXT: mr 3, 5
3507; PPC64LE-NEXT: lwsync
3508; PPC64LE-NEXT: blr
3509 %ret = atomicrmw nand i16* %ptr, i16 %val acq_rel
3510 ret i16 %ret
3511}
3512
3513define i16 @test209(i16* %ptr, i16 %val) {
3514; PPC64LE-LABEL: test209:
3515; PPC64LE: # BB#0:
3516; PPC64LE-NEXT: sync
3517; PPC64LE-NEXT: .LBB209_1:
3518; PPC64LE-NEXT: lharx 5, 0, 3
3519; PPC64LE-NEXT: nand 6, 4, 5
3520; PPC64LE-NEXT: sthcx. 6, 0, 3
3521; PPC64LE-NEXT: bne 0, .LBB209_1
3522; PPC64LE-NEXT: # BB#2:
3523; PPC64LE-NEXT: mr 3, 5
3524; PPC64LE-NEXT: lwsync
3525; PPC64LE-NEXT: blr
3526 %ret = atomicrmw nand i16* %ptr, i16 %val seq_cst
3527 ret i16 %ret
3528}
3529
3530define i32 @test210(i32* %ptr, i32 %val) {
3531; PPC64LE-LABEL: test210:
3532; PPC64LE: # BB#0:
3533; PPC64LE-NEXT: .LBB210_1:
3534; PPC64LE-NEXT: lwarx 5, 0, 3
3535; PPC64LE-NEXT: nand 6, 4, 5
3536; PPC64LE-NEXT: stwcx. 6, 0, 3
3537; PPC64LE-NEXT: bne 0, .LBB210_1
3538; PPC64LE-NEXT: # BB#2:
3539; PPC64LE-NEXT: mr 3, 5
3540; PPC64LE-NEXT: blr
3541 %ret = atomicrmw nand i32* %ptr, i32 %val monotonic
3542 ret i32 %ret
3543}
3544
3545define i32 @test211(i32* %ptr, i32 %val) {
3546; PPC64LE-LABEL: test211:
3547; PPC64LE: # BB#0:
3548; PPC64LE-NEXT: mr 5, 3
3549; PPC64LE-NEXT: .LBB211_1:
3550; PPC64LE-NEXT: lwarx 3, 0, 5
3551; PPC64LE-NEXT: nand 6, 4, 3
3552; PPC64LE-NEXT: stwcx. 6, 0, 5
3553; PPC64LE-NEXT: bne 0, .LBB211_1
3554; PPC64LE-NEXT: # BB#2:
3555; PPC64LE-NEXT: lwsync
3556; PPC64LE-NEXT: blr
3557 %ret = atomicrmw nand i32* %ptr, i32 %val acquire
3558 ret i32 %ret
3559}
3560
3561define i32 @test212(i32* %ptr, i32 %val) {
3562; PPC64LE-LABEL: test212:
3563; PPC64LE: # BB#0:
3564; PPC64LE-NEXT: lwsync
3565; PPC64LE-NEXT: .LBB212_1:
3566; PPC64LE-NEXT: lwarx 5, 0, 3
3567; PPC64LE-NEXT: nand 6, 4, 5
3568; PPC64LE-NEXT: stwcx. 6, 0, 3
3569; PPC64LE-NEXT: bne 0, .LBB212_1
3570; PPC64LE-NEXT: # BB#2:
3571; PPC64LE-NEXT: mr 3, 5
3572; PPC64LE-NEXT: blr
3573 %ret = atomicrmw nand i32* %ptr, i32 %val release
3574 ret i32 %ret
3575}
3576
3577define i32 @test213(i32* %ptr, i32 %val) {
3578; PPC64LE-LABEL: test213:
3579; PPC64LE: # BB#0:
3580; PPC64LE-NEXT: lwsync
3581; PPC64LE-NEXT: .LBB213_1:
3582; PPC64LE-NEXT: lwarx 5, 0, 3
3583; PPC64LE-NEXT: nand 6, 4, 5
3584; PPC64LE-NEXT: stwcx. 6, 0, 3
3585; PPC64LE-NEXT: bne 0, .LBB213_1
3586; PPC64LE-NEXT: # BB#2:
3587; PPC64LE-NEXT: mr 3, 5
3588; PPC64LE-NEXT: lwsync
3589; PPC64LE-NEXT: blr
3590 %ret = atomicrmw nand i32* %ptr, i32 %val acq_rel
3591 ret i32 %ret
3592}
3593
3594define i32 @test214(i32* %ptr, i32 %val) {
3595; PPC64LE-LABEL: test214:
3596; PPC64LE: # BB#0:
3597; PPC64LE-NEXT: sync
3598; PPC64LE-NEXT: .LBB214_1:
3599; PPC64LE-NEXT: lwarx 5, 0, 3
3600; PPC64LE-NEXT: nand 6, 4, 5
3601; PPC64LE-NEXT: stwcx. 6, 0, 3
3602; PPC64LE-NEXT: bne 0, .LBB214_1
3603; PPC64LE-NEXT: # BB#2:
3604; PPC64LE-NEXT: mr 3, 5
3605; PPC64LE-NEXT: lwsync
3606; PPC64LE-NEXT: blr
3607 %ret = atomicrmw nand i32* %ptr, i32 %val seq_cst
3608 ret i32 %ret
3609}
3610
3611define i64 @test215(i64* %ptr, i64 %val) {
3612; PPC64LE-LABEL: test215:
3613; PPC64LE: # BB#0:
3614; PPC64LE-NEXT: .LBB215_1:
3615; PPC64LE-NEXT: ldarx 5, 0, 3
3616; PPC64LE-NEXT: nand 6, 4, 5
3617; PPC64LE-NEXT: stdcx. 6, 0, 3
3618; PPC64LE-NEXT: bne 0, .LBB215_1
3619; PPC64LE-NEXT: # BB#2:
3620; PPC64LE-NEXT: mr 3, 5
3621; PPC64LE-NEXT: blr
3622 %ret = atomicrmw nand i64* %ptr, i64 %val monotonic
3623 ret i64 %ret
3624}
3625
3626define i64 @test216(i64* %ptr, i64 %val) {
3627; PPC64LE-LABEL: test216:
3628; PPC64LE: # BB#0:
3629; PPC64LE-NEXT: mr 5, 3
3630; PPC64LE-NEXT: .LBB216_1:
3631; PPC64LE-NEXT: ldarx 3, 0, 5
3632; PPC64LE-NEXT: nand 6, 4, 3
3633; PPC64LE-NEXT: stdcx. 6, 0, 5
3634; PPC64LE-NEXT: bne 0, .LBB216_1
3635; PPC64LE-NEXT: # BB#2:
3636; PPC64LE-NEXT: lwsync
3637; PPC64LE-NEXT: blr
3638 %ret = atomicrmw nand i64* %ptr, i64 %val acquire
3639 ret i64 %ret
3640}
3641
3642define i64 @test217(i64* %ptr, i64 %val) {
3643; PPC64LE-LABEL: test217:
3644; PPC64LE: # BB#0:
3645; PPC64LE-NEXT: lwsync
3646; PPC64LE-NEXT: .LBB217_1:
3647; PPC64LE-NEXT: ldarx 5, 0, 3
3648; PPC64LE-NEXT: nand 6, 4, 5
3649; PPC64LE-NEXT: stdcx. 6, 0, 3
3650; PPC64LE-NEXT: bne 0, .LBB217_1
3651; PPC64LE-NEXT: # BB#2:
3652; PPC64LE-NEXT: mr 3, 5
3653; PPC64LE-NEXT: blr
3654 %ret = atomicrmw nand i64* %ptr, i64 %val release
3655 ret i64 %ret
3656}
3657
3658define i64 @test218(i64* %ptr, i64 %val) {
3659; PPC64LE-LABEL: test218:
3660; PPC64LE: # BB#0:
3661; PPC64LE-NEXT: lwsync
3662; PPC64LE-NEXT: .LBB218_1:
3663; PPC64LE-NEXT: ldarx 5, 0, 3
3664; PPC64LE-NEXT: nand 6, 4, 5
3665; PPC64LE-NEXT: stdcx. 6, 0, 3
3666; PPC64LE-NEXT: bne 0, .LBB218_1
3667; PPC64LE-NEXT: # BB#2:
3668; PPC64LE-NEXT: mr 3, 5
3669; PPC64LE-NEXT: lwsync
3670; PPC64LE-NEXT: blr
3671 %ret = atomicrmw nand i64* %ptr, i64 %val acq_rel
3672 ret i64 %ret
3673}
3674
3675define i64 @test219(i64* %ptr, i64 %val) {
3676; PPC64LE-LABEL: test219:
3677; PPC64LE: # BB#0:
3678; PPC64LE-NEXT: sync
3679; PPC64LE-NEXT: .LBB219_1:
3680; PPC64LE-NEXT: ldarx 5, 0, 3
3681; PPC64LE-NEXT: nand 6, 4, 5
3682; PPC64LE-NEXT: stdcx. 6, 0, 3
3683; PPC64LE-NEXT: bne 0, .LBB219_1
3684; PPC64LE-NEXT: # BB#2:
3685; PPC64LE-NEXT: mr 3, 5
3686; PPC64LE-NEXT: lwsync
3687; PPC64LE-NEXT: blr
3688 %ret = atomicrmw nand i64* %ptr, i64 %val seq_cst
3689 ret i64 %ret
3690}
3691
3692define i8 @test220(i8* %ptr, i8 %val) {
3693; PPC64LE-LABEL: test220:
3694; PPC64LE: # BB#0:
3695; PPC64LE-NEXT: .LBB220_1:
3696; PPC64LE-NEXT: lbarx 5, 0, 3
3697; PPC64LE-NEXT: or 6, 4, 5
3698; PPC64LE-NEXT: stbcx. 6, 0, 3
3699; PPC64LE-NEXT: bne 0, .LBB220_1
3700; PPC64LE-NEXT: # BB#2:
3701; PPC64LE-NEXT: mr 3, 5
3702; PPC64LE-NEXT: blr
3703 %ret = atomicrmw or i8* %ptr, i8 %val monotonic
3704 ret i8 %ret
3705}
3706
3707define i8 @test221(i8* %ptr, i8 %val) {
3708; PPC64LE-LABEL: test221:
3709; PPC64LE: # BB#0:
3710; PPC64LE-NEXT: mr 5, 3
3711; PPC64LE-NEXT: .LBB221_1:
3712; PPC64LE-NEXT: lbarx 3, 0, 5
3713; PPC64LE-NEXT: or 6, 4, 3
3714; PPC64LE-NEXT: stbcx. 6, 0, 5
3715; PPC64LE-NEXT: bne 0, .LBB221_1
3716; PPC64LE-NEXT: # BB#2:
3717; PPC64LE-NEXT: lwsync
3718; PPC64LE-NEXT: blr
3719 %ret = atomicrmw or i8* %ptr, i8 %val acquire
3720 ret i8 %ret
3721}
3722
3723define i8 @test222(i8* %ptr, i8 %val) {
3724; PPC64LE-LABEL: test222:
3725; PPC64LE: # BB#0:
3726; PPC64LE-NEXT: lwsync
3727; PPC64LE-NEXT: .LBB222_1:
3728; PPC64LE-NEXT: lbarx 5, 0, 3
3729; PPC64LE-NEXT: or 6, 4, 5
3730; PPC64LE-NEXT: stbcx. 6, 0, 3
3731; PPC64LE-NEXT: bne 0, .LBB222_1
3732; PPC64LE-NEXT: # BB#2:
3733; PPC64LE-NEXT: mr 3, 5
3734; PPC64LE-NEXT: blr
3735 %ret = atomicrmw or i8* %ptr, i8 %val release
3736 ret i8 %ret
3737}
3738
3739define i8 @test223(i8* %ptr, i8 %val) {
3740; PPC64LE-LABEL: test223:
3741; PPC64LE: # BB#0:
3742; PPC64LE-NEXT: lwsync
3743; PPC64LE-NEXT: .LBB223_1:
3744; PPC64LE-NEXT: lbarx 5, 0, 3
3745; PPC64LE-NEXT: or 6, 4, 5
3746; PPC64LE-NEXT: stbcx. 6, 0, 3
3747; PPC64LE-NEXT: bne 0, .LBB223_1
3748; PPC64LE-NEXT: # BB#2:
3749; PPC64LE-NEXT: mr 3, 5
3750; PPC64LE-NEXT: lwsync
3751; PPC64LE-NEXT: blr
3752 %ret = atomicrmw or i8* %ptr, i8 %val acq_rel
3753 ret i8 %ret
3754}
3755
3756define i8 @test224(i8* %ptr, i8 %val) {
3757; PPC64LE-LABEL: test224:
3758; PPC64LE: # BB#0:
3759; PPC64LE-NEXT: sync
3760; PPC64LE-NEXT: .LBB224_1:
3761; PPC64LE-NEXT: lbarx 5, 0, 3
3762; PPC64LE-NEXT: or 6, 4, 5
3763; PPC64LE-NEXT: stbcx. 6, 0, 3
3764; PPC64LE-NEXT: bne 0, .LBB224_1
3765; PPC64LE-NEXT: # BB#2:
3766; PPC64LE-NEXT: mr 3, 5
3767; PPC64LE-NEXT: lwsync
3768; PPC64LE-NEXT: blr
3769 %ret = atomicrmw or i8* %ptr, i8 %val seq_cst
3770 ret i8 %ret
3771}
3772
3773define i16 @test225(i16* %ptr, i16 %val) {
3774; PPC64LE-LABEL: test225:
3775; PPC64LE: # BB#0:
3776; PPC64LE-NEXT: .LBB225_1:
3777; PPC64LE-NEXT: lharx 5, 0, 3
3778; PPC64LE-NEXT: or 6, 4, 5
3779; PPC64LE-NEXT: sthcx. 6, 0, 3
3780; PPC64LE-NEXT: bne 0, .LBB225_1
3781; PPC64LE-NEXT: # BB#2:
3782; PPC64LE-NEXT: mr 3, 5
3783; PPC64LE-NEXT: blr
3784 %ret = atomicrmw or i16* %ptr, i16 %val monotonic
3785 ret i16 %ret
3786}
3787
3788define i16 @test226(i16* %ptr, i16 %val) {
3789; PPC64LE-LABEL: test226:
3790; PPC64LE: # BB#0:
3791; PPC64LE-NEXT: mr 5, 3
3792; PPC64LE-NEXT: .LBB226_1:
3793; PPC64LE-NEXT: lharx 3, 0, 5
3794; PPC64LE-NEXT: or 6, 4, 3
3795; PPC64LE-NEXT: sthcx. 6, 0, 5
3796; PPC64LE-NEXT: bne 0, .LBB226_1
3797; PPC64LE-NEXT: # BB#2:
3798; PPC64LE-NEXT: lwsync
3799; PPC64LE-NEXT: blr
3800 %ret = atomicrmw or i16* %ptr, i16 %val acquire
3801 ret i16 %ret
3802}
3803
3804define i16 @test227(i16* %ptr, i16 %val) {
3805; PPC64LE-LABEL: test227:
3806; PPC64LE: # BB#0:
3807; PPC64LE-NEXT: lwsync
3808; PPC64LE-NEXT: .LBB227_1:
3809; PPC64LE-NEXT: lharx 5, 0, 3
3810; PPC64LE-NEXT: or 6, 4, 5
3811; PPC64LE-NEXT: sthcx. 6, 0, 3
3812; PPC64LE-NEXT: bne 0, .LBB227_1
3813; PPC64LE-NEXT: # BB#2:
3814; PPC64LE-NEXT: mr 3, 5
3815; PPC64LE-NEXT: blr
3816 %ret = atomicrmw or i16* %ptr, i16 %val release
3817 ret i16 %ret
3818}
3819
3820define i16 @test228(i16* %ptr, i16 %val) {
3821; PPC64LE-LABEL: test228:
3822; PPC64LE: # BB#0:
3823; PPC64LE-NEXT: lwsync
3824; PPC64LE-NEXT: .LBB228_1:
3825; PPC64LE-NEXT: lharx 5, 0, 3
3826; PPC64LE-NEXT: or 6, 4, 5
3827; PPC64LE-NEXT: sthcx. 6, 0, 3
3828; PPC64LE-NEXT: bne 0, .LBB228_1
3829; PPC64LE-NEXT: # BB#2:
3830; PPC64LE-NEXT: mr 3, 5
3831; PPC64LE-NEXT: lwsync
3832; PPC64LE-NEXT: blr
3833 %ret = atomicrmw or i16* %ptr, i16 %val acq_rel
3834 ret i16 %ret
3835}
3836
3837define i16 @test229(i16* %ptr, i16 %val) {
3838; PPC64LE-LABEL: test229:
3839; PPC64LE: # BB#0:
3840; PPC64LE-NEXT: sync
3841; PPC64LE-NEXT: .LBB229_1:
3842; PPC64LE-NEXT: lharx 5, 0, 3
3843; PPC64LE-NEXT: or 6, 4, 5
3844; PPC64LE-NEXT: sthcx. 6, 0, 3
3845; PPC64LE-NEXT: bne 0, .LBB229_1
3846; PPC64LE-NEXT: # BB#2:
3847; PPC64LE-NEXT: mr 3, 5
3848; PPC64LE-NEXT: lwsync
3849; PPC64LE-NEXT: blr
3850 %ret = atomicrmw or i16* %ptr, i16 %val seq_cst
3851 ret i16 %ret
3852}
3853
3854define i32 @test230(i32* %ptr, i32 %val) {
3855; PPC64LE-LABEL: test230:
3856; PPC64LE: # BB#0:
3857; PPC64LE-NEXT: .LBB230_1:
3858; PPC64LE-NEXT: lwarx 5, 0, 3
3859; PPC64LE-NEXT: or 6, 4, 5
3860; PPC64LE-NEXT: stwcx. 6, 0, 3
3861; PPC64LE-NEXT: bne 0, .LBB230_1
3862; PPC64LE-NEXT: # BB#2:
3863; PPC64LE-NEXT: mr 3, 5
3864; PPC64LE-NEXT: blr
3865 %ret = atomicrmw or i32* %ptr, i32 %val monotonic
3866 ret i32 %ret
3867}
3868
3869define i32 @test231(i32* %ptr, i32 %val) {
3870; PPC64LE-LABEL: test231:
3871; PPC64LE: # BB#0:
3872; PPC64LE-NEXT: mr 5, 3
3873; PPC64LE-NEXT: .LBB231_1:
3874; PPC64LE-NEXT: lwarx 3, 0, 5
3875; PPC64LE-NEXT: or 6, 4, 3
3876; PPC64LE-NEXT: stwcx. 6, 0, 5
3877; PPC64LE-NEXT: bne 0, .LBB231_1
3878; PPC64LE-NEXT: # BB#2:
3879; PPC64LE-NEXT: lwsync
3880; PPC64LE-NEXT: blr
3881 %ret = atomicrmw or i32* %ptr, i32 %val acquire
3882 ret i32 %ret
3883}
3884
3885define i32 @test232(i32* %ptr, i32 %val) {
3886; PPC64LE-LABEL: test232:
3887; PPC64LE: # BB#0:
3888; PPC64LE-NEXT: lwsync
3889; PPC64LE-NEXT: .LBB232_1:
3890; PPC64LE-NEXT: lwarx 5, 0, 3
3891; PPC64LE-NEXT: or 6, 4, 5
3892; PPC64LE-NEXT: stwcx. 6, 0, 3
3893; PPC64LE-NEXT: bne 0, .LBB232_1
3894; PPC64LE-NEXT: # BB#2:
3895; PPC64LE-NEXT: mr 3, 5
3896; PPC64LE-NEXT: blr
3897 %ret = atomicrmw or i32* %ptr, i32 %val release
3898 ret i32 %ret
3899}
3900
3901define i32 @test233(i32* %ptr, i32 %val) {
3902; PPC64LE-LABEL: test233:
3903; PPC64LE: # BB#0:
3904; PPC64LE-NEXT: lwsync
3905; PPC64LE-NEXT: .LBB233_1:
3906; PPC64LE-NEXT: lwarx 5, 0, 3
3907; PPC64LE-NEXT: or 6, 4, 5
3908; PPC64LE-NEXT: stwcx. 6, 0, 3
3909; PPC64LE-NEXT: bne 0, .LBB233_1
3910; PPC64LE-NEXT: # BB#2:
3911; PPC64LE-NEXT: mr 3, 5
3912; PPC64LE-NEXT: lwsync
3913; PPC64LE-NEXT: blr
3914 %ret = atomicrmw or i32* %ptr, i32 %val acq_rel
3915 ret i32 %ret
3916}
3917
3918define i32 @test234(i32* %ptr, i32 %val) {
3919; PPC64LE-LABEL: test234:
3920; PPC64LE: # BB#0:
3921; PPC64LE-NEXT: sync
3922; PPC64LE-NEXT: .LBB234_1:
3923; PPC64LE-NEXT: lwarx 5, 0, 3
3924; PPC64LE-NEXT: or 6, 4, 5
3925; PPC64LE-NEXT: stwcx. 6, 0, 3
3926; PPC64LE-NEXT: bne 0, .LBB234_1
3927; PPC64LE-NEXT: # BB#2:
3928; PPC64LE-NEXT: mr 3, 5
3929; PPC64LE-NEXT: lwsync
3930; PPC64LE-NEXT: blr
3931 %ret = atomicrmw or i32* %ptr, i32 %val seq_cst
3932 ret i32 %ret
3933}
3934
3935define i64 @test235(i64* %ptr, i64 %val) {
3936; PPC64LE-LABEL: test235:
3937; PPC64LE: # BB#0:
3938; PPC64LE-NEXT: .LBB235_1:
3939; PPC64LE-NEXT: ldarx 5, 0, 3
3940; PPC64LE-NEXT: or 6, 4, 5
3941; PPC64LE-NEXT: stdcx. 6, 0, 3
3942; PPC64LE-NEXT: bne 0, .LBB235_1
3943; PPC64LE-NEXT: # BB#2:
3944; PPC64LE-NEXT: mr 3, 5
3945; PPC64LE-NEXT: blr
3946 %ret = atomicrmw or i64* %ptr, i64 %val monotonic
3947 ret i64 %ret
3948}
3949
3950define i64 @test236(i64* %ptr, i64 %val) {
3951; PPC64LE-LABEL: test236:
3952; PPC64LE: # BB#0:
3953; PPC64LE-NEXT: mr 5, 3
3954; PPC64LE-NEXT: .LBB236_1:
3955; PPC64LE-NEXT: ldarx 3, 0, 5
3956; PPC64LE-NEXT: or 6, 4, 3
3957; PPC64LE-NEXT: stdcx. 6, 0, 5
3958; PPC64LE-NEXT: bne 0, .LBB236_1
3959; PPC64LE-NEXT: # BB#2:
3960; PPC64LE-NEXT: lwsync
3961; PPC64LE-NEXT: blr
3962 %ret = atomicrmw or i64* %ptr, i64 %val acquire
3963 ret i64 %ret
3964}
3965
3966define i64 @test237(i64* %ptr, i64 %val) {
3967; PPC64LE-LABEL: test237:
3968; PPC64LE: # BB#0:
3969; PPC64LE-NEXT: lwsync
3970; PPC64LE-NEXT: .LBB237_1:
3971; PPC64LE-NEXT: ldarx 5, 0, 3
3972; PPC64LE-NEXT: or 6, 4, 5
3973; PPC64LE-NEXT: stdcx. 6, 0, 3
3974; PPC64LE-NEXT: bne 0, .LBB237_1
3975; PPC64LE-NEXT: # BB#2:
3976; PPC64LE-NEXT: mr 3, 5
3977; PPC64LE-NEXT: blr
3978 %ret = atomicrmw or i64* %ptr, i64 %val release
3979 ret i64 %ret
3980}
3981
3982define i64 @test238(i64* %ptr, i64 %val) {
3983; PPC64LE-LABEL: test238:
3984; PPC64LE: # BB#0:
3985; PPC64LE-NEXT: lwsync
3986; PPC64LE-NEXT: .LBB238_1:
3987; PPC64LE-NEXT: ldarx 5, 0, 3
3988; PPC64LE-NEXT: or 6, 4, 5
3989; PPC64LE-NEXT: stdcx. 6, 0, 3
3990; PPC64LE-NEXT: bne 0, .LBB238_1
3991; PPC64LE-NEXT: # BB#2:
3992; PPC64LE-NEXT: mr 3, 5
3993; PPC64LE-NEXT: lwsync
3994; PPC64LE-NEXT: blr
3995 %ret = atomicrmw or i64* %ptr, i64 %val acq_rel
3996 ret i64 %ret
3997}
3998
3999define i64 @test239(i64* %ptr, i64 %val) {
4000; PPC64LE-LABEL: test239:
4001; PPC64LE: # BB#0:
4002; PPC64LE-NEXT: sync
4003; PPC64LE-NEXT: .LBB239_1:
4004; PPC64LE-NEXT: ldarx 5, 0, 3
4005; PPC64LE-NEXT: or 6, 4, 5
4006; PPC64LE-NEXT: stdcx. 6, 0, 3
4007; PPC64LE-NEXT: bne 0, .LBB239_1
4008; PPC64LE-NEXT: # BB#2:
4009; PPC64LE-NEXT: mr 3, 5
4010; PPC64LE-NEXT: lwsync
4011; PPC64LE-NEXT: blr
4012 %ret = atomicrmw or i64* %ptr, i64 %val seq_cst
4013 ret i64 %ret
4014}
4015
4016define i8 @test240(i8* %ptr, i8 %val) {
4017; PPC64LE-LABEL: test240:
4018; PPC64LE: # BB#0:
4019; PPC64LE-NEXT: .LBB240_1:
4020; PPC64LE-NEXT: lbarx 5, 0, 3
4021; PPC64LE-NEXT: xor 6, 4, 5
4022; PPC64LE-NEXT: stbcx. 6, 0, 3
4023; PPC64LE-NEXT: bne 0, .LBB240_1
4024; PPC64LE-NEXT: # BB#2:
4025; PPC64LE-NEXT: mr 3, 5
4026; PPC64LE-NEXT: blr
4027 %ret = atomicrmw xor i8* %ptr, i8 %val monotonic
4028 ret i8 %ret
4029}
4030
4031define i8 @test241(i8* %ptr, i8 %val) {
4032; PPC64LE-LABEL: test241:
4033; PPC64LE: # BB#0:
4034; PPC64LE-NEXT: mr 5, 3
4035; PPC64LE-NEXT: .LBB241_1:
4036; PPC64LE-NEXT: lbarx 3, 0, 5
4037; PPC64LE-NEXT: xor 6, 4, 3
4038; PPC64LE-NEXT: stbcx. 6, 0, 5
4039; PPC64LE-NEXT: bne 0, .LBB241_1
4040; PPC64LE-NEXT: # BB#2:
4041; PPC64LE-NEXT: lwsync
4042; PPC64LE-NEXT: blr
4043 %ret = atomicrmw xor i8* %ptr, i8 %val acquire
4044 ret i8 %ret
4045}
4046
4047define i8 @test242(i8* %ptr, i8 %val) {
4048; PPC64LE-LABEL: test242:
4049; PPC64LE: # BB#0:
4050; PPC64LE-NEXT: lwsync
4051; PPC64LE-NEXT: .LBB242_1:
4052; PPC64LE-NEXT: lbarx 5, 0, 3
4053; PPC64LE-NEXT: xor 6, 4, 5
4054; PPC64LE-NEXT: stbcx. 6, 0, 3
4055; PPC64LE-NEXT: bne 0, .LBB242_1
4056; PPC64LE-NEXT: # BB#2:
4057; PPC64LE-NEXT: mr 3, 5
4058; PPC64LE-NEXT: blr
4059 %ret = atomicrmw xor i8* %ptr, i8 %val release
4060 ret i8 %ret
4061}
4062
4063define i8 @test243(i8* %ptr, i8 %val) {
4064; PPC64LE-LABEL: test243:
4065; PPC64LE: # BB#0:
4066; PPC64LE-NEXT: lwsync
4067; PPC64LE-NEXT: .LBB243_1:
4068; PPC64LE-NEXT: lbarx 5, 0, 3
4069; PPC64LE-NEXT: xor 6, 4, 5
4070; PPC64LE-NEXT: stbcx. 6, 0, 3
4071; PPC64LE-NEXT: bne 0, .LBB243_1
4072; PPC64LE-NEXT: # BB#2:
4073; PPC64LE-NEXT: mr 3, 5
4074; PPC64LE-NEXT: lwsync
4075; PPC64LE-NEXT: blr
4076 %ret = atomicrmw xor i8* %ptr, i8 %val acq_rel
4077 ret i8 %ret
4078}
4079
4080define i8 @test244(i8* %ptr, i8 %val) {
4081; PPC64LE-LABEL: test244:
4082; PPC64LE: # BB#0:
4083; PPC64LE-NEXT: sync
4084; PPC64LE-NEXT: .LBB244_1:
4085; PPC64LE-NEXT: lbarx 5, 0, 3
4086; PPC64LE-NEXT: xor 6, 4, 5
4087; PPC64LE-NEXT: stbcx. 6, 0, 3
4088; PPC64LE-NEXT: bne 0, .LBB244_1
4089; PPC64LE-NEXT: # BB#2:
4090; PPC64LE-NEXT: mr 3, 5
4091; PPC64LE-NEXT: lwsync
4092; PPC64LE-NEXT: blr
4093 %ret = atomicrmw xor i8* %ptr, i8 %val seq_cst
4094 ret i8 %ret
4095}
4096
4097define i16 @test245(i16* %ptr, i16 %val) {
4098; PPC64LE-LABEL: test245:
4099; PPC64LE: # BB#0:
4100; PPC64LE-NEXT: .LBB245_1:
4101; PPC64LE-NEXT: lharx 5, 0, 3
4102; PPC64LE-NEXT: xor 6, 4, 5
4103; PPC64LE-NEXT: sthcx. 6, 0, 3
4104; PPC64LE-NEXT: bne 0, .LBB245_1
4105; PPC64LE-NEXT: # BB#2:
4106; PPC64LE-NEXT: mr 3, 5
4107; PPC64LE-NEXT: blr
4108 %ret = atomicrmw xor i16* %ptr, i16 %val monotonic
4109 ret i16 %ret
4110}
4111
4112define i16 @test246(i16* %ptr, i16 %val) {
4113; PPC64LE-LABEL: test246:
4114; PPC64LE: # BB#0:
4115; PPC64LE-NEXT: mr 5, 3
4116; PPC64LE-NEXT: .LBB246_1:
4117; PPC64LE-NEXT: lharx 3, 0, 5
4118; PPC64LE-NEXT: xor 6, 4, 3
4119; PPC64LE-NEXT: sthcx. 6, 0, 5
4120; PPC64LE-NEXT: bne 0, .LBB246_1
4121; PPC64LE-NEXT: # BB#2:
4122; PPC64LE-NEXT: lwsync
4123; PPC64LE-NEXT: blr
4124 %ret = atomicrmw xor i16* %ptr, i16 %val acquire
4125 ret i16 %ret
4126}
4127
4128define i16 @test247(i16* %ptr, i16 %val) {
4129; PPC64LE-LABEL: test247:
4130; PPC64LE: # BB#0:
4131; PPC64LE-NEXT: lwsync
4132; PPC64LE-NEXT: .LBB247_1:
4133; PPC64LE-NEXT: lharx 5, 0, 3
4134; PPC64LE-NEXT: xor 6, 4, 5
4135; PPC64LE-NEXT: sthcx. 6, 0, 3
4136; PPC64LE-NEXT: bne 0, .LBB247_1
4137; PPC64LE-NEXT: # BB#2:
4138; PPC64LE-NEXT: mr 3, 5
4139; PPC64LE-NEXT: blr
4140 %ret = atomicrmw xor i16* %ptr, i16 %val release
4141 ret i16 %ret
4142}
4143
4144define i16 @test248(i16* %ptr, i16 %val) {
4145; PPC64LE-LABEL: test248:
4146; PPC64LE: # BB#0:
4147; PPC64LE-NEXT: lwsync
4148; PPC64LE-NEXT: .LBB248_1:
4149; PPC64LE-NEXT: lharx 5, 0, 3
4150; PPC64LE-NEXT: xor 6, 4, 5
4151; PPC64LE-NEXT: sthcx. 6, 0, 3
4152; PPC64LE-NEXT: bne 0, .LBB248_1
4153; PPC64LE-NEXT: # BB#2:
4154; PPC64LE-NEXT: mr 3, 5
4155; PPC64LE-NEXT: lwsync
4156; PPC64LE-NEXT: blr
4157 %ret = atomicrmw xor i16* %ptr, i16 %val acq_rel
4158 ret i16 %ret
4159}
4160
4161define i16 @test249(i16* %ptr, i16 %val) {
4162; PPC64LE-LABEL: test249:
4163; PPC64LE: # BB#0:
4164; PPC64LE-NEXT: sync
4165; PPC64LE-NEXT: .LBB249_1:
4166; PPC64LE-NEXT: lharx 5, 0, 3
4167; PPC64LE-NEXT: xor 6, 4, 5
4168; PPC64LE-NEXT: sthcx. 6, 0, 3
4169; PPC64LE-NEXT: bne 0, .LBB249_1
4170; PPC64LE-NEXT: # BB#2:
4171; PPC64LE-NEXT: mr 3, 5
4172; PPC64LE-NEXT: lwsync
4173; PPC64LE-NEXT: blr
4174 %ret = atomicrmw xor i16* %ptr, i16 %val seq_cst
4175 ret i16 %ret
4176}
4177
4178define i32 @test250(i32* %ptr, i32 %val) {
4179; PPC64LE-LABEL: test250:
4180; PPC64LE: # BB#0:
4181; PPC64LE-NEXT: .LBB250_1:
4182; PPC64LE-NEXT: lwarx 5, 0, 3
4183; PPC64LE-NEXT: xor 6, 4, 5
4184; PPC64LE-NEXT: stwcx. 6, 0, 3
4185; PPC64LE-NEXT: bne 0, .LBB250_1
4186; PPC64LE-NEXT: # BB#2:
4187; PPC64LE-NEXT: mr 3, 5
4188; PPC64LE-NEXT: blr
4189 %ret = atomicrmw xor i32* %ptr, i32 %val monotonic
4190 ret i32 %ret
4191}
4192
4193define i32 @test251(i32* %ptr, i32 %val) {
4194; PPC64LE-LABEL: test251:
4195; PPC64LE: # BB#0:
4196; PPC64LE-NEXT: mr 5, 3
4197; PPC64LE-NEXT: .LBB251_1:
4198; PPC64LE-NEXT: lwarx 3, 0, 5
4199; PPC64LE-NEXT: xor 6, 4, 3
4200; PPC64LE-NEXT: stwcx. 6, 0, 5
4201; PPC64LE-NEXT: bne 0, .LBB251_1
4202; PPC64LE-NEXT: # BB#2:
4203; PPC64LE-NEXT: lwsync
4204; PPC64LE-NEXT: blr
4205 %ret = atomicrmw xor i32* %ptr, i32 %val acquire
4206 ret i32 %ret
4207}
4208
4209define i32 @test252(i32* %ptr, i32 %val) {
4210; PPC64LE-LABEL: test252:
4211; PPC64LE: # BB#0:
4212; PPC64LE-NEXT: lwsync
4213; PPC64LE-NEXT: .LBB252_1:
4214; PPC64LE-NEXT: lwarx 5, 0, 3
4215; PPC64LE-NEXT: xor 6, 4, 5
4216; PPC64LE-NEXT: stwcx. 6, 0, 3
4217; PPC64LE-NEXT: bne 0, .LBB252_1
4218; PPC64LE-NEXT: # BB#2:
4219; PPC64LE-NEXT: mr 3, 5
4220; PPC64LE-NEXT: blr
4221 %ret = atomicrmw xor i32* %ptr, i32 %val release
4222 ret i32 %ret
4223}
4224
4225define i32 @test253(i32* %ptr, i32 %val) {
4226; PPC64LE-LABEL: test253:
4227; PPC64LE: # BB#0:
4228; PPC64LE-NEXT: lwsync
4229; PPC64LE-NEXT: .LBB253_1:
4230; PPC64LE-NEXT: lwarx 5, 0, 3
4231; PPC64LE-NEXT: xor 6, 4, 5
4232; PPC64LE-NEXT: stwcx. 6, 0, 3
4233; PPC64LE-NEXT: bne 0, .LBB253_1
4234; PPC64LE-NEXT: # BB#2:
4235; PPC64LE-NEXT: mr 3, 5
4236; PPC64LE-NEXT: lwsync
4237; PPC64LE-NEXT: blr
4238 %ret = atomicrmw xor i32* %ptr, i32 %val acq_rel
4239 ret i32 %ret
4240}
4241
4242define i32 @test254(i32* %ptr, i32 %val) {
4243; PPC64LE-LABEL: test254:
4244; PPC64LE: # BB#0:
4245; PPC64LE-NEXT: sync
4246; PPC64LE-NEXT: .LBB254_1:
4247; PPC64LE-NEXT: lwarx 5, 0, 3
4248; PPC64LE-NEXT: xor 6, 4, 5
4249; PPC64LE-NEXT: stwcx. 6, 0, 3
4250; PPC64LE-NEXT: bne 0, .LBB254_1
4251; PPC64LE-NEXT: # BB#2:
4252; PPC64LE-NEXT: mr 3, 5
4253; PPC64LE-NEXT: lwsync
4254; PPC64LE-NEXT: blr
4255 %ret = atomicrmw xor i32* %ptr, i32 %val seq_cst
4256 ret i32 %ret
4257}
4258
4259define i64 @test255(i64* %ptr, i64 %val) {
4260; PPC64LE-LABEL: test255:
4261; PPC64LE: # BB#0:
4262; PPC64LE-NEXT: .LBB255_1:
4263; PPC64LE-NEXT: ldarx 5, 0, 3
4264; PPC64LE-NEXT: xor 6, 4, 5
4265; PPC64LE-NEXT: stdcx. 6, 0, 3
4266; PPC64LE-NEXT: bne 0, .LBB255_1
4267; PPC64LE-NEXT: # BB#2:
4268; PPC64LE-NEXT: mr 3, 5
4269; PPC64LE-NEXT: blr
4270 %ret = atomicrmw xor i64* %ptr, i64 %val monotonic
4271 ret i64 %ret
4272}
4273
4274define i64 @test256(i64* %ptr, i64 %val) {
4275; PPC64LE-LABEL: test256:
4276; PPC64LE: # BB#0:
4277; PPC64LE-NEXT: mr 5, 3
4278; PPC64LE-NEXT: .LBB256_1:
4279; PPC64LE-NEXT: ldarx 3, 0, 5
4280; PPC64LE-NEXT: xor 6, 4, 3
4281; PPC64LE-NEXT: stdcx. 6, 0, 5
4282; PPC64LE-NEXT: bne 0, .LBB256_1
4283; PPC64LE-NEXT: # BB#2:
4284; PPC64LE-NEXT: lwsync
4285; PPC64LE-NEXT: blr
4286 %ret = atomicrmw xor i64* %ptr, i64 %val acquire
4287 ret i64 %ret
4288}
4289
4290define i64 @test257(i64* %ptr, i64 %val) {
4291; PPC64LE-LABEL: test257:
4292; PPC64LE: # BB#0:
4293; PPC64LE-NEXT: lwsync
4294; PPC64LE-NEXT: .LBB257_1:
4295; PPC64LE-NEXT: ldarx 5, 0, 3
4296; PPC64LE-NEXT: xor 6, 4, 5
4297; PPC64LE-NEXT: stdcx. 6, 0, 3
4298; PPC64LE-NEXT: bne 0, .LBB257_1
4299; PPC64LE-NEXT: # BB#2:
4300; PPC64LE-NEXT: mr 3, 5
4301; PPC64LE-NEXT: blr
4302 %ret = atomicrmw xor i64* %ptr, i64 %val release
4303 ret i64 %ret
4304}
4305
4306define i64 @test258(i64* %ptr, i64 %val) {
4307; PPC64LE-LABEL: test258:
4308; PPC64LE: # BB#0:
4309; PPC64LE-NEXT: lwsync
4310; PPC64LE-NEXT: .LBB258_1:
4311; PPC64LE-NEXT: ldarx 5, 0, 3
4312; PPC64LE-NEXT: xor 6, 4, 5
4313; PPC64LE-NEXT: stdcx. 6, 0, 3
4314; PPC64LE-NEXT: bne 0, .LBB258_1
4315; PPC64LE-NEXT: # BB#2:
4316; PPC64LE-NEXT: mr 3, 5
4317; PPC64LE-NEXT: lwsync
4318; PPC64LE-NEXT: blr
4319 %ret = atomicrmw xor i64* %ptr, i64 %val acq_rel
4320 ret i64 %ret
4321}
4322
4323define i64 @test259(i64* %ptr, i64 %val) {
4324; PPC64LE-LABEL: test259:
4325; PPC64LE: # BB#0:
4326; PPC64LE-NEXT: sync
4327; PPC64LE-NEXT: .LBB259_1:
4328; PPC64LE-NEXT: ldarx 5, 0, 3
4329; PPC64LE-NEXT: xor 6, 4, 5
4330; PPC64LE-NEXT: stdcx. 6, 0, 3
4331; PPC64LE-NEXT: bne 0, .LBB259_1
4332; PPC64LE-NEXT: # BB#2:
4333; PPC64LE-NEXT: mr 3, 5
4334; PPC64LE-NEXT: lwsync
4335; PPC64LE-NEXT: blr
4336 %ret = atomicrmw xor i64* %ptr, i64 %val seq_cst
4337 ret i64 %ret
4338}
4339
4340define i8 @test260(i8* %ptr, i8 %val) {
4341; PPC64LE-LABEL: test260:
4342; PPC64LE: # BB#0:
4343; PPC64LE-NEXT: .LBB260_1:
4344; PPC64LE-NEXT: lbarx 5, 0, 3
4345; PPC64LE-NEXT: extsb 6, 5
4346; PPC64LE-NEXT: cmpw 4, 6
4347; PPC64LE-NEXT: ble 0, .LBB260_3
4348; PPC64LE-NEXT: # BB#2:
4349; PPC64LE-NEXT: stbcx. 4, 0, 3
4350; PPC64LE-NEXT: bne 0, .LBB260_1
4351; PPC64LE-NEXT: .LBB260_3:
4352; PPC64LE-NEXT: mr 3, 5
4353; PPC64LE-NEXT: blr
4354 %ret = atomicrmw max i8* %ptr, i8 %val monotonic
4355 ret i8 %ret
4356}
4357
4358define i8 @test261(i8* %ptr, i8 %val) {
4359; PPC64LE-LABEL: test261:
4360; PPC64LE: # BB#0:
4361; PPC64LE-NEXT: mr 5, 3
4362; PPC64LE-NEXT: .LBB261_1:
4363; PPC64LE-NEXT: lbarx 3, 0, 5
4364; PPC64LE-NEXT: extsb 6, 3
4365; PPC64LE-NEXT: cmpw 4, 6
4366; PPC64LE-NEXT: ble 0, .LBB261_3
4367; PPC64LE-NEXT: # BB#2:
4368; PPC64LE-NEXT: stbcx. 4, 0, 5
4369; PPC64LE-NEXT: bne 0, .LBB261_1
4370; PPC64LE-NEXT: .LBB261_3:
4371; PPC64LE-NEXT: lwsync
4372; PPC64LE-NEXT: blr
4373 %ret = atomicrmw max i8* %ptr, i8 %val acquire
4374 ret i8 %ret
4375}
4376
4377define i8 @test262(i8* %ptr, i8 %val) {
4378; PPC64LE-LABEL: test262:
4379; PPC64LE: # BB#0:
4380; PPC64LE-NEXT: lwsync
4381; PPC64LE-NEXT: .LBB262_1:
4382; PPC64LE-NEXT: lbarx 5, 0, 3
4383; PPC64LE-NEXT: extsb 6, 5
4384; PPC64LE-NEXT: cmpw 4, 6
4385; PPC64LE-NEXT: ble 0, .LBB262_3
4386; PPC64LE-NEXT: # BB#2:
4387; PPC64LE-NEXT: stbcx. 4, 0, 3
4388; PPC64LE-NEXT: bne 0, .LBB262_1
4389; PPC64LE-NEXT: .LBB262_3:
4390; PPC64LE-NEXT: mr 3, 5
4391; PPC64LE-NEXT: blr
4392 %ret = atomicrmw max i8* %ptr, i8 %val release
4393 ret i8 %ret
4394}
4395
4396define i8 @test263(i8* %ptr, i8 %val) {
4397; PPC64LE-LABEL: test263:
4398; PPC64LE: # BB#0:
4399; PPC64LE-NEXT: lwsync
4400; PPC64LE-NEXT: .LBB263_1:
4401; PPC64LE-NEXT: lbarx 5, 0, 3
4402; PPC64LE-NEXT: extsb 6, 5
4403; PPC64LE-NEXT: cmpw 4, 6
4404; PPC64LE-NEXT: ble 0, .LBB263_3
4405; PPC64LE-NEXT: # BB#2:
4406; PPC64LE-NEXT: stbcx. 4, 0, 3
4407; PPC64LE-NEXT: bne 0, .LBB263_1
4408; PPC64LE-NEXT: .LBB263_3:
4409; PPC64LE-NEXT: mr 3, 5
4410; PPC64LE-NEXT: lwsync
4411; PPC64LE-NEXT: blr
4412 %ret = atomicrmw max i8* %ptr, i8 %val acq_rel
4413 ret i8 %ret
4414}
4415
4416define i8 @test264(i8* %ptr, i8 %val) {
4417; PPC64LE-LABEL: test264:
4418; PPC64LE: # BB#0:
4419; PPC64LE-NEXT: sync
4420; PPC64LE-NEXT: .LBB264_1:
4421; PPC64LE-NEXT: lbarx 5, 0, 3
4422; PPC64LE-NEXT: extsb 6, 5
4423; PPC64LE-NEXT: cmpw 4, 6
4424; PPC64LE-NEXT: ble 0, .LBB264_3
4425; PPC64LE-NEXT: # BB#2:
4426; PPC64LE-NEXT: stbcx. 4, 0, 3
4427; PPC64LE-NEXT: bne 0, .LBB264_1
4428; PPC64LE-NEXT: .LBB264_3:
4429; PPC64LE-NEXT: mr 3, 5
4430; PPC64LE-NEXT: lwsync
4431; PPC64LE-NEXT: blr
4432 %ret = atomicrmw max i8* %ptr, i8 %val seq_cst
4433 ret i8 %ret
4434}
4435
4436define i16 @test265(i16* %ptr, i16 %val) {
4437; PPC64LE-LABEL: test265:
4438; PPC64LE: # BB#0:
4439; PPC64LE-NEXT: .LBB265_1:
4440; PPC64LE-NEXT: lharx 5, 0, 3
4441; PPC64LE-NEXT: extsh 6, 5
4442; PPC64LE-NEXT: cmpw 4, 6
4443; PPC64LE-NEXT: ble 0, .LBB265_3
4444; PPC64LE-NEXT: # BB#2:
4445; PPC64LE-NEXT: sthcx. 4, 0, 3
4446; PPC64LE-NEXT: bne 0, .LBB265_1
4447; PPC64LE-NEXT: .LBB265_3:
4448; PPC64LE-NEXT: mr 3, 5
4449; PPC64LE-NEXT: blr
4450 %ret = atomicrmw max i16* %ptr, i16 %val monotonic
4451 ret i16 %ret
4452}
4453
4454define i16 @test266(i16* %ptr, i16 %val) {
4455; PPC64LE-LABEL: test266:
4456; PPC64LE: # BB#0:
4457; PPC64LE-NEXT: mr 5, 3
4458; PPC64LE-NEXT: .LBB266_1:
4459; PPC64LE-NEXT: lharx 3, 0, 5
4460; PPC64LE-NEXT: extsh 6, 3
4461; PPC64LE-NEXT: cmpw 4, 6
4462; PPC64LE-NEXT: ble 0, .LBB266_3
4463; PPC64LE-NEXT: # BB#2:
4464; PPC64LE-NEXT: sthcx. 4, 0, 5
4465; PPC64LE-NEXT: bne 0, .LBB266_1
4466; PPC64LE-NEXT: .LBB266_3:
4467; PPC64LE-NEXT: lwsync
4468; PPC64LE-NEXT: blr
4469 %ret = atomicrmw max i16* %ptr, i16 %val acquire
4470 ret i16 %ret
4471}
4472
4473define i16 @test267(i16* %ptr, i16 %val) {
4474; PPC64LE-LABEL: test267:
4475; PPC64LE: # BB#0:
4476; PPC64LE-NEXT: lwsync
4477; PPC64LE-NEXT: .LBB267_1:
4478; PPC64LE-NEXT: lharx 5, 0, 3
4479; PPC64LE-NEXT: extsh 6, 5
4480; PPC64LE-NEXT: cmpw 4, 6
4481; PPC64LE-NEXT: ble 0, .LBB267_3
4482; PPC64LE-NEXT: # BB#2:
4483; PPC64LE-NEXT: sthcx. 4, 0, 3
4484; PPC64LE-NEXT: bne 0, .LBB267_1
4485; PPC64LE-NEXT: .LBB267_3:
4486; PPC64LE-NEXT: mr 3, 5
4487; PPC64LE-NEXT: blr
4488 %ret = atomicrmw max i16* %ptr, i16 %val release
4489 ret i16 %ret
4490}
4491
4492define i16 @test268(i16* %ptr, i16 %val) {
4493; PPC64LE-LABEL: test268:
4494; PPC64LE: # BB#0:
4495; PPC64LE-NEXT: lwsync
4496; PPC64LE-NEXT: .LBB268_1:
4497; PPC64LE-NEXT: lharx 5, 0, 3
4498; PPC64LE-NEXT: extsh 6, 5
4499; PPC64LE-NEXT: cmpw 4, 6
4500; PPC64LE-NEXT: ble 0, .LBB268_3
4501; PPC64LE-NEXT: # BB#2:
4502; PPC64LE-NEXT: sthcx. 4, 0, 3
4503; PPC64LE-NEXT: bne 0, .LBB268_1
4504; PPC64LE-NEXT: .LBB268_3:
4505; PPC64LE-NEXT: mr 3, 5
4506; PPC64LE-NEXT: lwsync
4507; PPC64LE-NEXT: blr
4508 %ret = atomicrmw max i16* %ptr, i16 %val acq_rel
4509 ret i16 %ret
4510}
4511
4512define i16 @test269(i16* %ptr, i16 %val) {
4513; PPC64LE-LABEL: test269:
4514; PPC64LE: # BB#0:
4515; PPC64LE-NEXT: sync
4516; PPC64LE-NEXT: .LBB269_1:
4517; PPC64LE-NEXT: lharx 5, 0, 3
4518; PPC64LE-NEXT: extsh 6, 5
4519; PPC64LE-NEXT: cmpw 4, 6
4520; PPC64LE-NEXT: ble 0, .LBB269_3
4521; PPC64LE-NEXT: # BB#2:
4522; PPC64LE-NEXT: sthcx. 4, 0, 3
4523; PPC64LE-NEXT: bne 0, .LBB269_1
4524; PPC64LE-NEXT: .LBB269_3:
4525; PPC64LE-NEXT: mr 3, 5
4526; PPC64LE-NEXT: lwsync
4527; PPC64LE-NEXT: blr
4528 %ret = atomicrmw max i16* %ptr, i16 %val seq_cst
4529 ret i16 %ret
4530}
4531
4532define i32 @test270(i32* %ptr, i32 %val) {
4533; PPC64LE-LABEL: test270:
4534; PPC64LE: # BB#0:
4535; PPC64LE-NEXT: .LBB270_1:
4536; PPC64LE-NEXT: lwarx 5, 0, 3
4537; PPC64LE-NEXT: cmpw 4, 5
4538; PPC64LE-NEXT: ble 0, .LBB270_3
4539; PPC64LE-NEXT: # BB#2:
4540; PPC64LE-NEXT: stwcx. 4, 0, 3
4541; PPC64LE-NEXT: bne 0, .LBB270_1
4542; PPC64LE-NEXT: .LBB270_3:
4543; PPC64LE-NEXT: mr 3, 5
4544; PPC64LE-NEXT: blr
4545 %ret = atomicrmw max i32* %ptr, i32 %val monotonic
4546 ret i32 %ret
4547}
4548
4549define i32 @test271(i32* %ptr, i32 %val) {
4550; PPC64LE-LABEL: test271:
4551; PPC64LE: # BB#0:
4552; PPC64LE-NEXT: mr 5, 3
4553; PPC64LE-NEXT: .LBB271_1:
4554; PPC64LE-NEXT: lwarx 3, 0, 5
4555; PPC64LE-NEXT: cmpw 4, 3
4556; PPC64LE-NEXT: ble 0, .LBB271_3
4557; PPC64LE-NEXT: # BB#2:
4558; PPC64LE-NEXT: stwcx. 4, 0, 5
4559; PPC64LE-NEXT: bne 0, .LBB271_1
4560; PPC64LE-NEXT: .LBB271_3:
4561; PPC64LE-NEXT: lwsync
4562; PPC64LE-NEXT: blr
4563 %ret = atomicrmw max i32* %ptr, i32 %val acquire
4564 ret i32 %ret
4565}
4566
4567define i32 @test272(i32* %ptr, i32 %val) {
4568; PPC64LE-LABEL: test272:
4569; PPC64LE: # BB#0:
4570; PPC64LE-NEXT: lwsync
4571; PPC64LE-NEXT: .LBB272_1:
4572; PPC64LE-NEXT: lwarx 5, 0, 3
4573; PPC64LE-NEXT: cmpw 4, 5
4574; PPC64LE-NEXT: ble 0, .LBB272_3
4575; PPC64LE-NEXT: # BB#2:
4576; PPC64LE-NEXT: stwcx. 4, 0, 3
4577; PPC64LE-NEXT: bne 0, .LBB272_1
4578; PPC64LE-NEXT: .LBB272_3:
4579; PPC64LE-NEXT: mr 3, 5
4580; PPC64LE-NEXT: blr
4581 %ret = atomicrmw max i32* %ptr, i32 %val release
4582 ret i32 %ret
4583}
4584
4585define i32 @test273(i32* %ptr, i32 %val) {
4586; PPC64LE-LABEL: test273:
4587; PPC64LE: # BB#0:
4588; PPC64LE-NEXT: lwsync
4589; PPC64LE-NEXT: .LBB273_1:
4590; PPC64LE-NEXT: lwarx 5, 0, 3
4591; PPC64LE-NEXT: cmpw 4, 5
4592; PPC64LE-NEXT: ble 0, .LBB273_3
4593; PPC64LE-NEXT: # BB#2:
4594; PPC64LE-NEXT: stwcx. 4, 0, 3
4595; PPC64LE-NEXT: bne 0, .LBB273_1
4596; PPC64LE-NEXT: .LBB273_3:
4597; PPC64LE-NEXT: mr 3, 5
4598; PPC64LE-NEXT: lwsync
4599; PPC64LE-NEXT: blr
4600 %ret = atomicrmw max i32* %ptr, i32 %val acq_rel
4601 ret i32 %ret
4602}
4603
4604define i32 @test274(i32* %ptr, i32 %val) {
4605; PPC64LE-LABEL: test274:
4606; PPC64LE: # BB#0:
4607; PPC64LE-NEXT: sync
4608; PPC64LE-NEXT: .LBB274_1:
4609; PPC64LE-NEXT: lwarx 5, 0, 3
4610; PPC64LE-NEXT: cmpw 4, 5
4611; PPC64LE-NEXT: ble 0, .LBB274_3
4612; PPC64LE-NEXT: # BB#2:
4613; PPC64LE-NEXT: stwcx. 4, 0, 3
4614; PPC64LE-NEXT: bne 0, .LBB274_1
4615; PPC64LE-NEXT: .LBB274_3:
4616; PPC64LE-NEXT: mr 3, 5
4617; PPC64LE-NEXT: lwsync
4618; PPC64LE-NEXT: blr
4619 %ret = atomicrmw max i32* %ptr, i32 %val seq_cst
4620 ret i32 %ret
4621}
4622
4623define i64 @test275(i64* %ptr, i64 %val) {
4624; PPC64LE-LABEL: test275:
4625; PPC64LE: # BB#0:
4626; PPC64LE-NEXT: .LBB275_1:
4627; PPC64LE-NEXT: ldarx 5, 0, 3
4628; PPC64LE-NEXT: cmpd 4, 5
4629; PPC64LE-NEXT: ble 0, .LBB275_3
4630; PPC64LE-NEXT: # BB#2:
4631; PPC64LE-NEXT: stdcx. 4, 0, 3
4632; PPC64LE-NEXT: bne 0, .LBB275_1
4633; PPC64LE-NEXT: .LBB275_3:
4634; PPC64LE-NEXT: mr 3, 5
4635; PPC64LE-NEXT: blr
4636 %ret = atomicrmw max i64* %ptr, i64 %val monotonic
4637 ret i64 %ret
4638}
4639
4640define i64 @test276(i64* %ptr, i64 %val) {
4641; PPC64LE-LABEL: test276:
4642; PPC64LE: # BB#0:
4643; PPC64LE-NEXT: mr 5, 3
4644; PPC64LE-NEXT: .LBB276_1:
4645; PPC64LE-NEXT: ldarx 3, 0, 5
4646; PPC64LE-NEXT: cmpd 4, 3
4647; PPC64LE-NEXT: ble 0, .LBB276_3
4648; PPC64LE-NEXT: # BB#2:
4649; PPC64LE-NEXT: stdcx. 4, 0, 5
4650; PPC64LE-NEXT: bne 0, .LBB276_1
4651; PPC64LE-NEXT: .LBB276_3:
4652; PPC64LE-NEXT: lwsync
4653; PPC64LE-NEXT: blr
4654 %ret = atomicrmw max i64* %ptr, i64 %val acquire
4655 ret i64 %ret
4656}
4657
4658define i64 @test277(i64* %ptr, i64 %val) {
4659; PPC64LE-LABEL: test277:
4660; PPC64LE: # BB#0:
4661; PPC64LE-NEXT: lwsync
4662; PPC64LE-NEXT: .LBB277_1:
4663; PPC64LE-NEXT: ldarx 5, 0, 3
4664; PPC64LE-NEXT: cmpd 4, 5
4665; PPC64LE-NEXT: ble 0, .LBB277_3
4666; PPC64LE-NEXT: # BB#2:
4667; PPC64LE-NEXT: stdcx. 4, 0, 3
4668; PPC64LE-NEXT: bne 0, .LBB277_1
4669; PPC64LE-NEXT: .LBB277_3:
4670; PPC64LE-NEXT: mr 3, 5
4671; PPC64LE-NEXT: blr
4672 %ret = atomicrmw max i64* %ptr, i64 %val release
4673 ret i64 %ret
4674}
4675
4676define i64 @test278(i64* %ptr, i64 %val) {
4677; PPC64LE-LABEL: test278:
4678; PPC64LE: # BB#0:
4679; PPC64LE-NEXT: lwsync
4680; PPC64LE-NEXT: .LBB278_1:
4681; PPC64LE-NEXT: ldarx 5, 0, 3
4682; PPC64LE-NEXT: cmpd 4, 5
4683; PPC64LE-NEXT: ble 0, .LBB278_3
4684; PPC64LE-NEXT: # BB#2:
4685; PPC64LE-NEXT: stdcx. 4, 0, 3
4686; PPC64LE-NEXT: bne 0, .LBB278_1
4687; PPC64LE-NEXT: .LBB278_3:
4688; PPC64LE-NEXT: mr 3, 5
4689; PPC64LE-NEXT: lwsync
4690; PPC64LE-NEXT: blr
4691 %ret = atomicrmw max i64* %ptr, i64 %val acq_rel
4692 ret i64 %ret
4693}
4694
4695define i64 @test279(i64* %ptr, i64 %val) {
4696; PPC64LE-LABEL: test279:
4697; PPC64LE: # BB#0:
4698; PPC64LE-NEXT: sync
4699; PPC64LE-NEXT: .LBB279_1:
4700; PPC64LE-NEXT: ldarx 5, 0, 3
4701; PPC64LE-NEXT: cmpd 4, 5
4702; PPC64LE-NEXT: ble 0, .LBB279_3
4703; PPC64LE-NEXT: # BB#2:
4704; PPC64LE-NEXT: stdcx. 4, 0, 3
4705; PPC64LE-NEXT: bne 0, .LBB279_1
4706; PPC64LE-NEXT: .LBB279_3:
4707; PPC64LE-NEXT: mr 3, 5
4708; PPC64LE-NEXT: lwsync
4709; PPC64LE-NEXT: blr
4710 %ret = atomicrmw max i64* %ptr, i64 %val seq_cst
4711 ret i64 %ret
4712}
4713
4714define i8 @test280(i8* %ptr, i8 %val) {
4715; PPC64LE-LABEL: test280:
4716; PPC64LE: # BB#0:
4717; PPC64LE-NEXT: .LBB280_1:
4718; PPC64LE-NEXT: lbarx 5, 0, 3
4719; PPC64LE-NEXT: extsb 6, 5
4720; PPC64LE-NEXT: cmpw 4, 6
4721; PPC64LE-NEXT: bge 0, .LBB280_3
4722; PPC64LE-NEXT: # BB#2:
4723; PPC64LE-NEXT: stbcx. 4, 0, 3
4724; PPC64LE-NEXT: bne 0, .LBB280_1
4725; PPC64LE-NEXT: .LBB280_3:
4726; PPC64LE-NEXT: mr 3, 5
4727; PPC64LE-NEXT: blr
4728 %ret = atomicrmw min i8* %ptr, i8 %val monotonic
4729 ret i8 %ret
4730}
4731
4732define i8 @test281(i8* %ptr, i8 %val) {
4733; PPC64LE-LABEL: test281:
4734; PPC64LE: # BB#0:
4735; PPC64LE-NEXT: mr 5, 3
4736; PPC64LE-NEXT: .LBB281_1:
4737; PPC64LE-NEXT: lbarx 3, 0, 5
4738; PPC64LE-NEXT: extsb 6, 3
4739; PPC64LE-NEXT: cmpw 4, 6
4740; PPC64LE-NEXT: bge 0, .LBB281_3
4741; PPC64LE-NEXT: # BB#2:
4742; PPC64LE-NEXT: stbcx. 4, 0, 5
4743; PPC64LE-NEXT: bne 0, .LBB281_1
4744; PPC64LE-NEXT: .LBB281_3:
4745; PPC64LE-NEXT: lwsync
4746; PPC64LE-NEXT: blr
4747 %ret = atomicrmw min i8* %ptr, i8 %val acquire
4748 ret i8 %ret
4749}
4750
4751define i8 @test282(i8* %ptr, i8 %val) {
4752; PPC64LE-LABEL: test282:
4753; PPC64LE: # BB#0:
4754; PPC64LE-NEXT: lwsync
4755; PPC64LE-NEXT: .LBB282_1:
4756; PPC64LE-NEXT: lbarx 5, 0, 3
4757; PPC64LE-NEXT: extsb 6, 5
4758; PPC64LE-NEXT: cmpw 4, 6
4759; PPC64LE-NEXT: bge 0, .LBB282_3
4760; PPC64LE-NEXT: # BB#2:
4761; PPC64LE-NEXT: stbcx. 4, 0, 3
4762; PPC64LE-NEXT: bne 0, .LBB282_1
4763; PPC64LE-NEXT: .LBB282_3:
4764; PPC64LE-NEXT: mr 3, 5
4765; PPC64LE-NEXT: blr
4766 %ret = atomicrmw min i8* %ptr, i8 %val release
4767 ret i8 %ret
4768}
4769
4770define i8 @test283(i8* %ptr, i8 %val) {
4771; PPC64LE-LABEL: test283:
4772; PPC64LE: # BB#0:
4773; PPC64LE-NEXT: lwsync
4774; PPC64LE-NEXT: .LBB283_1:
4775; PPC64LE-NEXT: lbarx 5, 0, 3
4776; PPC64LE-NEXT: extsb 6, 5
4777; PPC64LE-NEXT: cmpw 4, 6
4778; PPC64LE-NEXT: bge 0, .LBB283_3
4779; PPC64LE-NEXT: # BB#2:
4780; PPC64LE-NEXT: stbcx. 4, 0, 3
4781; PPC64LE-NEXT: bne 0, .LBB283_1
4782; PPC64LE-NEXT: .LBB283_3:
4783; PPC64LE-NEXT: mr 3, 5
4784; PPC64LE-NEXT: lwsync
4785; PPC64LE-NEXT: blr
4786 %ret = atomicrmw min i8* %ptr, i8 %val acq_rel
4787 ret i8 %ret
4788}
4789
4790define i8 @test284(i8* %ptr, i8 %val) {
4791; PPC64LE-LABEL: test284:
4792; PPC64LE: # BB#0:
4793; PPC64LE-NEXT: sync
4794; PPC64LE-NEXT: .LBB284_1:
4795; PPC64LE-NEXT: lbarx 5, 0, 3
4796; PPC64LE-NEXT: extsb 6, 5
4797; PPC64LE-NEXT: cmpw 4, 6
4798; PPC64LE-NEXT: bge 0, .LBB284_3
4799; PPC64LE-NEXT: # BB#2:
4800; PPC64LE-NEXT: stbcx. 4, 0, 3
4801; PPC64LE-NEXT: bne 0, .LBB284_1
4802; PPC64LE-NEXT: .LBB284_3:
4803; PPC64LE-NEXT: mr 3, 5
4804; PPC64LE-NEXT: lwsync
4805; PPC64LE-NEXT: blr
4806 %ret = atomicrmw min i8* %ptr, i8 %val seq_cst
4807 ret i8 %ret
4808}
4809
4810define i16 @test285(i16* %ptr, i16 %val) {
4811; PPC64LE-LABEL: test285:
4812; PPC64LE: # BB#0:
4813; PPC64LE-NEXT: .LBB285_1:
4814; PPC64LE-NEXT: lharx 5, 0, 3
4815; PPC64LE-NEXT: extsh 6, 5
4816; PPC64LE-NEXT: cmpw 4, 6
4817; PPC64LE-NEXT: bge 0, .LBB285_3
4818; PPC64LE-NEXT: # BB#2:
4819; PPC64LE-NEXT: sthcx. 4, 0, 3
4820; PPC64LE-NEXT: bne 0, .LBB285_1
4821; PPC64LE-NEXT: .LBB285_3:
4822; PPC64LE-NEXT: mr 3, 5
4823; PPC64LE-NEXT: blr
4824 %ret = atomicrmw min i16* %ptr, i16 %val monotonic
4825 ret i16 %ret
4826}
4827
4828define i16 @test286(i16* %ptr, i16 %val) {
4829; PPC64LE-LABEL: test286:
4830; PPC64LE: # BB#0:
4831; PPC64LE-NEXT: mr 5, 3
4832; PPC64LE-NEXT: .LBB286_1:
4833; PPC64LE-NEXT: lharx 3, 0, 5
4834; PPC64LE-NEXT: extsh 6, 3
4835; PPC64LE-NEXT: cmpw 4, 6
4836; PPC64LE-NEXT: bge 0, .LBB286_3
4837; PPC64LE-NEXT: # BB#2:
4838; PPC64LE-NEXT: sthcx. 4, 0, 5
4839; PPC64LE-NEXT: bne 0, .LBB286_1
4840; PPC64LE-NEXT: .LBB286_3:
4841; PPC64LE-NEXT: lwsync
4842; PPC64LE-NEXT: blr
4843 %ret = atomicrmw min i16* %ptr, i16 %val acquire
4844 ret i16 %ret
4845}
4846
4847define i16 @test287(i16* %ptr, i16 %val) {
4848; PPC64LE-LABEL: test287:
4849; PPC64LE: # BB#0:
4850; PPC64LE-NEXT: lwsync
4851; PPC64LE-NEXT: .LBB287_1:
4852; PPC64LE-NEXT: lharx 5, 0, 3
4853; PPC64LE-NEXT: extsh 6, 5
4854; PPC64LE-NEXT: cmpw 4, 6
4855; PPC64LE-NEXT: bge 0, .LBB287_3
4856; PPC64LE-NEXT: # BB#2:
4857; PPC64LE-NEXT: sthcx. 4, 0, 3
4858; PPC64LE-NEXT: bne 0, .LBB287_1
4859; PPC64LE-NEXT: .LBB287_3:
4860; PPC64LE-NEXT: mr 3, 5
4861; PPC64LE-NEXT: blr
4862 %ret = atomicrmw min i16* %ptr, i16 %val release
4863 ret i16 %ret
4864}
4865
4866define i16 @test288(i16* %ptr, i16 %val) {
4867; PPC64LE-LABEL: test288:
4868; PPC64LE: # BB#0:
4869; PPC64LE-NEXT: lwsync
4870; PPC64LE-NEXT: .LBB288_1:
4871; PPC64LE-NEXT: lharx 5, 0, 3
4872; PPC64LE-NEXT: extsh 6, 5
4873; PPC64LE-NEXT: cmpw 4, 6
4874; PPC64LE-NEXT: bge 0, .LBB288_3
4875; PPC64LE-NEXT: # BB#2:
4876; PPC64LE-NEXT: sthcx. 4, 0, 3
4877; PPC64LE-NEXT: bne 0, .LBB288_1
4878; PPC64LE-NEXT: .LBB288_3:
4879; PPC64LE-NEXT: mr 3, 5
4880; PPC64LE-NEXT: lwsync
4881; PPC64LE-NEXT: blr
4882 %ret = atomicrmw min i16* %ptr, i16 %val acq_rel
4883 ret i16 %ret
4884}
4885
4886define i16 @test289(i16* %ptr, i16 %val) {
4887; PPC64LE-LABEL: test289:
4888; PPC64LE: # BB#0:
4889; PPC64LE-NEXT: sync
4890; PPC64LE-NEXT: .LBB289_1:
4891; PPC64LE-NEXT: lharx 5, 0, 3
4892; PPC64LE-NEXT: extsh 6, 5
4893; PPC64LE-NEXT: cmpw 4, 6
4894; PPC64LE-NEXT: bge 0, .LBB289_3
4895; PPC64LE-NEXT: # BB#2:
4896; PPC64LE-NEXT: sthcx. 4, 0, 3
4897; PPC64LE-NEXT: bne 0, .LBB289_1
4898; PPC64LE-NEXT: .LBB289_3:
4899; PPC64LE-NEXT: mr 3, 5
4900; PPC64LE-NEXT: lwsync
4901; PPC64LE-NEXT: blr
4902 %ret = atomicrmw min i16* %ptr, i16 %val seq_cst
4903 ret i16 %ret
4904}
4905
4906define i32 @test290(i32* %ptr, i32 %val) {
4907; PPC64LE-LABEL: test290:
4908; PPC64LE: # BB#0:
4909; PPC64LE-NEXT: .LBB290_1:
4910; PPC64LE-NEXT: lwarx 5, 0, 3
4911; PPC64LE-NEXT: cmpw 4, 5
4912; PPC64LE-NEXT: bge 0, .LBB290_3
4913; PPC64LE-NEXT: # BB#2:
4914; PPC64LE-NEXT: stwcx. 4, 0, 3
4915; PPC64LE-NEXT: bne 0, .LBB290_1
4916; PPC64LE-NEXT: .LBB290_3:
4917; PPC64LE-NEXT: mr 3, 5
4918; PPC64LE-NEXT: blr
4919 %ret = atomicrmw min i32* %ptr, i32 %val monotonic
4920 ret i32 %ret
4921}
4922
4923define i32 @test291(i32* %ptr, i32 %val) {
4924; PPC64LE-LABEL: test291:
4925; PPC64LE: # BB#0:
4926; PPC64LE-NEXT: mr 5, 3
4927; PPC64LE-NEXT: .LBB291_1:
4928; PPC64LE-NEXT: lwarx 3, 0, 5
4929; PPC64LE-NEXT: cmpw 4, 3
4930; PPC64LE-NEXT: bge 0, .LBB291_3
4931; PPC64LE-NEXT: # BB#2:
4932; PPC64LE-NEXT: stwcx. 4, 0, 5
4933; PPC64LE-NEXT: bne 0, .LBB291_1
4934; PPC64LE-NEXT: .LBB291_3:
4935; PPC64LE-NEXT: lwsync
4936; PPC64LE-NEXT: blr
4937 %ret = atomicrmw min i32* %ptr, i32 %val acquire
4938 ret i32 %ret
4939}
4940
4941define i32 @test292(i32* %ptr, i32 %val) {
4942; PPC64LE-LABEL: test292:
4943; PPC64LE: # BB#0:
4944; PPC64LE-NEXT: lwsync
4945; PPC64LE-NEXT: .LBB292_1:
4946; PPC64LE-NEXT: lwarx 5, 0, 3
4947; PPC64LE-NEXT: cmpw 4, 5
4948; PPC64LE-NEXT: bge 0, .LBB292_3
4949; PPC64LE-NEXT: # BB#2:
4950; PPC64LE-NEXT: stwcx. 4, 0, 3
4951; PPC64LE-NEXT: bne 0, .LBB292_1
4952; PPC64LE-NEXT: .LBB292_3:
4953; PPC64LE-NEXT: mr 3, 5
4954; PPC64LE-NEXT: blr
4955 %ret = atomicrmw min i32* %ptr, i32 %val release
4956 ret i32 %ret
4957}
4958
4959define i32 @test293(i32* %ptr, i32 %val) {
4960; PPC64LE-LABEL: test293:
4961; PPC64LE: # BB#0:
4962; PPC64LE-NEXT: lwsync
4963; PPC64LE-NEXT: .LBB293_1:
4964; PPC64LE-NEXT: lwarx 5, 0, 3
4965; PPC64LE-NEXT: cmpw 4, 5
4966; PPC64LE-NEXT: bge 0, .LBB293_3
4967; PPC64LE-NEXT: # BB#2:
4968; PPC64LE-NEXT: stwcx. 4, 0, 3
4969; PPC64LE-NEXT: bne 0, .LBB293_1
4970; PPC64LE-NEXT: .LBB293_3:
4971; PPC64LE-NEXT: mr 3, 5
4972; PPC64LE-NEXT: lwsync
4973; PPC64LE-NEXT: blr
4974 %ret = atomicrmw min i32* %ptr, i32 %val acq_rel
4975 ret i32 %ret
4976}
4977
4978define i32 @test294(i32* %ptr, i32 %val) {
4979; PPC64LE-LABEL: test294:
4980; PPC64LE: # BB#0:
4981; PPC64LE-NEXT: sync
4982; PPC64LE-NEXT: .LBB294_1:
4983; PPC64LE-NEXT: lwarx 5, 0, 3
4984; PPC64LE-NEXT: cmpw 4, 5
4985; PPC64LE-NEXT: bge 0, .LBB294_3
4986; PPC64LE-NEXT: # BB#2:
4987; PPC64LE-NEXT: stwcx. 4, 0, 3
4988; PPC64LE-NEXT: bne 0, .LBB294_1
4989; PPC64LE-NEXT: .LBB294_3:
4990; PPC64LE-NEXT: mr 3, 5
4991; PPC64LE-NEXT: lwsync
4992; PPC64LE-NEXT: blr
4993 %ret = atomicrmw min i32* %ptr, i32 %val seq_cst
4994 ret i32 %ret
4995}
4996
4997define i64 @test295(i64* %ptr, i64 %val) {
4998; PPC64LE-LABEL: test295:
4999; PPC64LE: # BB#0:
5000; PPC64LE-NEXT: .LBB295_1:
5001; PPC64LE-NEXT: ldarx 5, 0, 3
5002; PPC64LE-NEXT: cmpd 4, 5
5003; PPC64LE-NEXT: bge 0, .LBB295_3
5004; PPC64LE-NEXT: # BB#2:
5005; PPC64LE-NEXT: stdcx. 4, 0, 3
5006; PPC64LE-NEXT: bne 0, .LBB295_1
5007; PPC64LE-NEXT: .LBB295_3:
5008; PPC64LE-NEXT: mr 3, 5
5009; PPC64LE-NEXT: blr
5010 %ret = atomicrmw min i64* %ptr, i64 %val monotonic
5011 ret i64 %ret
5012}
5013
5014define i64 @test296(i64* %ptr, i64 %val) {
5015; PPC64LE-LABEL: test296:
5016; PPC64LE: # BB#0:
5017; PPC64LE-NEXT: mr 5, 3
5018; PPC64LE-NEXT: .LBB296_1:
5019; PPC64LE-NEXT: ldarx 3, 0, 5
5020; PPC64LE-NEXT: cmpd 4, 3
5021; PPC64LE-NEXT: bge 0, .LBB296_3
5022; PPC64LE-NEXT: # BB#2:
5023; PPC64LE-NEXT: stdcx. 4, 0, 5
5024; PPC64LE-NEXT: bne 0, .LBB296_1
5025; PPC64LE-NEXT: .LBB296_3:
5026; PPC64LE-NEXT: lwsync
5027; PPC64LE-NEXT: blr
5028 %ret = atomicrmw min i64* %ptr, i64 %val acquire
5029 ret i64 %ret
5030}
5031
5032define i64 @test297(i64* %ptr, i64 %val) {
5033; PPC64LE-LABEL: test297:
5034; PPC64LE: # BB#0:
5035; PPC64LE-NEXT: lwsync
5036; PPC64LE-NEXT: .LBB297_1:
5037; PPC64LE-NEXT: ldarx 5, 0, 3
5038; PPC64LE-NEXT: cmpd 4, 5
5039; PPC64LE-NEXT: bge 0, .LBB297_3
5040; PPC64LE-NEXT: # BB#2:
5041; PPC64LE-NEXT: stdcx. 4, 0, 3
5042; PPC64LE-NEXT: bne 0, .LBB297_1
5043; PPC64LE-NEXT: .LBB297_3:
5044; PPC64LE-NEXT: mr 3, 5
5045; PPC64LE-NEXT: blr
5046 %ret = atomicrmw min i64* %ptr, i64 %val release
5047 ret i64 %ret
5048}
5049
5050define i64 @test298(i64* %ptr, i64 %val) {
5051; PPC64LE-LABEL: test298:
5052; PPC64LE: # BB#0:
5053; PPC64LE-NEXT: lwsync
5054; PPC64LE-NEXT: .LBB298_1:
5055; PPC64LE-NEXT: ldarx 5, 0, 3
5056; PPC64LE-NEXT: cmpd 4, 5
5057; PPC64LE-NEXT: bge 0, .LBB298_3
5058; PPC64LE-NEXT: # BB#2:
5059; PPC64LE-NEXT: stdcx. 4, 0, 3
5060; PPC64LE-NEXT: bne 0, .LBB298_1
5061; PPC64LE-NEXT: .LBB298_3:
5062; PPC64LE-NEXT: mr 3, 5
5063; PPC64LE-NEXT: lwsync
5064; PPC64LE-NEXT: blr
5065 %ret = atomicrmw min i64* %ptr, i64 %val acq_rel
5066 ret i64 %ret
5067}
5068
5069define i64 @test299(i64* %ptr, i64 %val) {
5070; PPC64LE-LABEL: test299:
5071; PPC64LE: # BB#0:
5072; PPC64LE-NEXT: sync
5073; PPC64LE-NEXT: .LBB299_1:
5074; PPC64LE-NEXT: ldarx 5, 0, 3
5075; PPC64LE-NEXT: cmpd 4, 5
5076; PPC64LE-NEXT: bge 0, .LBB299_3
5077; PPC64LE-NEXT: # BB#2:
5078; PPC64LE-NEXT: stdcx. 4, 0, 3
5079; PPC64LE-NEXT: bne 0, .LBB299_1
5080; PPC64LE-NEXT: .LBB299_3:
5081; PPC64LE-NEXT: mr 3, 5
5082; PPC64LE-NEXT: lwsync
5083; PPC64LE-NEXT: blr
5084 %ret = atomicrmw min i64* %ptr, i64 %val seq_cst
5085 ret i64 %ret
5086}
5087
5088define i8 @test300(i8* %ptr, i8 %val) {
5089; PPC64LE-LABEL: test300:
5090; PPC64LE: # BB#0:
5091; PPC64LE-NEXT: .LBB300_1:
5092; PPC64LE-NEXT: lbarx 5, 0, 3
5093; PPC64LE-NEXT: cmplw 4, 5
5094; PPC64LE-NEXT: ble 0, .LBB300_3
5095; PPC64LE-NEXT: # BB#2:
5096; PPC64LE-NEXT: stbcx. 4, 0, 3
5097; PPC64LE-NEXT: bne 0, .LBB300_1
5098; PPC64LE-NEXT: .LBB300_3:
5099; PPC64LE-NEXT: mr 3, 5
5100; PPC64LE-NEXT: blr
5101 %ret = atomicrmw umax i8* %ptr, i8 %val monotonic
5102 ret i8 %ret
5103}
5104
5105define i8 @test301(i8* %ptr, i8 %val) {
5106; PPC64LE-LABEL: test301:
5107; PPC64LE: # BB#0:
5108; PPC64LE-NEXT: mr 5, 3
5109; PPC64LE-NEXT: .LBB301_1:
5110; PPC64LE-NEXT: lbarx 3, 0, 5
5111; PPC64LE-NEXT: cmplw 4, 3
5112; PPC64LE-NEXT: ble 0, .LBB301_3
5113; PPC64LE-NEXT: # BB#2:
5114; PPC64LE-NEXT: stbcx. 4, 0, 5
5115; PPC64LE-NEXT: bne 0, .LBB301_1
5116; PPC64LE-NEXT: .LBB301_3:
5117; PPC64LE-NEXT: lwsync
5118; PPC64LE-NEXT: blr
5119 %ret = atomicrmw umax i8* %ptr, i8 %val acquire
5120 ret i8 %ret
5121}
5122
5123define i8 @test302(i8* %ptr, i8 %val) {
5124; PPC64LE-LABEL: test302:
5125; PPC64LE: # BB#0:
5126; PPC64LE-NEXT: lwsync
5127; PPC64LE-NEXT: .LBB302_1:
5128; PPC64LE-NEXT: lbarx 5, 0, 3
5129; PPC64LE-NEXT: cmplw 4, 5
5130; PPC64LE-NEXT: ble 0, .LBB302_3
5131; PPC64LE-NEXT: # BB#2:
5132; PPC64LE-NEXT: stbcx. 4, 0, 3
5133; PPC64LE-NEXT: bne 0, .LBB302_1
5134; PPC64LE-NEXT: .LBB302_3:
5135; PPC64LE-NEXT: mr 3, 5
5136; PPC64LE-NEXT: blr
5137 %ret = atomicrmw umax i8* %ptr, i8 %val release
5138 ret i8 %ret
5139}
5140
5141define i8 @test303(i8* %ptr, i8 %val) {
5142; PPC64LE-LABEL: test303:
5143; PPC64LE: # BB#0:
5144; PPC64LE-NEXT: lwsync
5145; PPC64LE-NEXT: .LBB303_1:
5146; PPC64LE-NEXT: lbarx 5, 0, 3
5147; PPC64LE-NEXT: cmplw 4, 5
5148; PPC64LE-NEXT: ble 0, .LBB303_3
5149; PPC64LE-NEXT: # BB#2:
5150; PPC64LE-NEXT: stbcx. 4, 0, 3
5151; PPC64LE-NEXT: bne 0, .LBB303_1
5152; PPC64LE-NEXT: .LBB303_3:
5153; PPC64LE-NEXT: mr 3, 5
5154; PPC64LE-NEXT: lwsync
5155; PPC64LE-NEXT: blr
5156 %ret = atomicrmw umax i8* %ptr, i8 %val acq_rel
5157 ret i8 %ret
5158}
5159
5160define i8 @test304(i8* %ptr, i8 %val) {
5161; PPC64LE-LABEL: test304:
5162; PPC64LE: # BB#0:
5163; PPC64LE-NEXT: sync
5164; PPC64LE-NEXT: .LBB304_1:
5165; PPC64LE-NEXT: lbarx 5, 0, 3
5166; PPC64LE-NEXT: cmplw 4, 5
5167; PPC64LE-NEXT: ble 0, .LBB304_3
5168; PPC64LE-NEXT: # BB#2:
5169; PPC64LE-NEXT: stbcx. 4, 0, 3
5170; PPC64LE-NEXT: bne 0, .LBB304_1
5171; PPC64LE-NEXT: .LBB304_3:
5172; PPC64LE-NEXT: mr 3, 5
5173; PPC64LE-NEXT: lwsync
5174; PPC64LE-NEXT: blr
5175 %ret = atomicrmw umax i8* %ptr, i8 %val seq_cst
5176 ret i8 %ret
5177}
5178
5179define i16 @test305(i16* %ptr, i16 %val) {
5180; PPC64LE-LABEL: test305:
5181; PPC64LE: # BB#0:
5182; PPC64LE-NEXT: .LBB305_1:
5183; PPC64LE-NEXT: lharx 5, 0, 3
5184; PPC64LE-NEXT: cmplw 4, 5
5185; PPC64LE-NEXT: ble 0, .LBB305_3
5186; PPC64LE-NEXT: # BB#2:
5187; PPC64LE-NEXT: sthcx. 4, 0, 3
5188; PPC64LE-NEXT: bne 0, .LBB305_1
5189; PPC64LE-NEXT: .LBB305_3:
5190; PPC64LE-NEXT: mr 3, 5
5191; PPC64LE-NEXT: blr
5192 %ret = atomicrmw umax i16* %ptr, i16 %val monotonic
5193 ret i16 %ret
5194}
5195
5196define i16 @test306(i16* %ptr, i16 %val) {
5197; PPC64LE-LABEL: test306:
5198; PPC64LE: # BB#0:
5199; PPC64LE-NEXT: mr 5, 3
5200; PPC64LE-NEXT: .LBB306_1:
5201; PPC64LE-NEXT: lharx 3, 0, 5
5202; PPC64LE-NEXT: cmplw 4, 3
5203; PPC64LE-NEXT: ble 0, .LBB306_3
5204; PPC64LE-NEXT: # BB#2:
5205; PPC64LE-NEXT: sthcx. 4, 0, 5
5206; PPC64LE-NEXT: bne 0, .LBB306_1
5207; PPC64LE-NEXT: .LBB306_3:
5208; PPC64LE-NEXT: lwsync
5209; PPC64LE-NEXT: blr
5210 %ret = atomicrmw umax i16* %ptr, i16 %val acquire
5211 ret i16 %ret
5212}
5213
5214define i16 @test307(i16* %ptr, i16 %val) {
5215; PPC64LE-LABEL: test307:
5216; PPC64LE: # BB#0:
5217; PPC64LE-NEXT: lwsync
5218; PPC64LE-NEXT: .LBB307_1:
5219; PPC64LE-NEXT: lharx 5, 0, 3
5220; PPC64LE-NEXT: cmplw 4, 5
5221; PPC64LE-NEXT: ble 0, .LBB307_3
5222; PPC64LE-NEXT: # BB#2:
5223; PPC64LE-NEXT: sthcx. 4, 0, 3
5224; PPC64LE-NEXT: bne 0, .LBB307_1
5225; PPC64LE-NEXT: .LBB307_3:
5226; PPC64LE-NEXT: mr 3, 5
5227; PPC64LE-NEXT: blr
5228 %ret = atomicrmw umax i16* %ptr, i16 %val release
5229 ret i16 %ret
5230}
5231
5232define i16 @test308(i16* %ptr, i16 %val) {
5233; PPC64LE-LABEL: test308:
5234; PPC64LE: # BB#0:
5235; PPC64LE-NEXT: lwsync
5236; PPC64LE-NEXT: .LBB308_1:
5237; PPC64LE-NEXT: lharx 5, 0, 3
5238; PPC64LE-NEXT: cmplw 4, 5
5239; PPC64LE-NEXT: ble 0, .LBB308_3
5240; PPC64LE-NEXT: # BB#2:
5241; PPC64LE-NEXT: sthcx. 4, 0, 3
5242; PPC64LE-NEXT: bne 0, .LBB308_1
5243; PPC64LE-NEXT: .LBB308_3:
5244; PPC64LE-NEXT: mr 3, 5
5245; PPC64LE-NEXT: lwsync
5246; PPC64LE-NEXT: blr
5247 %ret = atomicrmw umax i16* %ptr, i16 %val acq_rel
5248 ret i16 %ret
5249}
5250
5251define i16 @test309(i16* %ptr, i16 %val) {
5252; PPC64LE-LABEL: test309:
5253; PPC64LE: # BB#0:
5254; PPC64LE-NEXT: sync
5255; PPC64LE-NEXT: .LBB309_1:
5256; PPC64LE-NEXT: lharx 5, 0, 3
5257; PPC64LE-NEXT: cmplw 4, 5
5258; PPC64LE-NEXT: ble 0, .LBB309_3
5259; PPC64LE-NEXT: # BB#2:
5260; PPC64LE-NEXT: sthcx. 4, 0, 3
5261; PPC64LE-NEXT: bne 0, .LBB309_1
5262; PPC64LE-NEXT: .LBB309_3:
5263; PPC64LE-NEXT: mr 3, 5
5264; PPC64LE-NEXT: lwsync
5265; PPC64LE-NEXT: blr
5266 %ret = atomicrmw umax i16* %ptr, i16 %val seq_cst
5267 ret i16 %ret
5268}
5269
5270define i32 @test310(i32* %ptr, i32 %val) {
5271; PPC64LE-LABEL: test310:
5272; PPC64LE: # BB#0:
5273; PPC64LE-NEXT: .LBB310_1:
5274; PPC64LE-NEXT: lwarx 5, 0, 3
5275; PPC64LE-NEXT: cmplw 4, 5
5276; PPC64LE-NEXT: ble 0, .LBB310_3
5277; PPC64LE-NEXT: # BB#2:
5278; PPC64LE-NEXT: stwcx. 4, 0, 3
5279; PPC64LE-NEXT: bne 0, .LBB310_1
5280; PPC64LE-NEXT: .LBB310_3:
5281; PPC64LE-NEXT: mr 3, 5
5282; PPC64LE-NEXT: blr
5283 %ret = atomicrmw umax i32* %ptr, i32 %val monotonic
5284 ret i32 %ret
5285}
5286
5287define i32 @test311(i32* %ptr, i32 %val) {
5288; PPC64LE-LABEL: test311:
5289; PPC64LE: # BB#0:
5290; PPC64LE-NEXT: mr 5, 3
5291; PPC64LE-NEXT: .LBB311_1:
5292; PPC64LE-NEXT: lwarx 3, 0, 5
5293; PPC64LE-NEXT: cmplw 4, 3
5294; PPC64LE-NEXT: ble 0, .LBB311_3
5295; PPC64LE-NEXT: # BB#2:
5296; PPC64LE-NEXT: stwcx. 4, 0, 5
5297; PPC64LE-NEXT: bne 0, .LBB311_1
5298; PPC64LE-NEXT: .LBB311_3:
5299; PPC64LE-NEXT: lwsync
5300; PPC64LE-NEXT: blr
5301 %ret = atomicrmw umax i32* %ptr, i32 %val acquire
5302 ret i32 %ret
5303}
5304
5305define i32 @test312(i32* %ptr, i32 %val) {
5306; PPC64LE-LABEL: test312:
5307; PPC64LE: # BB#0:
5308; PPC64LE-NEXT: lwsync
5309; PPC64LE-NEXT: .LBB312_1:
5310; PPC64LE-NEXT: lwarx 5, 0, 3
5311; PPC64LE-NEXT: cmplw 4, 5
5312; PPC64LE-NEXT: ble 0, .LBB312_3
5313; PPC64LE-NEXT: # BB#2:
5314; PPC64LE-NEXT: stwcx. 4, 0, 3
5315; PPC64LE-NEXT: bne 0, .LBB312_1
5316; PPC64LE-NEXT: .LBB312_3:
5317; PPC64LE-NEXT: mr 3, 5
5318; PPC64LE-NEXT: blr
5319 %ret = atomicrmw umax i32* %ptr, i32 %val release
5320 ret i32 %ret
5321}
5322
5323define i32 @test313(i32* %ptr, i32 %val) {
5324; PPC64LE-LABEL: test313:
5325; PPC64LE: # BB#0:
5326; PPC64LE-NEXT: lwsync
5327; PPC64LE-NEXT: .LBB313_1:
5328; PPC64LE-NEXT: lwarx 5, 0, 3
5329; PPC64LE-NEXT: cmplw 4, 5
5330; PPC64LE-NEXT: ble 0, .LBB313_3
5331; PPC64LE-NEXT: # BB#2:
5332; PPC64LE-NEXT: stwcx. 4, 0, 3
5333; PPC64LE-NEXT: bne 0, .LBB313_1
5334; PPC64LE-NEXT: .LBB313_3:
5335; PPC64LE-NEXT: mr 3, 5
5336; PPC64LE-NEXT: lwsync
5337; PPC64LE-NEXT: blr
5338 %ret = atomicrmw umax i32* %ptr, i32 %val acq_rel
5339 ret i32 %ret
5340}
5341
5342define i32 @test314(i32* %ptr, i32 %val) {
5343; PPC64LE-LABEL: test314:
5344; PPC64LE: # BB#0:
5345; PPC64LE-NEXT: sync
5346; PPC64LE-NEXT: .LBB314_1:
5347; PPC64LE-NEXT: lwarx 5, 0, 3
5348; PPC64LE-NEXT: cmplw 4, 5
5349; PPC64LE-NEXT: ble 0, .LBB314_3
5350; PPC64LE-NEXT: # BB#2:
5351; PPC64LE-NEXT: stwcx. 4, 0, 3
5352; PPC64LE-NEXT: bne 0, .LBB314_1
5353; PPC64LE-NEXT: .LBB314_3:
5354; PPC64LE-NEXT: mr 3, 5
5355; PPC64LE-NEXT: lwsync
5356; PPC64LE-NEXT: blr
5357 %ret = atomicrmw umax i32* %ptr, i32 %val seq_cst
5358 ret i32 %ret
5359}
5360
5361define i64 @test315(i64* %ptr, i64 %val) {
5362; PPC64LE-LABEL: test315:
5363; PPC64LE: # BB#0:
5364; PPC64LE-NEXT: .LBB315_1:
5365; PPC64LE-NEXT: ldarx 5, 0, 3
5366; PPC64LE-NEXT: cmpld 4, 5
5367; PPC64LE-NEXT: ble 0, .LBB315_3
5368; PPC64LE-NEXT: # BB#2:
5369; PPC64LE-NEXT: stdcx. 4, 0, 3
5370; PPC64LE-NEXT: bne 0, .LBB315_1
5371; PPC64LE-NEXT: .LBB315_3:
5372; PPC64LE-NEXT: mr 3, 5
5373; PPC64LE-NEXT: blr
5374 %ret = atomicrmw umax i64* %ptr, i64 %val monotonic
5375 ret i64 %ret
5376}
5377
5378define i64 @test316(i64* %ptr, i64 %val) {
5379; PPC64LE-LABEL: test316:
5380; PPC64LE: # BB#0:
5381; PPC64LE-NEXT: mr 5, 3
5382; PPC64LE-NEXT: .LBB316_1:
5383; PPC64LE-NEXT: ldarx 3, 0, 5
5384; PPC64LE-NEXT: cmpld 4, 3
5385; PPC64LE-NEXT: ble 0, .LBB316_3
5386; PPC64LE-NEXT: # BB#2:
5387; PPC64LE-NEXT: stdcx. 4, 0, 5
5388; PPC64LE-NEXT: bne 0, .LBB316_1
5389; PPC64LE-NEXT: .LBB316_3:
5390; PPC64LE-NEXT: lwsync
5391; PPC64LE-NEXT: blr
5392 %ret = atomicrmw umax i64* %ptr, i64 %val acquire
5393 ret i64 %ret
5394}
5395
5396define i64 @test317(i64* %ptr, i64 %val) {
5397; PPC64LE-LABEL: test317:
5398; PPC64LE: # BB#0:
5399; PPC64LE-NEXT: lwsync
5400; PPC64LE-NEXT: .LBB317_1:
5401; PPC64LE-NEXT: ldarx 5, 0, 3
5402; PPC64LE-NEXT: cmpld 4, 5
5403; PPC64LE-NEXT: ble 0, .LBB317_3
5404; PPC64LE-NEXT: # BB#2:
5405; PPC64LE-NEXT: stdcx. 4, 0, 3
5406; PPC64LE-NEXT: bne 0, .LBB317_1
5407; PPC64LE-NEXT: .LBB317_3:
5408; PPC64LE-NEXT: mr 3, 5
5409; PPC64LE-NEXT: blr
5410 %ret = atomicrmw umax i64* %ptr, i64 %val release
5411 ret i64 %ret
5412}
5413
5414define i64 @test318(i64* %ptr, i64 %val) {
5415; PPC64LE-LABEL: test318:
5416; PPC64LE: # BB#0:
5417; PPC64LE-NEXT: lwsync
5418; PPC64LE-NEXT: .LBB318_1:
5419; PPC64LE-NEXT: ldarx 5, 0, 3
5420; PPC64LE-NEXT: cmpld 4, 5
5421; PPC64LE-NEXT: ble 0, .LBB318_3
5422; PPC64LE-NEXT: # BB#2:
5423; PPC64LE-NEXT: stdcx. 4, 0, 3
5424; PPC64LE-NEXT: bne 0, .LBB318_1
5425; PPC64LE-NEXT: .LBB318_3:
5426; PPC64LE-NEXT: mr 3, 5
5427; PPC64LE-NEXT: lwsync
5428; PPC64LE-NEXT: blr
5429 %ret = atomicrmw umax i64* %ptr, i64 %val acq_rel
5430 ret i64 %ret
5431}
5432
5433define i64 @test319(i64* %ptr, i64 %val) {
5434; PPC64LE-LABEL: test319:
5435; PPC64LE: # BB#0:
5436; PPC64LE-NEXT: sync
5437; PPC64LE-NEXT: .LBB319_1:
5438; PPC64LE-NEXT: ldarx 5, 0, 3
5439; PPC64LE-NEXT: cmpld 4, 5
5440; PPC64LE-NEXT: ble 0, .LBB319_3
5441; PPC64LE-NEXT: # BB#2:
5442; PPC64LE-NEXT: stdcx. 4, 0, 3
5443; PPC64LE-NEXT: bne 0, .LBB319_1
5444; PPC64LE-NEXT: .LBB319_3:
5445; PPC64LE-NEXT: mr 3, 5
5446; PPC64LE-NEXT: lwsync
5447; PPC64LE-NEXT: blr
5448 %ret = atomicrmw umax i64* %ptr, i64 %val seq_cst
5449 ret i64 %ret
5450}
5451
5452define i8 @test320(i8* %ptr, i8 %val) {
5453; PPC64LE-LABEL: test320:
5454; PPC64LE: # BB#0:
5455; PPC64LE-NEXT: .LBB320_1:
5456; PPC64LE-NEXT: lbarx 5, 0, 3
5457; PPC64LE-NEXT: cmplw 4, 5
5458; PPC64LE-NEXT: bge 0, .LBB320_3
5459; PPC64LE-NEXT: # BB#2:
5460; PPC64LE-NEXT: stbcx. 4, 0, 3
5461; PPC64LE-NEXT: bne 0, .LBB320_1
5462; PPC64LE-NEXT: .LBB320_3:
5463; PPC64LE-NEXT: mr 3, 5
5464; PPC64LE-NEXT: blr
5465 %ret = atomicrmw umin i8* %ptr, i8 %val monotonic
5466 ret i8 %ret
5467}
5468
5469define i8 @test321(i8* %ptr, i8 %val) {
5470; PPC64LE-LABEL: test321:
5471; PPC64LE: # BB#0:
5472; PPC64LE-NEXT: mr 5, 3
5473; PPC64LE-NEXT: .LBB321_1:
5474; PPC64LE-NEXT: lbarx 3, 0, 5
5475; PPC64LE-NEXT: cmplw 4, 3
5476; PPC64LE-NEXT: bge 0, .LBB321_3
5477; PPC64LE-NEXT: # BB#2:
5478; PPC64LE-NEXT: stbcx. 4, 0, 5
5479; PPC64LE-NEXT: bne 0, .LBB321_1
5480; PPC64LE-NEXT: .LBB321_3:
5481; PPC64LE-NEXT: lwsync
5482; PPC64LE-NEXT: blr
5483 %ret = atomicrmw umin i8* %ptr, i8 %val acquire
5484 ret i8 %ret
5485}
5486
5487define i8 @test322(i8* %ptr, i8 %val) {
5488; PPC64LE-LABEL: test322:
5489; PPC64LE: # BB#0:
5490; PPC64LE-NEXT: lwsync
5491; PPC64LE-NEXT: .LBB322_1:
5492; PPC64LE-NEXT: lbarx 5, 0, 3
5493; PPC64LE-NEXT: cmplw 4, 5
5494; PPC64LE-NEXT: bge 0, .LBB322_3
5495; PPC64LE-NEXT: # BB#2:
5496; PPC64LE-NEXT: stbcx. 4, 0, 3
5497; PPC64LE-NEXT: bne 0, .LBB322_1
5498; PPC64LE-NEXT: .LBB322_3:
5499; PPC64LE-NEXT: mr 3, 5
5500; PPC64LE-NEXT: blr
5501 %ret = atomicrmw umin i8* %ptr, i8 %val release
5502 ret i8 %ret
5503}
5504
5505define i8 @test323(i8* %ptr, i8 %val) {
5506; PPC64LE-LABEL: test323:
5507; PPC64LE: # BB#0:
5508; PPC64LE-NEXT: lwsync
5509; PPC64LE-NEXT: .LBB323_1:
5510; PPC64LE-NEXT: lbarx 5, 0, 3
5511; PPC64LE-NEXT: cmplw 4, 5
5512; PPC64LE-NEXT: bge 0, .LBB323_3
5513; PPC64LE-NEXT: # BB#2:
5514; PPC64LE-NEXT: stbcx. 4, 0, 3
5515; PPC64LE-NEXT: bne 0, .LBB323_1
5516; PPC64LE-NEXT: .LBB323_3:
5517; PPC64LE-NEXT: mr 3, 5
5518; PPC64LE-NEXT: lwsync
5519; PPC64LE-NEXT: blr
5520 %ret = atomicrmw umin i8* %ptr, i8 %val acq_rel
5521 ret i8 %ret
5522}
5523
5524define i8 @test324(i8* %ptr, i8 %val) {
5525; PPC64LE-LABEL: test324:
5526; PPC64LE: # BB#0:
5527; PPC64LE-NEXT: sync
5528; PPC64LE-NEXT: .LBB324_1:
5529; PPC64LE-NEXT: lbarx 5, 0, 3
5530; PPC64LE-NEXT: cmplw 4, 5
5531; PPC64LE-NEXT: bge 0, .LBB324_3
5532; PPC64LE-NEXT: # BB#2:
5533; PPC64LE-NEXT: stbcx. 4, 0, 3
5534; PPC64LE-NEXT: bne 0, .LBB324_1
5535; PPC64LE-NEXT: .LBB324_3:
5536; PPC64LE-NEXT: mr 3, 5
5537; PPC64LE-NEXT: lwsync
5538; PPC64LE-NEXT: blr
5539 %ret = atomicrmw umin i8* %ptr, i8 %val seq_cst
5540 ret i8 %ret
5541}
5542
5543define i16 @test325(i16* %ptr, i16 %val) {
5544; PPC64LE-LABEL: test325:
5545; PPC64LE: # BB#0:
5546; PPC64LE-NEXT: .LBB325_1:
5547; PPC64LE-NEXT: lharx 5, 0, 3
5548; PPC64LE-NEXT: cmplw 4, 5
5549; PPC64LE-NEXT: bge 0, .LBB325_3
5550; PPC64LE-NEXT: # BB#2:
5551; PPC64LE-NEXT: sthcx. 4, 0, 3
5552; PPC64LE-NEXT: bne 0, .LBB325_1
5553; PPC64LE-NEXT: .LBB325_3:
5554; PPC64LE-NEXT: mr 3, 5
5555; PPC64LE-NEXT: blr
5556 %ret = atomicrmw umin i16* %ptr, i16 %val monotonic
5557 ret i16 %ret
5558}
5559
5560define i16 @test326(i16* %ptr, i16 %val) {
5561; PPC64LE-LABEL: test326:
5562; PPC64LE: # BB#0:
5563; PPC64LE-NEXT: mr 5, 3
5564; PPC64LE-NEXT: .LBB326_1:
5565; PPC64LE-NEXT: lharx 3, 0, 5
5566; PPC64LE-NEXT: cmplw 4, 3
5567; PPC64LE-NEXT: bge 0, .LBB326_3
5568; PPC64LE-NEXT: # BB#2:
5569; PPC64LE-NEXT: sthcx. 4, 0, 5
5570; PPC64LE-NEXT: bne 0, .LBB326_1
5571; PPC64LE-NEXT: .LBB326_3:
5572; PPC64LE-NEXT: lwsync
5573; PPC64LE-NEXT: blr
5574 %ret = atomicrmw umin i16* %ptr, i16 %val acquire
5575 ret i16 %ret
5576}
5577
5578define i16 @test327(i16* %ptr, i16 %val) {
5579; PPC64LE-LABEL: test327:
5580; PPC64LE: # BB#0:
5581; PPC64LE-NEXT: lwsync
5582; PPC64LE-NEXT: .LBB327_1:
5583; PPC64LE-NEXT: lharx 5, 0, 3
5584; PPC64LE-NEXT: cmplw 4, 5
5585; PPC64LE-NEXT: bge 0, .LBB327_3
5586; PPC64LE-NEXT: # BB#2:
5587; PPC64LE-NEXT: sthcx. 4, 0, 3
5588; PPC64LE-NEXT: bne 0, .LBB327_1
5589; PPC64LE-NEXT: .LBB327_3:
5590; PPC64LE-NEXT: mr 3, 5
5591; PPC64LE-NEXT: blr
5592 %ret = atomicrmw umin i16* %ptr, i16 %val release
5593 ret i16 %ret
5594}
5595
5596define i16 @test328(i16* %ptr, i16 %val) {
5597; PPC64LE-LABEL: test328:
5598; PPC64LE: # BB#0:
5599; PPC64LE-NEXT: lwsync
5600; PPC64LE-NEXT: .LBB328_1:
5601; PPC64LE-NEXT: lharx 5, 0, 3
5602; PPC64LE-NEXT: cmplw 4, 5
5603; PPC64LE-NEXT: bge 0, .LBB328_3
5604; PPC64LE-NEXT: # BB#2:
5605; PPC64LE-NEXT: sthcx. 4, 0, 3
5606; PPC64LE-NEXT: bne 0, .LBB328_1
5607; PPC64LE-NEXT: .LBB328_3:
5608; PPC64LE-NEXT: mr 3, 5
5609; PPC64LE-NEXT: lwsync
5610; PPC64LE-NEXT: blr
5611 %ret = atomicrmw umin i16* %ptr, i16 %val acq_rel
5612 ret i16 %ret
5613}
5614
5615define i16 @test329(i16* %ptr, i16 %val) {
5616; PPC64LE-LABEL: test329:
5617; PPC64LE: # BB#0:
5618; PPC64LE-NEXT: sync
5619; PPC64LE-NEXT: .LBB329_1:
5620; PPC64LE-NEXT: lharx 5, 0, 3
5621; PPC64LE-NEXT: cmplw 4, 5
5622; PPC64LE-NEXT: bge 0, .LBB329_3
5623; PPC64LE-NEXT: # BB#2:
5624; PPC64LE-NEXT: sthcx. 4, 0, 3
5625; PPC64LE-NEXT: bne 0, .LBB329_1
5626; PPC64LE-NEXT: .LBB329_3:
5627; PPC64LE-NEXT: mr 3, 5
5628; PPC64LE-NEXT: lwsync
5629; PPC64LE-NEXT: blr
5630 %ret = atomicrmw umin i16* %ptr, i16 %val seq_cst
5631 ret i16 %ret
5632}
5633
5634define i32 @test330(i32* %ptr, i32 %val) {
5635; PPC64LE-LABEL: test330:
5636; PPC64LE: # BB#0:
5637; PPC64LE-NEXT: .LBB330_1:
5638; PPC64LE-NEXT: lwarx 5, 0, 3
5639; PPC64LE-NEXT: cmplw 4, 5
5640; PPC64LE-NEXT: bge 0, .LBB330_3
5641; PPC64LE-NEXT: # BB#2:
5642; PPC64LE-NEXT: stwcx. 4, 0, 3
5643; PPC64LE-NEXT: bne 0, .LBB330_1
5644; PPC64LE-NEXT: .LBB330_3:
5645; PPC64LE-NEXT: mr 3, 5
5646; PPC64LE-NEXT: blr
5647 %ret = atomicrmw umin i32* %ptr, i32 %val monotonic
5648 ret i32 %ret
5649}
5650
5651define i32 @test331(i32* %ptr, i32 %val) {
5652; PPC64LE-LABEL: test331:
5653; PPC64LE: # BB#0:
5654; PPC64LE-NEXT: mr 5, 3
5655; PPC64LE-NEXT: .LBB331_1:
5656; PPC64LE-NEXT: lwarx 3, 0, 5
5657; PPC64LE-NEXT: cmplw 4, 3
5658; PPC64LE-NEXT: bge 0, .LBB331_3
5659; PPC64LE-NEXT: # BB#2:
5660; PPC64LE-NEXT: stwcx. 4, 0, 5
5661; PPC64LE-NEXT: bne 0, .LBB331_1
5662; PPC64LE-NEXT: .LBB331_3:
5663; PPC64LE-NEXT: lwsync
5664; PPC64LE-NEXT: blr
5665 %ret = atomicrmw umin i32* %ptr, i32 %val acquire
5666 ret i32 %ret
5667}
5668
5669define i32 @test332(i32* %ptr, i32 %val) {
5670; PPC64LE-LABEL: test332:
5671; PPC64LE: # BB#0:
5672; PPC64LE-NEXT: lwsync
5673; PPC64LE-NEXT: .LBB332_1:
5674; PPC64LE-NEXT: lwarx 5, 0, 3
5675; PPC64LE-NEXT: cmplw 4, 5
5676; PPC64LE-NEXT: bge 0, .LBB332_3
5677; PPC64LE-NEXT: # BB#2:
5678; PPC64LE-NEXT: stwcx. 4, 0, 3
5679; PPC64LE-NEXT: bne 0, .LBB332_1
5680; PPC64LE-NEXT: .LBB332_3:
5681; PPC64LE-NEXT: mr 3, 5
5682; PPC64LE-NEXT: blr
5683 %ret = atomicrmw umin i32* %ptr, i32 %val release
5684 ret i32 %ret
5685}
5686
5687define i32 @test333(i32* %ptr, i32 %val) {
5688; PPC64LE-LABEL: test333:
5689; PPC64LE: # BB#0:
5690; PPC64LE-NEXT: lwsync
5691; PPC64LE-NEXT: .LBB333_1:
5692; PPC64LE-NEXT: lwarx 5, 0, 3
5693; PPC64LE-NEXT: cmplw 4, 5
5694; PPC64LE-NEXT: bge 0, .LBB333_3
5695; PPC64LE-NEXT: # BB#2:
5696; PPC64LE-NEXT: stwcx. 4, 0, 3
5697; PPC64LE-NEXT: bne 0, .LBB333_1
5698; PPC64LE-NEXT: .LBB333_3:
5699; PPC64LE-NEXT: mr 3, 5
5700; PPC64LE-NEXT: lwsync
5701; PPC64LE-NEXT: blr
5702 %ret = atomicrmw umin i32* %ptr, i32 %val acq_rel
5703 ret i32 %ret
5704}
5705
5706define i32 @test334(i32* %ptr, i32 %val) {
5707; PPC64LE-LABEL: test334:
5708; PPC64LE: # BB#0:
5709; PPC64LE-NEXT: sync
5710; PPC64LE-NEXT: .LBB334_1:
5711; PPC64LE-NEXT: lwarx 5, 0, 3
5712; PPC64LE-NEXT: cmplw 4, 5
5713; PPC64LE-NEXT: bge 0, .LBB334_3
5714; PPC64LE-NEXT: # BB#2:
5715; PPC64LE-NEXT: stwcx. 4, 0, 3
5716; PPC64LE-NEXT: bne 0, .LBB334_1
5717; PPC64LE-NEXT: .LBB334_3:
5718; PPC64LE-NEXT: mr 3, 5
5719; PPC64LE-NEXT: lwsync
5720; PPC64LE-NEXT: blr
5721 %ret = atomicrmw umin i32* %ptr, i32 %val seq_cst
5722 ret i32 %ret
5723}
5724
5725define i64 @test335(i64* %ptr, i64 %val) {
5726; PPC64LE-LABEL: test335:
5727; PPC64LE: # BB#0:
5728; PPC64LE-NEXT: .LBB335_1:
5729; PPC64LE-NEXT: ldarx 5, 0, 3
5730; PPC64LE-NEXT: cmpld 4, 5
5731; PPC64LE-NEXT: bge 0, .LBB335_3
5732; PPC64LE-NEXT: # BB#2:
5733; PPC64LE-NEXT: stdcx. 4, 0, 3
5734; PPC64LE-NEXT: bne 0, .LBB335_1
5735; PPC64LE-NEXT: .LBB335_3:
5736; PPC64LE-NEXT: mr 3, 5
5737; PPC64LE-NEXT: blr
5738 %ret = atomicrmw umin i64* %ptr, i64 %val monotonic
5739 ret i64 %ret
5740}
5741
5742define i64 @test336(i64* %ptr, i64 %val) {
5743; PPC64LE-LABEL: test336:
5744; PPC64LE: # BB#0:
5745; PPC64LE-NEXT: mr 5, 3
5746; PPC64LE-NEXT: .LBB336_1:
5747; PPC64LE-NEXT: ldarx 3, 0, 5
5748; PPC64LE-NEXT: cmpld 4, 3
5749; PPC64LE-NEXT: bge 0, .LBB336_3
5750; PPC64LE-NEXT: # BB#2:
5751; PPC64LE-NEXT: stdcx. 4, 0, 5
5752; PPC64LE-NEXT: bne 0, .LBB336_1
5753; PPC64LE-NEXT: .LBB336_3:
5754; PPC64LE-NEXT: lwsync
5755; PPC64LE-NEXT: blr
5756 %ret = atomicrmw umin i64* %ptr, i64 %val acquire
5757 ret i64 %ret
5758}
5759
5760define i64 @test337(i64* %ptr, i64 %val) {
5761; PPC64LE-LABEL: test337:
5762; PPC64LE: # BB#0:
5763; PPC64LE-NEXT: lwsync
5764; PPC64LE-NEXT: .LBB337_1:
5765; PPC64LE-NEXT: ldarx 5, 0, 3
5766; PPC64LE-NEXT: cmpld 4, 5
5767; PPC64LE-NEXT: bge 0, .LBB337_3
5768; PPC64LE-NEXT: # BB#2:
5769; PPC64LE-NEXT: stdcx. 4, 0, 3
5770; PPC64LE-NEXT: bne 0, .LBB337_1
5771; PPC64LE-NEXT: .LBB337_3:
5772; PPC64LE-NEXT: mr 3, 5
5773; PPC64LE-NEXT: blr
5774 %ret = atomicrmw umin i64* %ptr, i64 %val release
5775 ret i64 %ret
5776}
5777
5778define i64 @test338(i64* %ptr, i64 %val) {
5779; PPC64LE-LABEL: test338:
5780; PPC64LE: # BB#0:
5781; PPC64LE-NEXT: lwsync
5782; PPC64LE-NEXT: .LBB338_1:
5783; PPC64LE-NEXT: ldarx 5, 0, 3
5784; PPC64LE-NEXT: cmpld 4, 5
5785; PPC64LE-NEXT: bge 0, .LBB338_3
5786; PPC64LE-NEXT: # BB#2:
5787; PPC64LE-NEXT: stdcx. 4, 0, 3
5788; PPC64LE-NEXT: bne 0, .LBB338_1
5789; PPC64LE-NEXT: .LBB338_3:
5790; PPC64LE-NEXT: mr 3, 5
5791; PPC64LE-NEXT: lwsync
5792; PPC64LE-NEXT: blr
5793 %ret = atomicrmw umin i64* %ptr, i64 %val acq_rel
5794 ret i64 %ret
5795}
5796
5797define i64 @test339(i64* %ptr, i64 %val) {
5798; PPC64LE-LABEL: test339:
5799; PPC64LE: # BB#0:
5800; PPC64LE-NEXT: sync
5801; PPC64LE-NEXT: .LBB339_1:
5802; PPC64LE-NEXT: ldarx 5, 0, 3
5803; PPC64LE-NEXT: cmpld 4, 5
5804; PPC64LE-NEXT: bge 0, .LBB339_3
5805; PPC64LE-NEXT: # BB#2:
5806; PPC64LE-NEXT: stdcx. 4, 0, 3
5807; PPC64LE-NEXT: bne 0, .LBB339_1
5808; PPC64LE-NEXT: .LBB339_3:
5809; PPC64LE-NEXT: mr 3, 5
5810; PPC64LE-NEXT: lwsync
5811; PPC64LE-NEXT: blr
5812 %ret = atomicrmw umin i64* %ptr, i64 %val seq_cst
5813 ret i64 %ret
5814}
5815
5816define i8 @test340(i8* %ptr, i8 %val) {
5817; PPC64LE-LABEL: test340:
5818; PPC64LE: # BB#0:
5819; PPC64LE-NEXT: .LBB340_1:
5820; PPC64LE-NEXT: lbarx 5, 0, 3
5821; PPC64LE-NEXT: stbcx. 4, 0, 3
5822; PPC64LE-NEXT: bne 0, .LBB340_1
5823; PPC64LE-NEXT: # BB#2:
5824; PPC64LE-NEXT: mr 3, 5
5825; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5826 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5827 ret i8 %ret
5828}
5829
5830define i8 @test341(i8* %ptr, i8 %val) {
5831; PPC64LE-LABEL: test341:
5832; PPC64LE: # BB#0:
5833; PPC64LE-NEXT: mr 5, 3
5834; PPC64LE-NEXT: .LBB341_1:
5835; PPC64LE-NEXT: lbarx 3, 0, 5
5836; PPC64LE-NEXT: stbcx. 4, 0, 5
5837; PPC64LE-NEXT: bne 0, .LBB341_1
5838; PPC64LE-NEXT: # BB#2:
5839; PPC64LE-NEXT: lwsync
5840; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5841 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5842 ret i8 %ret
5843}
5844
5845define i8 @test342(i8* %ptr, i8 %val) {
5846; PPC64LE-LABEL: test342:
5847; PPC64LE: # BB#0:
5848; PPC64LE-NEXT: lwsync
5849; PPC64LE-NEXT: .LBB342_1:
5850; PPC64LE-NEXT: lbarx 5, 0, 3
5851; PPC64LE-NEXT: stbcx. 4, 0, 3
5852; PPC64LE-NEXT: bne 0, .LBB342_1
5853; PPC64LE-NEXT: # BB#2:
5854; PPC64LE-NEXT: mr 3, 5
5855; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5856 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5857 ret i8 %ret
5858}
5859
5860define i8 @test343(i8* %ptr, i8 %val) {
5861; PPC64LE-LABEL: test343:
5862; PPC64LE: # BB#0:
5863; PPC64LE-NEXT: lwsync
5864; PPC64LE-NEXT: .LBB343_1:
5865; PPC64LE-NEXT: lbarx 5, 0, 3
5866; PPC64LE-NEXT: stbcx. 4, 0, 3
5867; PPC64LE-NEXT: bne 0, .LBB343_1
5868; PPC64LE-NEXT: # BB#2:
5869; PPC64LE-NEXT: mr 3, 5
5870; PPC64LE-NEXT: lwsync
5871; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5872 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5873 ret i8 %ret
5874}
5875
5876define i8 @test344(i8* %ptr, i8 %val) {
5877; PPC64LE-LABEL: test344:
5878; PPC64LE: # BB#0:
5879; PPC64LE-NEXT: sync
5880; PPC64LE-NEXT: .LBB344_1:
5881; PPC64LE-NEXT: lbarx 5, 0, 3
5882; PPC64LE-NEXT: stbcx. 4, 0, 3
5883; PPC64LE-NEXT: bne 0, .LBB344_1
5884; PPC64LE-NEXT: # BB#2:
5885; PPC64LE-NEXT: mr 3, 5
5886; PPC64LE-NEXT: lwsync
5887; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5888 %ret = atomicrmw xchg i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5889 ret i8 %ret
5890}
5891
5892define i16 @test345(i16* %ptr, i16 %val) {
5893; PPC64LE-LABEL: test345:
5894; PPC64LE: # BB#0:
5895; PPC64LE-NEXT: .LBB345_1:
5896; PPC64LE-NEXT: lharx 5, 0, 3
5897; PPC64LE-NEXT: sthcx. 4, 0, 3
5898; PPC64LE-NEXT: bne 0, .LBB345_1
5899; PPC64LE-NEXT: # BB#2:
5900; PPC64LE-NEXT: mr 3, 5
5901; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5902 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5903 ret i16 %ret
5904}
5905
5906define i16 @test346(i16* %ptr, i16 %val) {
5907; PPC64LE-LABEL: test346:
5908; PPC64LE: # BB#0:
5909; PPC64LE-NEXT: mr 5, 3
5910; PPC64LE-NEXT: .LBB346_1:
5911; PPC64LE-NEXT: lharx 3, 0, 5
5912; PPC64LE-NEXT: sthcx. 4, 0, 5
5913; PPC64LE-NEXT: bne 0, .LBB346_1
5914; PPC64LE-NEXT: # BB#2:
5915; PPC64LE-NEXT: lwsync
5916; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5917 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5918 ret i16 %ret
5919}
5920
5921define i16 @test347(i16* %ptr, i16 %val) {
5922; PPC64LE-LABEL: test347:
5923; PPC64LE: # BB#0:
5924; PPC64LE-NEXT: lwsync
5925; PPC64LE-NEXT: .LBB347_1:
5926; PPC64LE-NEXT: lharx 5, 0, 3
5927; PPC64LE-NEXT: sthcx. 4, 0, 3
5928; PPC64LE-NEXT: bne 0, .LBB347_1
5929; PPC64LE-NEXT: # BB#2:
5930; PPC64LE-NEXT: mr 3, 5
5931; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5932 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5933 ret i16 %ret
5934}
5935
5936define i16 @test348(i16* %ptr, i16 %val) {
5937; PPC64LE-LABEL: test348:
5938; PPC64LE: # BB#0:
5939; PPC64LE-NEXT: lwsync
5940; PPC64LE-NEXT: .LBB348_1:
5941; PPC64LE-NEXT: lharx 5, 0, 3
5942; PPC64LE-NEXT: sthcx. 4, 0, 3
5943; PPC64LE-NEXT: bne 0, .LBB348_1
5944; PPC64LE-NEXT: # BB#2:
5945; PPC64LE-NEXT: mr 3, 5
5946; PPC64LE-NEXT: lwsync
5947; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5948 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5949 ret i16 %ret
5950}
5951
5952define i16 @test349(i16* %ptr, i16 %val) {
5953; PPC64LE-LABEL: test349:
5954; PPC64LE: # BB#0:
5955; PPC64LE-NEXT: sync
5956; PPC64LE-NEXT: .LBB349_1:
5957; PPC64LE-NEXT: lharx 5, 0, 3
5958; PPC64LE-NEXT: sthcx. 4, 0, 3
5959; PPC64LE-NEXT: bne 0, .LBB349_1
5960; PPC64LE-NEXT: # BB#2:
5961; PPC64LE-NEXT: mr 3, 5
5962; PPC64LE-NEXT: lwsync
5963; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5964 %ret = atomicrmw xchg i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5965 ret i16 %ret
5966}
5967
5968define i32 @test350(i32* %ptr, i32 %val) {
5969; PPC64LE-LABEL: test350:
5970; PPC64LE: # BB#0:
5971; PPC64LE-NEXT: .LBB350_1:
5972; PPC64LE-NEXT: lwarx 5, 0, 3
5973; PPC64LE-NEXT: stwcx. 4, 0, 3
5974; PPC64LE-NEXT: bne 0, .LBB350_1
5975; PPC64LE-NEXT: # BB#2:
5976; PPC64LE-NEXT: mr 3, 5
5977; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5978 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5979 ret i32 %ret
5980}
5981
5982define i32 @test351(i32* %ptr, i32 %val) {
5983; PPC64LE-LABEL: test351:
5984; PPC64LE: # BB#0:
5985; PPC64LE-NEXT: mr 5, 3
5986; PPC64LE-NEXT: .LBB351_1:
5987; PPC64LE-NEXT: lwarx 3, 0, 5
5988; PPC64LE-NEXT: stwcx. 4, 0, 5
5989; PPC64LE-NEXT: bne 0, .LBB351_1
5990; PPC64LE-NEXT: # BB#2:
5991; PPC64LE-NEXT: lwsync
5992; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]5993 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]5994 ret i32 %ret
5995}
5996
5997define i32 @test352(i32* %ptr, i32 %val) {
5998; PPC64LE-LABEL: test352:
5999; PPC64LE: # BB#0:
6000; PPC64LE-NEXT: lwsync
6001; PPC64LE-NEXT: .LBB352_1:
6002; PPC64LE-NEXT: lwarx 5, 0, 3
6003; PPC64LE-NEXT: stwcx. 4, 0, 3
6004; PPC64LE-NEXT: bne 0, .LBB352_1
6005; PPC64LE-NEXT: # BB#2:
6006; PPC64LE-NEXT: mr 3, 5
6007; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6008 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6009 ret i32 %ret
6010}
6011
6012define i32 @test353(i32* %ptr, i32 %val) {
6013; PPC64LE-LABEL: test353:
6014; PPC64LE: # BB#0:
6015; PPC64LE-NEXT: lwsync
6016; PPC64LE-NEXT: .LBB353_1:
6017; PPC64LE-NEXT: lwarx 5, 0, 3
6018; PPC64LE-NEXT: stwcx. 4, 0, 3
6019; PPC64LE-NEXT: bne 0, .LBB353_1
6020; PPC64LE-NEXT: # BB#2:
6021; PPC64LE-NEXT: mr 3, 5
6022; PPC64LE-NEXT: lwsync
6023; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6024 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6025 ret i32 %ret
6026}
6027
6028define i32 @test354(i32* %ptr, i32 %val) {
6029; PPC64LE-LABEL: test354:
6030; PPC64LE: # BB#0:
6031; PPC64LE-NEXT: sync
6032; PPC64LE-NEXT: .LBB354_1:
6033; PPC64LE-NEXT: lwarx 5, 0, 3
6034; PPC64LE-NEXT: stwcx. 4, 0, 3
6035; PPC64LE-NEXT: bne 0, .LBB354_1
6036; PPC64LE-NEXT: # BB#2:
6037; PPC64LE-NEXT: mr 3, 5
6038; PPC64LE-NEXT: lwsync
6039; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6040 %ret = atomicrmw xchg i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6041 ret i32 %ret
6042}
6043
6044define i64 @test355(i64* %ptr, i64 %val) {
6045; PPC64LE-LABEL: test355:
6046; PPC64LE: # BB#0:
6047; PPC64LE-NEXT: .LBB355_1:
6048; PPC64LE-NEXT: ldarx 5, 0, 3
6049; PPC64LE-NEXT: stdcx. 4, 0, 3
6050; PPC64LE-NEXT: bne 0, .LBB355_1
6051; PPC64LE-NEXT: # BB#2:
6052; PPC64LE-NEXT: mr 3, 5
6053; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6054 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6055 ret i64 %ret
6056}
6057
6058define i64 @test356(i64* %ptr, i64 %val) {
6059; PPC64LE-LABEL: test356:
6060; PPC64LE: # BB#0:
6061; PPC64LE-NEXT: mr 5, 3
6062; PPC64LE-NEXT: .LBB356_1:
6063; PPC64LE-NEXT: ldarx 3, 0, 5
6064; PPC64LE-NEXT: stdcx. 4, 0, 5
6065; PPC64LE-NEXT: bne 0, .LBB356_1
6066; PPC64LE-NEXT: # BB#2:
6067; PPC64LE-NEXT: lwsync
6068; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6069 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6070 ret i64 %ret
6071}
6072
6073define i64 @test357(i64* %ptr, i64 %val) {
6074; PPC64LE-LABEL: test357:
6075; PPC64LE: # BB#0:
6076; PPC64LE-NEXT: lwsync
6077; PPC64LE-NEXT: .LBB357_1:
6078; PPC64LE-NEXT: ldarx 5, 0, 3
6079; PPC64LE-NEXT: stdcx. 4, 0, 3
6080; PPC64LE-NEXT: bne 0, .LBB357_1
6081; PPC64LE-NEXT: # BB#2:
6082; PPC64LE-NEXT: mr 3, 5
6083; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6084 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6085 ret i64 %ret
6086}
6087
6088define i64 @test358(i64* %ptr, i64 %val) {
6089; PPC64LE-LABEL: test358:
6090; PPC64LE: # BB#0:
6091; PPC64LE-NEXT: lwsync
6092; PPC64LE-NEXT: .LBB358_1:
6093; PPC64LE-NEXT: ldarx 5, 0, 3
6094; PPC64LE-NEXT: stdcx. 4, 0, 3
6095; PPC64LE-NEXT: bne 0, .LBB358_1
6096; PPC64LE-NEXT: # BB#2:
6097; PPC64LE-NEXT: mr 3, 5
6098; PPC64LE-NEXT: lwsync
6099; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6100 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6101 ret i64 %ret
6102}
6103
6104define i64 @test359(i64* %ptr, i64 %val) {
6105; PPC64LE-LABEL: test359:
6106; PPC64LE: # BB#0:
6107; PPC64LE-NEXT: sync
6108; PPC64LE-NEXT: .LBB359_1:
6109; PPC64LE-NEXT: ldarx 5, 0, 3
6110; PPC64LE-NEXT: stdcx. 4, 0, 3
6111; PPC64LE-NEXT: bne 0, .LBB359_1
6112; PPC64LE-NEXT: # BB#2:
6113; PPC64LE-NEXT: mr 3, 5
6114; PPC64LE-NEXT: lwsync
6115; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6116 %ret = atomicrmw xchg i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6117 ret i64 %ret
6118}
6119
6120define i8 @test360(i8* %ptr, i8 %val) {
6121; PPC64LE-LABEL: test360:
6122; PPC64LE: # BB#0:
6123; PPC64LE-NEXT: .LBB360_1:
6124; PPC64LE-NEXT: lbarx 5, 0, 3
6125; PPC64LE-NEXT: add 6, 4, 5
6126; PPC64LE-NEXT: stbcx. 6, 0, 3
6127; PPC64LE-NEXT: bne 0, .LBB360_1
6128; PPC64LE-NEXT: # BB#2:
6129; PPC64LE-NEXT: mr 3, 5
6130; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6131 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6132 ret i8 %ret
6133}
6134
6135define i8 @test361(i8* %ptr, i8 %val) {
6136; PPC64LE-LABEL: test361:
6137; PPC64LE: # BB#0:
6138; PPC64LE-NEXT: mr 5, 3
6139; PPC64LE-NEXT: .LBB361_1:
6140; PPC64LE-NEXT: lbarx 3, 0, 5
6141; PPC64LE-NEXT: add 6, 4, 3
6142; PPC64LE-NEXT: stbcx. 6, 0, 5
6143; PPC64LE-NEXT: bne 0, .LBB361_1
6144; PPC64LE-NEXT: # BB#2:
6145; PPC64LE-NEXT: lwsync
6146; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6147 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6148 ret i8 %ret
6149}
6150
6151define i8 @test362(i8* %ptr, i8 %val) {
6152; PPC64LE-LABEL: test362:
6153; PPC64LE: # BB#0:
6154; PPC64LE-NEXT: lwsync
6155; PPC64LE-NEXT: .LBB362_1:
6156; PPC64LE-NEXT: lbarx 5, 0, 3
6157; PPC64LE-NEXT: add 6, 4, 5
6158; PPC64LE-NEXT: stbcx. 6, 0, 3
6159; PPC64LE-NEXT: bne 0, .LBB362_1
6160; PPC64LE-NEXT: # BB#2:
6161; PPC64LE-NEXT: mr 3, 5
6162; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6163 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6164 ret i8 %ret
6165}
6166
6167define i8 @test363(i8* %ptr, i8 %val) {
6168; PPC64LE-LABEL: test363:
6169; PPC64LE: # BB#0:
6170; PPC64LE-NEXT: lwsync
6171; PPC64LE-NEXT: .LBB363_1:
6172; PPC64LE-NEXT: lbarx 5, 0, 3
6173; PPC64LE-NEXT: add 6, 4, 5
6174; PPC64LE-NEXT: stbcx. 6, 0, 3
6175; PPC64LE-NEXT: bne 0, .LBB363_1
6176; PPC64LE-NEXT: # BB#2:
6177; PPC64LE-NEXT: mr 3, 5
6178; PPC64LE-NEXT: lwsync
6179; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6180 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6181 ret i8 %ret
6182}
6183
6184define i8 @test364(i8* %ptr, i8 %val) {
6185; PPC64LE-LABEL: test364:
6186; PPC64LE: # BB#0:
6187; PPC64LE-NEXT: sync
6188; PPC64LE-NEXT: .LBB364_1:
6189; PPC64LE-NEXT: lbarx 5, 0, 3
6190; PPC64LE-NEXT: add 6, 4, 5
6191; PPC64LE-NEXT: stbcx. 6, 0, 3
6192; PPC64LE-NEXT: bne 0, .LBB364_1
6193; PPC64LE-NEXT: # BB#2:
6194; PPC64LE-NEXT: mr 3, 5
6195; PPC64LE-NEXT: lwsync
6196; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6197 %ret = atomicrmw add i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6198 ret i8 %ret
6199}
6200
6201define i16 @test365(i16* %ptr, i16 %val) {
6202; PPC64LE-LABEL: test365:
6203; PPC64LE: # BB#0:
6204; PPC64LE-NEXT: .LBB365_1:
6205; PPC64LE-NEXT: lharx 5, 0, 3
6206; PPC64LE-NEXT: add 6, 4, 5
6207; PPC64LE-NEXT: sthcx. 6, 0, 3
6208; PPC64LE-NEXT: bne 0, .LBB365_1
6209; PPC64LE-NEXT: # BB#2:
6210; PPC64LE-NEXT: mr 3, 5
6211; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6212 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6213 ret i16 %ret
6214}
6215
6216define i16 @test366(i16* %ptr, i16 %val) {
6217; PPC64LE-LABEL: test366:
6218; PPC64LE: # BB#0:
6219; PPC64LE-NEXT: mr 5, 3
6220; PPC64LE-NEXT: .LBB366_1:
6221; PPC64LE-NEXT: lharx 3, 0, 5
6222; PPC64LE-NEXT: add 6, 4, 3
6223; PPC64LE-NEXT: sthcx. 6, 0, 5
6224; PPC64LE-NEXT: bne 0, .LBB366_1
6225; PPC64LE-NEXT: # BB#2:
6226; PPC64LE-NEXT: lwsync
6227; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6228 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6229 ret i16 %ret
6230}
6231
6232define i16 @test367(i16* %ptr, i16 %val) {
6233; PPC64LE-LABEL: test367:
6234; PPC64LE: # BB#0:
6235; PPC64LE-NEXT: lwsync
6236; PPC64LE-NEXT: .LBB367_1:
6237; PPC64LE-NEXT: lharx 5, 0, 3
6238; PPC64LE-NEXT: add 6, 4, 5
6239; PPC64LE-NEXT: sthcx. 6, 0, 3
6240; PPC64LE-NEXT: bne 0, .LBB367_1
6241; PPC64LE-NEXT: # BB#2:
6242; PPC64LE-NEXT: mr 3, 5
6243; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6244 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6245 ret i16 %ret
6246}
6247
6248define i16 @test368(i16* %ptr, i16 %val) {
6249; PPC64LE-LABEL: test368:
6250; PPC64LE: # BB#0:
6251; PPC64LE-NEXT: lwsync
6252; PPC64LE-NEXT: .LBB368_1:
6253; PPC64LE-NEXT: lharx 5, 0, 3
6254; PPC64LE-NEXT: add 6, 4, 5
6255; PPC64LE-NEXT: sthcx. 6, 0, 3
6256; PPC64LE-NEXT: bne 0, .LBB368_1
6257; PPC64LE-NEXT: # BB#2:
6258; PPC64LE-NEXT: mr 3, 5
6259; PPC64LE-NEXT: lwsync
6260; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6261 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6262 ret i16 %ret
6263}
6264
6265define i16 @test369(i16* %ptr, i16 %val) {
6266; PPC64LE-LABEL: test369:
6267; PPC64LE: # BB#0:
6268; PPC64LE-NEXT: sync
6269; PPC64LE-NEXT: .LBB369_1:
6270; PPC64LE-NEXT: lharx 5, 0, 3
6271; PPC64LE-NEXT: add 6, 4, 5
6272; PPC64LE-NEXT: sthcx. 6, 0, 3
6273; PPC64LE-NEXT: bne 0, .LBB369_1
6274; PPC64LE-NEXT: # BB#2:
6275; PPC64LE-NEXT: mr 3, 5
6276; PPC64LE-NEXT: lwsync
6277; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6278 %ret = atomicrmw add i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6279 ret i16 %ret
6280}
6281
6282define i32 @test370(i32* %ptr, i32 %val) {
6283; PPC64LE-LABEL: test370:
6284; PPC64LE: # BB#0:
6285; PPC64LE-NEXT: .LBB370_1:
6286; PPC64LE-NEXT: lwarx 5, 0, 3
6287; PPC64LE-NEXT: add 6, 4, 5
6288; PPC64LE-NEXT: stwcx. 6, 0, 3
6289; PPC64LE-NEXT: bne 0, .LBB370_1
6290; PPC64LE-NEXT: # BB#2:
6291; PPC64LE-NEXT: mr 3, 5
6292; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6293 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6294 ret i32 %ret
6295}
6296
6297define i32 @test371(i32* %ptr, i32 %val) {
6298; PPC64LE-LABEL: test371:
6299; PPC64LE: # BB#0:
6300; PPC64LE-NEXT: mr 5, 3
6301; PPC64LE-NEXT: .LBB371_1:
6302; PPC64LE-NEXT: lwarx 3, 0, 5
6303; PPC64LE-NEXT: add 6, 4, 3
6304; PPC64LE-NEXT: stwcx. 6, 0, 5
6305; PPC64LE-NEXT: bne 0, .LBB371_1
6306; PPC64LE-NEXT: # BB#2:
6307; PPC64LE-NEXT: lwsync
6308; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6309 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6310 ret i32 %ret
6311}
6312
6313define i32 @test372(i32* %ptr, i32 %val) {
6314; PPC64LE-LABEL: test372:
6315; PPC64LE: # BB#0:
6316; PPC64LE-NEXT: lwsync
6317; PPC64LE-NEXT: .LBB372_1:
6318; PPC64LE-NEXT: lwarx 5, 0, 3
6319; PPC64LE-NEXT: add 6, 4, 5
6320; PPC64LE-NEXT: stwcx. 6, 0, 3
6321; PPC64LE-NEXT: bne 0, .LBB372_1
6322; PPC64LE-NEXT: # BB#2:
6323; PPC64LE-NEXT: mr 3, 5
6324; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6325 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6326 ret i32 %ret
6327}
6328
6329define i32 @test373(i32* %ptr, i32 %val) {
6330; PPC64LE-LABEL: test373:
6331; PPC64LE: # BB#0:
6332; PPC64LE-NEXT: lwsync
6333; PPC64LE-NEXT: .LBB373_1:
6334; PPC64LE-NEXT: lwarx 5, 0, 3
6335; PPC64LE-NEXT: add 6, 4, 5
6336; PPC64LE-NEXT: stwcx. 6, 0, 3
6337; PPC64LE-NEXT: bne 0, .LBB373_1
6338; PPC64LE-NEXT: # BB#2:
6339; PPC64LE-NEXT: mr 3, 5
6340; PPC64LE-NEXT: lwsync
6341; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6342 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6343 ret i32 %ret
6344}
6345
6346define i32 @test374(i32* %ptr, i32 %val) {
6347; PPC64LE-LABEL: test374:
6348; PPC64LE: # BB#0:
6349; PPC64LE-NEXT: sync
6350; PPC64LE-NEXT: .LBB374_1:
6351; PPC64LE-NEXT: lwarx 5, 0, 3
6352; PPC64LE-NEXT: add 6, 4, 5
6353; PPC64LE-NEXT: stwcx. 6, 0, 3
6354; PPC64LE-NEXT: bne 0, .LBB374_1
6355; PPC64LE-NEXT: # BB#2:
6356; PPC64LE-NEXT: mr 3, 5
6357; PPC64LE-NEXT: lwsync
6358; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6359 %ret = atomicrmw add i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6360 ret i32 %ret
6361}
6362
6363define i64 @test375(i64* %ptr, i64 %val) {
6364; PPC64LE-LABEL: test375:
6365; PPC64LE: # BB#0:
6366; PPC64LE-NEXT: .LBB375_1:
6367; PPC64LE-NEXT: ldarx 5, 0, 3
6368; PPC64LE-NEXT: add 6, 4, 5
6369; PPC64LE-NEXT: stdcx. 6, 0, 3
6370; PPC64LE-NEXT: bne 0, .LBB375_1
6371; PPC64LE-NEXT: # BB#2:
6372; PPC64LE-NEXT: mr 3, 5
6373; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6374 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6375 ret i64 %ret
6376}
6377
6378define i64 @test376(i64* %ptr, i64 %val) {
6379; PPC64LE-LABEL: test376:
6380; PPC64LE: # BB#0:
6381; PPC64LE-NEXT: mr 5, 3
6382; PPC64LE-NEXT: .LBB376_1:
6383; PPC64LE-NEXT: ldarx 3, 0, 5
6384; PPC64LE-NEXT: add 6, 4, 3
6385; PPC64LE-NEXT: stdcx. 6, 0, 5
6386; PPC64LE-NEXT: bne 0, .LBB376_1
6387; PPC64LE-NEXT: # BB#2:
6388; PPC64LE-NEXT: lwsync
6389; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6390 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6391 ret i64 %ret
6392}
6393
6394define i64 @test377(i64* %ptr, i64 %val) {
6395; PPC64LE-LABEL: test377:
6396; PPC64LE: # BB#0:
6397; PPC64LE-NEXT: lwsync
6398; PPC64LE-NEXT: .LBB377_1:
6399; PPC64LE-NEXT: ldarx 5, 0, 3
6400; PPC64LE-NEXT: add 6, 4, 5
6401; PPC64LE-NEXT: stdcx. 6, 0, 3
6402; PPC64LE-NEXT: bne 0, .LBB377_1
6403; PPC64LE-NEXT: # BB#2:
6404; PPC64LE-NEXT: mr 3, 5
6405; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6406 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6407 ret i64 %ret
6408}
6409
6410define i64 @test378(i64* %ptr, i64 %val) {
6411; PPC64LE-LABEL: test378:
6412; PPC64LE: # BB#0:
6413; PPC64LE-NEXT: lwsync
6414; PPC64LE-NEXT: .LBB378_1:
6415; PPC64LE-NEXT: ldarx 5, 0, 3
6416; PPC64LE-NEXT: add 6, 4, 5
6417; PPC64LE-NEXT: stdcx. 6, 0, 3
6418; PPC64LE-NEXT: bne 0, .LBB378_1
6419; PPC64LE-NEXT: # BB#2:
6420; PPC64LE-NEXT: mr 3, 5
6421; PPC64LE-NEXT: lwsync
6422; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6423 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6424 ret i64 %ret
6425}
6426
6427define i64 @test379(i64* %ptr, i64 %val) {
6428; PPC64LE-LABEL: test379:
6429; PPC64LE: # BB#0:
6430; PPC64LE-NEXT: sync
6431; PPC64LE-NEXT: .LBB379_1:
6432; PPC64LE-NEXT: ldarx 5, 0, 3
6433; PPC64LE-NEXT: add 6, 4, 5
6434; PPC64LE-NEXT: stdcx. 6, 0, 3
6435; PPC64LE-NEXT: bne 0, .LBB379_1
6436; PPC64LE-NEXT: # BB#2:
6437; PPC64LE-NEXT: mr 3, 5
6438; PPC64LE-NEXT: lwsync
6439; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6440 %ret = atomicrmw add i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6441 ret i64 %ret
6442}
6443
6444define i8 @test380(i8* %ptr, i8 %val) {
6445; PPC64LE-LABEL: test380:
6446; PPC64LE: # BB#0:
6447; PPC64LE-NEXT: .LBB380_1:
6448; PPC64LE-NEXT: lbarx 5, 0, 3
6449; PPC64LE-NEXT: subf 6, 4, 5
6450; PPC64LE-NEXT: stbcx. 6, 0, 3
6451; PPC64LE-NEXT: bne 0, .LBB380_1
6452; PPC64LE-NEXT: # BB#2:
6453; PPC64LE-NEXT: mr 3, 5
6454; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6455 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6456 ret i8 %ret
6457}
6458
6459define i8 @test381(i8* %ptr, i8 %val) {
6460; PPC64LE-LABEL: test381:
6461; PPC64LE: # BB#0:
6462; PPC64LE-NEXT: mr 5, 3
6463; PPC64LE-NEXT: .LBB381_1:
6464; PPC64LE-NEXT: lbarx 3, 0, 5
6465; PPC64LE-NEXT: subf 6, 4, 3
6466; PPC64LE-NEXT: stbcx. 6, 0, 5
6467; PPC64LE-NEXT: bne 0, .LBB381_1
6468; PPC64LE-NEXT: # BB#2:
6469; PPC64LE-NEXT: lwsync
6470; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6471 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6472 ret i8 %ret
6473}
6474
6475define i8 @test382(i8* %ptr, i8 %val) {
6476; PPC64LE-LABEL: test382:
6477; PPC64LE: # BB#0:
6478; PPC64LE-NEXT: lwsync
6479; PPC64LE-NEXT: .LBB382_1:
6480; PPC64LE-NEXT: lbarx 5, 0, 3
6481; PPC64LE-NEXT: subf 6, 4, 5
6482; PPC64LE-NEXT: stbcx. 6, 0, 3
6483; PPC64LE-NEXT: bne 0, .LBB382_1
6484; PPC64LE-NEXT: # BB#2:
6485; PPC64LE-NEXT: mr 3, 5
6486; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6487 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6488 ret i8 %ret
6489}
6490
6491define i8 @test383(i8* %ptr, i8 %val) {
6492; PPC64LE-LABEL: test383:
6493; PPC64LE: # BB#0:
6494; PPC64LE-NEXT: lwsync
6495; PPC64LE-NEXT: .LBB383_1:
6496; PPC64LE-NEXT: lbarx 5, 0, 3
6497; PPC64LE-NEXT: subf 6, 4, 5
6498; PPC64LE-NEXT: stbcx. 6, 0, 3
6499; PPC64LE-NEXT: bne 0, .LBB383_1
6500; PPC64LE-NEXT: # BB#2:
6501; PPC64LE-NEXT: mr 3, 5
6502; PPC64LE-NEXT: lwsync
6503; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6504 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6505 ret i8 %ret
6506}
6507
6508define i8 @test384(i8* %ptr, i8 %val) {
6509; PPC64LE-LABEL: test384:
6510; PPC64LE: # BB#0:
6511; PPC64LE-NEXT: sync
6512; PPC64LE-NEXT: .LBB384_1:
6513; PPC64LE-NEXT: lbarx 5, 0, 3
6514; PPC64LE-NEXT: subf 6, 4, 5
6515; PPC64LE-NEXT: stbcx. 6, 0, 3
6516; PPC64LE-NEXT: bne 0, .LBB384_1
6517; PPC64LE-NEXT: # BB#2:
6518; PPC64LE-NEXT: mr 3, 5
6519; PPC64LE-NEXT: lwsync
6520; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6521 %ret = atomicrmw sub i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6522 ret i8 %ret
6523}
6524
6525define i16 @test385(i16* %ptr, i16 %val) {
6526; PPC64LE-LABEL: test385:
6527; PPC64LE: # BB#0:
6528; PPC64LE-NEXT: .LBB385_1:
6529; PPC64LE-NEXT: lharx 5, 0, 3
6530; PPC64LE-NEXT: subf 6, 4, 5
6531; PPC64LE-NEXT: sthcx. 6, 0, 3
6532; PPC64LE-NEXT: bne 0, .LBB385_1
6533; PPC64LE-NEXT: # BB#2:
6534; PPC64LE-NEXT: mr 3, 5
6535; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6536 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6537 ret i16 %ret
6538}
6539
6540define i16 @test386(i16* %ptr, i16 %val) {
6541; PPC64LE-LABEL: test386:
6542; PPC64LE: # BB#0:
6543; PPC64LE-NEXT: mr 5, 3
6544; PPC64LE-NEXT: .LBB386_1:
6545; PPC64LE-NEXT: lharx 3, 0, 5
6546; PPC64LE-NEXT: subf 6, 4, 3
6547; PPC64LE-NEXT: sthcx. 6, 0, 5
6548; PPC64LE-NEXT: bne 0, .LBB386_1
6549; PPC64LE-NEXT: # BB#2:
6550; PPC64LE-NEXT: lwsync
6551; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6552 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6553 ret i16 %ret
6554}
6555
6556define i16 @test387(i16* %ptr, i16 %val) {
6557; PPC64LE-LABEL: test387:
6558; PPC64LE: # BB#0:
6559; PPC64LE-NEXT: lwsync
6560; PPC64LE-NEXT: .LBB387_1:
6561; PPC64LE-NEXT: lharx 5, 0, 3
6562; PPC64LE-NEXT: subf 6, 4, 5
6563; PPC64LE-NEXT: sthcx. 6, 0, 3
6564; PPC64LE-NEXT: bne 0, .LBB387_1
6565; PPC64LE-NEXT: # BB#2:
6566; PPC64LE-NEXT: mr 3, 5
6567; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6568 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6569 ret i16 %ret
6570}
6571
6572define i16 @test388(i16* %ptr, i16 %val) {
6573; PPC64LE-LABEL: test388:
6574; PPC64LE: # BB#0:
6575; PPC64LE-NEXT: lwsync
6576; PPC64LE-NEXT: .LBB388_1:
6577; PPC64LE-NEXT: lharx 5, 0, 3
6578; PPC64LE-NEXT: subf 6, 4, 5
6579; PPC64LE-NEXT: sthcx. 6, 0, 3
6580; PPC64LE-NEXT: bne 0, .LBB388_1
6581; PPC64LE-NEXT: # BB#2:
6582; PPC64LE-NEXT: mr 3, 5
6583; PPC64LE-NEXT: lwsync
6584; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6585 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6586 ret i16 %ret
6587}
6588
6589define i16 @test389(i16* %ptr, i16 %val) {
6590; PPC64LE-LABEL: test389:
6591; PPC64LE: # BB#0:
6592; PPC64LE-NEXT: sync
6593; PPC64LE-NEXT: .LBB389_1:
6594; PPC64LE-NEXT: lharx 5, 0, 3
6595; PPC64LE-NEXT: subf 6, 4, 5
6596; PPC64LE-NEXT: sthcx. 6, 0, 3
6597; PPC64LE-NEXT: bne 0, .LBB389_1
6598; PPC64LE-NEXT: # BB#2:
6599; PPC64LE-NEXT: mr 3, 5
6600; PPC64LE-NEXT: lwsync
6601; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6602 %ret = atomicrmw sub i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6603 ret i16 %ret
6604}
6605
6606define i32 @test390(i32* %ptr, i32 %val) {
6607; PPC64LE-LABEL: test390:
6608; PPC64LE: # BB#0:
6609; PPC64LE-NEXT: .LBB390_1:
6610; PPC64LE-NEXT: lwarx 5, 0, 3
6611; PPC64LE-NEXT: subf 6, 4, 5
6612; PPC64LE-NEXT: stwcx. 6, 0, 3
6613; PPC64LE-NEXT: bne 0, .LBB390_1
6614; PPC64LE-NEXT: # BB#2:
6615; PPC64LE-NEXT: mr 3, 5
6616; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6617 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6618 ret i32 %ret
6619}
6620
6621define i32 @test391(i32* %ptr, i32 %val) {
6622; PPC64LE-LABEL: test391:
6623; PPC64LE: # BB#0:
6624; PPC64LE-NEXT: mr 5, 3
6625; PPC64LE-NEXT: .LBB391_1:
6626; PPC64LE-NEXT: lwarx 3, 0, 5
6627; PPC64LE-NEXT: subf 6, 4, 3
6628; PPC64LE-NEXT: stwcx. 6, 0, 5
6629; PPC64LE-NEXT: bne 0, .LBB391_1
6630; PPC64LE-NEXT: # BB#2:
6631; PPC64LE-NEXT: lwsync
6632; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6633 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6634 ret i32 %ret
6635}
6636
6637define i32 @test392(i32* %ptr, i32 %val) {
6638; PPC64LE-LABEL: test392:
6639; PPC64LE: # BB#0:
6640; PPC64LE-NEXT: lwsync
6641; PPC64LE-NEXT: .LBB392_1:
6642; PPC64LE-NEXT: lwarx 5, 0, 3
6643; PPC64LE-NEXT: subf 6, 4, 5
6644; PPC64LE-NEXT: stwcx. 6, 0, 3
6645; PPC64LE-NEXT: bne 0, .LBB392_1
6646; PPC64LE-NEXT: # BB#2:
6647; PPC64LE-NEXT: mr 3, 5
6648; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6649 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6650 ret i32 %ret
6651}
6652
6653define i32 @test393(i32* %ptr, i32 %val) {
6654; PPC64LE-LABEL: test393:
6655; PPC64LE: # BB#0:
6656; PPC64LE-NEXT: lwsync
6657; PPC64LE-NEXT: .LBB393_1:
6658; PPC64LE-NEXT: lwarx 5, 0, 3
6659; PPC64LE-NEXT: subf 6, 4, 5
6660; PPC64LE-NEXT: stwcx. 6, 0, 3
6661; PPC64LE-NEXT: bne 0, .LBB393_1
6662; PPC64LE-NEXT: # BB#2:
6663; PPC64LE-NEXT: mr 3, 5
6664; PPC64LE-NEXT: lwsync
6665; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6666 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6667 ret i32 %ret
6668}
6669
6670define i32 @test394(i32* %ptr, i32 %val) {
6671; PPC64LE-LABEL: test394:
6672; PPC64LE: # BB#0:
6673; PPC64LE-NEXT: sync
6674; PPC64LE-NEXT: .LBB394_1:
6675; PPC64LE-NEXT: lwarx 5, 0, 3
6676; PPC64LE-NEXT: subf 6, 4, 5
6677; PPC64LE-NEXT: stwcx. 6, 0, 3
6678; PPC64LE-NEXT: bne 0, .LBB394_1
6679; PPC64LE-NEXT: # BB#2:
6680; PPC64LE-NEXT: mr 3, 5
6681; PPC64LE-NEXT: lwsync
6682; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6683 %ret = atomicrmw sub i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6684 ret i32 %ret
6685}
6686
6687define i64 @test395(i64* %ptr, i64 %val) {
6688; PPC64LE-LABEL: test395:
6689; PPC64LE: # BB#0:
6690; PPC64LE-NEXT: .LBB395_1:
6691; PPC64LE-NEXT: ldarx 5, 0, 3
6692; PPC64LE-NEXT: sub 6, 5, 4
6693; PPC64LE-NEXT: stdcx. 6, 0, 3
6694; PPC64LE-NEXT: bne 0, .LBB395_1
6695; PPC64LE-NEXT: # BB#2:
6696; PPC64LE-NEXT: mr 3, 5
6697; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6698 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6699 ret i64 %ret
6700}
6701
6702define i64 @test396(i64* %ptr, i64 %val) {
6703; PPC64LE-LABEL: test396:
6704; PPC64LE: # BB#0:
6705; PPC64LE-NEXT: mr 5, 3
6706; PPC64LE-NEXT: .LBB396_1:
6707; PPC64LE-NEXT: ldarx 3, 0, 5
6708; PPC64LE-NEXT: sub 6, 3, 4
6709; PPC64LE-NEXT: stdcx. 6, 0, 5
6710; PPC64LE-NEXT: bne 0, .LBB396_1
6711; PPC64LE-NEXT: # BB#2:
6712; PPC64LE-NEXT: lwsync
6713; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6714 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6715 ret i64 %ret
6716}
6717
6718define i64 @test397(i64* %ptr, i64 %val) {
6719; PPC64LE-LABEL: test397:
6720; PPC64LE: # BB#0:
6721; PPC64LE-NEXT: lwsync
6722; PPC64LE-NEXT: .LBB397_1:
6723; PPC64LE-NEXT: ldarx 5, 0, 3
6724; PPC64LE-NEXT: sub 6, 5, 4
6725; PPC64LE-NEXT: stdcx. 6, 0, 3
6726; PPC64LE-NEXT: bne 0, .LBB397_1
6727; PPC64LE-NEXT: # BB#2:
6728; PPC64LE-NEXT: mr 3, 5
6729; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6730 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6731 ret i64 %ret
6732}
6733
6734define i64 @test398(i64* %ptr, i64 %val) {
6735; PPC64LE-LABEL: test398:
6736; PPC64LE: # BB#0:
6737; PPC64LE-NEXT: lwsync
6738; PPC64LE-NEXT: .LBB398_1:
6739; PPC64LE-NEXT: ldarx 5, 0, 3
6740; PPC64LE-NEXT: sub 6, 5, 4
6741; PPC64LE-NEXT: stdcx. 6, 0, 3
6742; PPC64LE-NEXT: bne 0, .LBB398_1
6743; PPC64LE-NEXT: # BB#2:
6744; PPC64LE-NEXT: mr 3, 5
6745; PPC64LE-NEXT: lwsync
6746; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6747 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6748 ret i64 %ret
6749}
6750
6751define i64 @test399(i64* %ptr, i64 %val) {
6752; PPC64LE-LABEL: test399:
6753; PPC64LE: # BB#0:
6754; PPC64LE-NEXT: sync
6755; PPC64LE-NEXT: .LBB399_1:
6756; PPC64LE-NEXT: ldarx 5, 0, 3
6757; PPC64LE-NEXT: sub 6, 5, 4
6758; PPC64LE-NEXT: stdcx. 6, 0, 3
6759; PPC64LE-NEXT: bne 0, .LBB399_1
6760; PPC64LE-NEXT: # BB#2:
6761; PPC64LE-NEXT: mr 3, 5
6762; PPC64LE-NEXT: lwsync
6763; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6764 %ret = atomicrmw sub i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6765 ret i64 %ret
6766}
6767
6768define i8 @test400(i8* %ptr, i8 %val) {
6769; PPC64LE-LABEL: test400:
6770; PPC64LE: # BB#0:
6771; PPC64LE-NEXT: .LBB400_1:
6772; PPC64LE-NEXT: lbarx 5, 0, 3
6773; PPC64LE-NEXT: and 6, 4, 5
6774; PPC64LE-NEXT: stbcx. 6, 0, 3
6775; PPC64LE-NEXT: bne 0, .LBB400_1
6776; PPC64LE-NEXT: # BB#2:
6777; PPC64LE-NEXT: mr 3, 5
6778; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6779 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6780 ret i8 %ret
6781}
6782
6783define i8 @test401(i8* %ptr, i8 %val) {
6784; PPC64LE-LABEL: test401:
6785; PPC64LE: # BB#0:
6786; PPC64LE-NEXT: mr 5, 3
6787; PPC64LE-NEXT: .LBB401_1:
6788; PPC64LE-NEXT: lbarx 3, 0, 5
6789; PPC64LE-NEXT: and 6, 4, 3
6790; PPC64LE-NEXT: stbcx. 6, 0, 5
6791; PPC64LE-NEXT: bne 0, .LBB401_1
6792; PPC64LE-NEXT: # BB#2:
6793; PPC64LE-NEXT: lwsync
6794; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6795 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6796 ret i8 %ret
6797}
6798
6799define i8 @test402(i8* %ptr, i8 %val) {
6800; PPC64LE-LABEL: test402:
6801; PPC64LE: # BB#0:
6802; PPC64LE-NEXT: lwsync
6803; PPC64LE-NEXT: .LBB402_1:
6804; PPC64LE-NEXT: lbarx 5, 0, 3
6805; PPC64LE-NEXT: and 6, 4, 5
6806; PPC64LE-NEXT: stbcx. 6, 0, 3
6807; PPC64LE-NEXT: bne 0, .LBB402_1
6808; PPC64LE-NEXT: # BB#2:
6809; PPC64LE-NEXT: mr 3, 5
6810; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6811 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6812 ret i8 %ret
6813}
6814
6815define i8 @test403(i8* %ptr, i8 %val) {
6816; PPC64LE-LABEL: test403:
6817; PPC64LE: # BB#0:
6818; PPC64LE-NEXT: lwsync
6819; PPC64LE-NEXT: .LBB403_1:
6820; PPC64LE-NEXT: lbarx 5, 0, 3
6821; PPC64LE-NEXT: and 6, 4, 5
6822; PPC64LE-NEXT: stbcx. 6, 0, 3
6823; PPC64LE-NEXT: bne 0, .LBB403_1
6824; PPC64LE-NEXT: # BB#2:
6825; PPC64LE-NEXT: mr 3, 5
6826; PPC64LE-NEXT: lwsync
6827; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6828 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6829 ret i8 %ret
6830}
6831
6832define i8 @test404(i8* %ptr, i8 %val) {
6833; PPC64LE-LABEL: test404:
6834; PPC64LE: # BB#0:
6835; PPC64LE-NEXT: sync
6836; PPC64LE-NEXT: .LBB404_1:
6837; PPC64LE-NEXT: lbarx 5, 0, 3
6838; PPC64LE-NEXT: and 6, 4, 5
6839; PPC64LE-NEXT: stbcx. 6, 0, 3
6840; PPC64LE-NEXT: bne 0, .LBB404_1
6841; PPC64LE-NEXT: # BB#2:
6842; PPC64LE-NEXT: mr 3, 5
6843; PPC64LE-NEXT: lwsync
6844; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6845 %ret = atomicrmw and i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6846 ret i8 %ret
6847}
6848
6849define i16 @test405(i16* %ptr, i16 %val) {
6850; PPC64LE-LABEL: test405:
6851; PPC64LE: # BB#0:
6852; PPC64LE-NEXT: .LBB405_1:
6853; PPC64LE-NEXT: lharx 5, 0, 3
6854; PPC64LE-NEXT: and 6, 4, 5
6855; PPC64LE-NEXT: sthcx. 6, 0, 3
6856; PPC64LE-NEXT: bne 0, .LBB405_1
6857; PPC64LE-NEXT: # BB#2:
6858; PPC64LE-NEXT: mr 3, 5
6859; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6860 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6861 ret i16 %ret
6862}
6863
6864define i16 @test406(i16* %ptr, i16 %val) {
6865; PPC64LE-LABEL: test406:
6866; PPC64LE: # BB#0:
6867; PPC64LE-NEXT: mr 5, 3
6868; PPC64LE-NEXT: .LBB406_1:
6869; PPC64LE-NEXT: lharx 3, 0, 5
6870; PPC64LE-NEXT: and 6, 4, 3
6871; PPC64LE-NEXT: sthcx. 6, 0, 5
6872; PPC64LE-NEXT: bne 0, .LBB406_1
6873; PPC64LE-NEXT: # BB#2:
6874; PPC64LE-NEXT: lwsync
6875; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6876 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6877 ret i16 %ret
6878}
6879
6880define i16 @test407(i16* %ptr, i16 %val) {
6881; PPC64LE-LABEL: test407:
6882; PPC64LE: # BB#0:
6883; PPC64LE-NEXT: lwsync
6884; PPC64LE-NEXT: .LBB407_1:
6885; PPC64LE-NEXT: lharx 5, 0, 3
6886; PPC64LE-NEXT: and 6, 4, 5
6887; PPC64LE-NEXT: sthcx. 6, 0, 3
6888; PPC64LE-NEXT: bne 0, .LBB407_1
6889; PPC64LE-NEXT: # BB#2:
6890; PPC64LE-NEXT: mr 3, 5
6891; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6892 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6893 ret i16 %ret
6894}
6895
6896define i16 @test408(i16* %ptr, i16 %val) {
6897; PPC64LE-LABEL: test408:
6898; PPC64LE: # BB#0:
6899; PPC64LE-NEXT: lwsync
6900; PPC64LE-NEXT: .LBB408_1:
6901; PPC64LE-NEXT: lharx 5, 0, 3
6902; PPC64LE-NEXT: and 6, 4, 5
6903; PPC64LE-NEXT: sthcx. 6, 0, 3
6904; PPC64LE-NEXT: bne 0, .LBB408_1
6905; PPC64LE-NEXT: # BB#2:
6906; PPC64LE-NEXT: mr 3, 5
6907; PPC64LE-NEXT: lwsync
6908; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6909 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6910 ret i16 %ret
6911}
6912
6913define i16 @test409(i16* %ptr, i16 %val) {
6914; PPC64LE-LABEL: test409:
6915; PPC64LE: # BB#0:
6916; PPC64LE-NEXT: sync
6917; PPC64LE-NEXT: .LBB409_1:
6918; PPC64LE-NEXT: lharx 5, 0, 3
6919; PPC64LE-NEXT: and 6, 4, 5
6920; PPC64LE-NEXT: sthcx. 6, 0, 3
6921; PPC64LE-NEXT: bne 0, .LBB409_1
6922; PPC64LE-NEXT: # BB#2:
6923; PPC64LE-NEXT: mr 3, 5
6924; PPC64LE-NEXT: lwsync
6925; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6926 %ret = atomicrmw and i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6927 ret i16 %ret
6928}
6929
6930define i32 @test410(i32* %ptr, i32 %val) {
6931; PPC64LE-LABEL: test410:
6932; PPC64LE: # BB#0:
6933; PPC64LE-NEXT: .LBB410_1:
6934; PPC64LE-NEXT: lwarx 5, 0, 3
6935; PPC64LE-NEXT: and 6, 4, 5
6936; PPC64LE-NEXT: stwcx. 6, 0, 3
6937; PPC64LE-NEXT: bne 0, .LBB410_1
6938; PPC64LE-NEXT: # BB#2:
6939; PPC64LE-NEXT: mr 3, 5
6940; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6941 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6942 ret i32 %ret
6943}
6944
6945define i32 @test411(i32* %ptr, i32 %val) {
6946; PPC64LE-LABEL: test411:
6947; PPC64LE: # BB#0:
6948; PPC64LE-NEXT: mr 5, 3
6949; PPC64LE-NEXT: .LBB411_1:
6950; PPC64LE-NEXT: lwarx 3, 0, 5
6951; PPC64LE-NEXT: and 6, 4, 3
6952; PPC64LE-NEXT: stwcx. 6, 0, 5
6953; PPC64LE-NEXT: bne 0, .LBB411_1
6954; PPC64LE-NEXT: # BB#2:
6955; PPC64LE-NEXT: lwsync
6956; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6957 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6958 ret i32 %ret
6959}
6960
6961define i32 @test412(i32* %ptr, i32 %val) {
6962; PPC64LE-LABEL: test412:
6963; PPC64LE: # BB#0:
6964; PPC64LE-NEXT: lwsync
6965; PPC64LE-NEXT: .LBB412_1:
6966; PPC64LE-NEXT: lwarx 5, 0, 3
6967; PPC64LE-NEXT: and 6, 4, 5
6968; PPC64LE-NEXT: stwcx. 6, 0, 3
6969; PPC64LE-NEXT: bne 0, .LBB412_1
6970; PPC64LE-NEXT: # BB#2:
6971; PPC64LE-NEXT: mr 3, 5
6972; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6973 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6974 ret i32 %ret
6975}
6976
6977define i32 @test413(i32* %ptr, i32 %val) {
6978; PPC64LE-LABEL: test413:
6979; PPC64LE: # BB#0:
6980; PPC64LE-NEXT: lwsync
6981; PPC64LE-NEXT: .LBB413_1:
6982; PPC64LE-NEXT: lwarx 5, 0, 3
6983; PPC64LE-NEXT: and 6, 4, 5
6984; PPC64LE-NEXT: stwcx. 6, 0, 3
6985; PPC64LE-NEXT: bne 0, .LBB413_1
6986; PPC64LE-NEXT: # BB#2:
6987; PPC64LE-NEXT: mr 3, 5
6988; PPC64LE-NEXT: lwsync
6989; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]6990 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]6991 ret i32 %ret
6992}
6993
6994define i32 @test414(i32* %ptr, i32 %val) {
6995; PPC64LE-LABEL: test414:
6996; PPC64LE: # BB#0:
6997; PPC64LE-NEXT: sync
6998; PPC64LE-NEXT: .LBB414_1:
6999; PPC64LE-NEXT: lwarx 5, 0, 3
7000; PPC64LE-NEXT: and 6, 4, 5
7001; PPC64LE-NEXT: stwcx. 6, 0, 3
7002; PPC64LE-NEXT: bne 0, .LBB414_1
7003; PPC64LE-NEXT: # BB#2:
7004; PPC64LE-NEXT: mr 3, 5
7005; PPC64LE-NEXT: lwsync
7006; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7007 %ret = atomicrmw and i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7008 ret i32 %ret
7009}
7010
7011define i64 @test415(i64* %ptr, i64 %val) {
7012; PPC64LE-LABEL: test415:
7013; PPC64LE: # BB#0:
7014; PPC64LE-NEXT: .LBB415_1:
7015; PPC64LE-NEXT: ldarx 5, 0, 3
7016; PPC64LE-NEXT: and 6, 4, 5
7017; PPC64LE-NEXT: stdcx. 6, 0, 3
7018; PPC64LE-NEXT: bne 0, .LBB415_1
7019; PPC64LE-NEXT: # BB#2:
7020; PPC64LE-NEXT: mr 3, 5
7021; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7022 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7023 ret i64 %ret
7024}
7025
7026define i64 @test416(i64* %ptr, i64 %val) {
7027; PPC64LE-LABEL: test416:
7028; PPC64LE: # BB#0:
7029; PPC64LE-NEXT: mr 5, 3
7030; PPC64LE-NEXT: .LBB416_1:
7031; PPC64LE-NEXT: ldarx 3, 0, 5
7032; PPC64LE-NEXT: and 6, 4, 3
7033; PPC64LE-NEXT: stdcx. 6, 0, 5
7034; PPC64LE-NEXT: bne 0, .LBB416_1
7035; PPC64LE-NEXT: # BB#2:
7036; PPC64LE-NEXT: lwsync
7037; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7038 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7039 ret i64 %ret
7040}
7041
7042define i64 @test417(i64* %ptr, i64 %val) {
7043; PPC64LE-LABEL: test417:
7044; PPC64LE: # BB#0:
7045; PPC64LE-NEXT: lwsync
7046; PPC64LE-NEXT: .LBB417_1:
7047; PPC64LE-NEXT: ldarx 5, 0, 3
7048; PPC64LE-NEXT: and 6, 4, 5
7049; PPC64LE-NEXT: stdcx. 6, 0, 3
7050; PPC64LE-NEXT: bne 0, .LBB417_1
7051; PPC64LE-NEXT: # BB#2:
7052; PPC64LE-NEXT: mr 3, 5
7053; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7054 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7055 ret i64 %ret
7056}
7057
7058define i64 @test418(i64* %ptr, i64 %val) {
7059; PPC64LE-LABEL: test418:
7060; PPC64LE: # BB#0:
7061; PPC64LE-NEXT: lwsync
7062; PPC64LE-NEXT: .LBB418_1:
7063; PPC64LE-NEXT: ldarx 5, 0, 3
7064; PPC64LE-NEXT: and 6, 4, 5
7065; PPC64LE-NEXT: stdcx. 6, 0, 3
7066; PPC64LE-NEXT: bne 0, .LBB418_1
7067; PPC64LE-NEXT: # BB#2:
7068; PPC64LE-NEXT: mr 3, 5
7069; PPC64LE-NEXT: lwsync
7070; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7071 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7072 ret i64 %ret
7073}
7074
7075define i64 @test419(i64* %ptr, i64 %val) {
7076; PPC64LE-LABEL: test419:
7077; PPC64LE: # BB#0:
7078; PPC64LE-NEXT: sync
7079; PPC64LE-NEXT: .LBB419_1:
7080; PPC64LE-NEXT: ldarx 5, 0, 3
7081; PPC64LE-NEXT: and 6, 4, 5
7082; PPC64LE-NEXT: stdcx. 6, 0, 3
7083; PPC64LE-NEXT: bne 0, .LBB419_1
7084; PPC64LE-NEXT: # BB#2:
7085; PPC64LE-NEXT: mr 3, 5
7086; PPC64LE-NEXT: lwsync
7087; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7088 %ret = atomicrmw and i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7089 ret i64 %ret
7090}
7091
7092define i8 @test420(i8* %ptr, i8 %val) {
7093; PPC64LE-LABEL: test420:
7094; PPC64LE: # BB#0:
7095; PPC64LE-NEXT: .LBB420_1:
7096; PPC64LE-NEXT: lbarx 5, 0, 3
7097; PPC64LE-NEXT: nand 6, 4, 5
7098; PPC64LE-NEXT: stbcx. 6, 0, 3
7099; PPC64LE-NEXT: bne 0, .LBB420_1
7100; PPC64LE-NEXT: # BB#2:
7101; PPC64LE-NEXT: mr 3, 5
7102; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7103 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7104 ret i8 %ret
7105}
7106
7107define i8 @test421(i8* %ptr, i8 %val) {
7108; PPC64LE-LABEL: test421:
7109; PPC64LE: # BB#0:
7110; PPC64LE-NEXT: mr 5, 3
7111; PPC64LE-NEXT: .LBB421_1:
7112; PPC64LE-NEXT: lbarx 3, 0, 5
7113; PPC64LE-NEXT: nand 6, 4, 3
7114; PPC64LE-NEXT: stbcx. 6, 0, 5
7115; PPC64LE-NEXT: bne 0, .LBB421_1
7116; PPC64LE-NEXT: # BB#2:
7117; PPC64LE-NEXT: lwsync
7118; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7119 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7120 ret i8 %ret
7121}
7122
7123define i8 @test422(i8* %ptr, i8 %val) {
7124; PPC64LE-LABEL: test422:
7125; PPC64LE: # BB#0:
7126; PPC64LE-NEXT: lwsync
7127; PPC64LE-NEXT: .LBB422_1:
7128; PPC64LE-NEXT: lbarx 5, 0, 3
7129; PPC64LE-NEXT: nand 6, 4, 5
7130; PPC64LE-NEXT: stbcx. 6, 0, 3
7131; PPC64LE-NEXT: bne 0, .LBB422_1
7132; PPC64LE-NEXT: # BB#2:
7133; PPC64LE-NEXT: mr 3, 5
7134; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7135 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7136 ret i8 %ret
7137}
7138
7139define i8 @test423(i8* %ptr, i8 %val) {
7140; PPC64LE-LABEL: test423:
7141; PPC64LE: # BB#0:
7142; PPC64LE-NEXT: lwsync
7143; PPC64LE-NEXT: .LBB423_1:
7144; PPC64LE-NEXT: lbarx 5, 0, 3
7145; PPC64LE-NEXT: nand 6, 4, 5
7146; PPC64LE-NEXT: stbcx. 6, 0, 3
7147; PPC64LE-NEXT: bne 0, .LBB423_1
7148; PPC64LE-NEXT: # BB#2:
7149; PPC64LE-NEXT: mr 3, 5
7150; PPC64LE-NEXT: lwsync
7151; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7152 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7153 ret i8 %ret
7154}
7155
7156define i8 @test424(i8* %ptr, i8 %val) {
7157; PPC64LE-LABEL: test424:
7158; PPC64LE: # BB#0:
7159; PPC64LE-NEXT: sync
7160; PPC64LE-NEXT: .LBB424_1:
7161; PPC64LE-NEXT: lbarx 5, 0, 3
7162; PPC64LE-NEXT: nand 6, 4, 5
7163; PPC64LE-NEXT: stbcx. 6, 0, 3
7164; PPC64LE-NEXT: bne 0, .LBB424_1
7165; PPC64LE-NEXT: # BB#2:
7166; PPC64LE-NEXT: mr 3, 5
7167; PPC64LE-NEXT: lwsync
7168; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7169 %ret = atomicrmw nand i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7170 ret i8 %ret
7171}
7172
7173define i16 @test425(i16* %ptr, i16 %val) {
7174; PPC64LE-LABEL: test425:
7175; PPC64LE: # BB#0:
7176; PPC64LE-NEXT: .LBB425_1:
7177; PPC64LE-NEXT: lharx 5, 0, 3
7178; PPC64LE-NEXT: nand 6, 4, 5
7179; PPC64LE-NEXT: sthcx. 6, 0, 3
7180; PPC64LE-NEXT: bne 0, .LBB425_1
7181; PPC64LE-NEXT: # BB#2:
7182; PPC64LE-NEXT: mr 3, 5
7183; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7184 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7185 ret i16 %ret
7186}
7187
7188define i16 @test426(i16* %ptr, i16 %val) {
7189; PPC64LE-LABEL: test426:
7190; PPC64LE: # BB#0:
7191; PPC64LE-NEXT: mr 5, 3
7192; PPC64LE-NEXT: .LBB426_1:
7193; PPC64LE-NEXT: lharx 3, 0, 5
7194; PPC64LE-NEXT: nand 6, 4, 3
7195; PPC64LE-NEXT: sthcx. 6, 0, 5
7196; PPC64LE-NEXT: bne 0, .LBB426_1
7197; PPC64LE-NEXT: # BB#2:
7198; PPC64LE-NEXT: lwsync
7199; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7200 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7201 ret i16 %ret
7202}
7203
7204define i16 @test427(i16* %ptr, i16 %val) {
7205; PPC64LE-LABEL: test427:
7206; PPC64LE: # BB#0:
7207; PPC64LE-NEXT: lwsync
7208; PPC64LE-NEXT: .LBB427_1:
7209; PPC64LE-NEXT: lharx 5, 0, 3
7210; PPC64LE-NEXT: nand 6, 4, 5
7211; PPC64LE-NEXT: sthcx. 6, 0, 3
7212; PPC64LE-NEXT: bne 0, .LBB427_1
7213; PPC64LE-NEXT: # BB#2:
7214; PPC64LE-NEXT: mr 3, 5
7215; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7216 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7217 ret i16 %ret
7218}
7219
7220define i16 @test428(i16* %ptr, i16 %val) {
7221; PPC64LE-LABEL: test428:
7222; PPC64LE: # BB#0:
7223; PPC64LE-NEXT: lwsync
7224; PPC64LE-NEXT: .LBB428_1:
7225; PPC64LE-NEXT: lharx 5, 0, 3
7226; PPC64LE-NEXT: nand 6, 4, 5
7227; PPC64LE-NEXT: sthcx. 6, 0, 3
7228; PPC64LE-NEXT: bne 0, .LBB428_1
7229; PPC64LE-NEXT: # BB#2:
7230; PPC64LE-NEXT: mr 3, 5
7231; PPC64LE-NEXT: lwsync
7232; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7233 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7234 ret i16 %ret
7235}
7236
7237define i16 @test429(i16* %ptr, i16 %val) {
7238; PPC64LE-LABEL: test429:
7239; PPC64LE: # BB#0:
7240; PPC64LE-NEXT: sync
7241; PPC64LE-NEXT: .LBB429_1:
7242; PPC64LE-NEXT: lharx 5, 0, 3
7243; PPC64LE-NEXT: nand 6, 4, 5
7244; PPC64LE-NEXT: sthcx. 6, 0, 3
7245; PPC64LE-NEXT: bne 0, .LBB429_1
7246; PPC64LE-NEXT: # BB#2:
7247; PPC64LE-NEXT: mr 3, 5
7248; PPC64LE-NEXT: lwsync
7249; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7250 %ret = atomicrmw nand i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7251 ret i16 %ret
7252}
7253
7254define i32 @test430(i32* %ptr, i32 %val) {
7255; PPC64LE-LABEL: test430:
7256; PPC64LE: # BB#0:
7257; PPC64LE-NEXT: .LBB430_1:
7258; PPC64LE-NEXT: lwarx 5, 0, 3
7259; PPC64LE-NEXT: nand 6, 4, 5
7260; PPC64LE-NEXT: stwcx. 6, 0, 3
7261; PPC64LE-NEXT: bne 0, .LBB430_1
7262; PPC64LE-NEXT: # BB#2:
7263; PPC64LE-NEXT: mr 3, 5
7264; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7265 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7266 ret i32 %ret
7267}
7268
7269define i32 @test431(i32* %ptr, i32 %val) {
7270; PPC64LE-LABEL: test431:
7271; PPC64LE: # BB#0:
7272; PPC64LE-NEXT: mr 5, 3
7273; PPC64LE-NEXT: .LBB431_1:
7274; PPC64LE-NEXT: lwarx 3, 0, 5
7275; PPC64LE-NEXT: nand 6, 4, 3
7276; PPC64LE-NEXT: stwcx. 6, 0, 5
7277; PPC64LE-NEXT: bne 0, .LBB431_1
7278; PPC64LE-NEXT: # BB#2:
7279; PPC64LE-NEXT: lwsync
7280; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7281 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7282 ret i32 %ret
7283}
7284
7285define i32 @test432(i32* %ptr, i32 %val) {
7286; PPC64LE-LABEL: test432:
7287; PPC64LE: # BB#0:
7288; PPC64LE-NEXT: lwsync
7289; PPC64LE-NEXT: .LBB432_1:
7290; PPC64LE-NEXT: lwarx 5, 0, 3
7291; PPC64LE-NEXT: nand 6, 4, 5
7292; PPC64LE-NEXT: stwcx. 6, 0, 3
7293; PPC64LE-NEXT: bne 0, .LBB432_1
7294; PPC64LE-NEXT: # BB#2:
7295; PPC64LE-NEXT: mr 3, 5
7296; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7297 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7298 ret i32 %ret
7299}
7300
7301define i32 @test433(i32* %ptr, i32 %val) {
7302; PPC64LE-LABEL: test433:
7303; PPC64LE: # BB#0:
7304; PPC64LE-NEXT: lwsync
7305; PPC64LE-NEXT: .LBB433_1:
7306; PPC64LE-NEXT: lwarx 5, 0, 3
7307; PPC64LE-NEXT: nand 6, 4, 5
7308; PPC64LE-NEXT: stwcx. 6, 0, 3
7309; PPC64LE-NEXT: bne 0, .LBB433_1
7310; PPC64LE-NEXT: # BB#2:
7311; PPC64LE-NEXT: mr 3, 5
7312; PPC64LE-NEXT: lwsync
7313; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7314 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7315 ret i32 %ret
7316}
7317
7318define i32 @test434(i32* %ptr, i32 %val) {
7319; PPC64LE-LABEL: test434:
7320; PPC64LE: # BB#0:
7321; PPC64LE-NEXT: sync
7322; PPC64LE-NEXT: .LBB434_1:
7323; PPC64LE-NEXT: lwarx 5, 0, 3
7324; PPC64LE-NEXT: nand 6, 4, 5
7325; PPC64LE-NEXT: stwcx. 6, 0, 3
7326; PPC64LE-NEXT: bne 0, .LBB434_1
7327; PPC64LE-NEXT: # BB#2:
7328; PPC64LE-NEXT: mr 3, 5
7329; PPC64LE-NEXT: lwsync
7330; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7331 %ret = atomicrmw nand i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7332 ret i32 %ret
7333}
7334
7335define i64 @test435(i64* %ptr, i64 %val) {
7336; PPC64LE-LABEL: test435:
7337; PPC64LE: # BB#0:
7338; PPC64LE-NEXT: .LBB435_1:
7339; PPC64LE-NEXT: ldarx 5, 0, 3
7340; PPC64LE-NEXT: nand 6, 4, 5
7341; PPC64LE-NEXT: stdcx. 6, 0, 3
7342; PPC64LE-NEXT: bne 0, .LBB435_1
7343; PPC64LE-NEXT: # BB#2:
7344; PPC64LE-NEXT: mr 3, 5
7345; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7346 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7347 ret i64 %ret
7348}
7349
7350define i64 @test436(i64* %ptr, i64 %val) {
7351; PPC64LE-LABEL: test436:
7352; PPC64LE: # BB#0:
7353; PPC64LE-NEXT: mr 5, 3
7354; PPC64LE-NEXT: .LBB436_1:
7355; PPC64LE-NEXT: ldarx 3, 0, 5
7356; PPC64LE-NEXT: nand 6, 4, 3
7357; PPC64LE-NEXT: stdcx. 6, 0, 5
7358; PPC64LE-NEXT: bne 0, .LBB436_1
7359; PPC64LE-NEXT: # BB#2:
7360; PPC64LE-NEXT: lwsync
7361; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7362 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7363 ret i64 %ret
7364}
7365
7366define i64 @test437(i64* %ptr, i64 %val) {
7367; PPC64LE-LABEL: test437:
7368; PPC64LE: # BB#0:
7369; PPC64LE-NEXT: lwsync
7370; PPC64LE-NEXT: .LBB437_1:
7371; PPC64LE-NEXT: ldarx 5, 0, 3
7372; PPC64LE-NEXT: nand 6, 4, 5
7373; PPC64LE-NEXT: stdcx. 6, 0, 3
7374; PPC64LE-NEXT: bne 0, .LBB437_1
7375; PPC64LE-NEXT: # BB#2:
7376; PPC64LE-NEXT: mr 3, 5
7377; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7378 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7379 ret i64 %ret
7380}
7381
7382define i64 @test438(i64* %ptr, i64 %val) {
7383; PPC64LE-LABEL: test438:
7384; PPC64LE: # BB#0:
7385; PPC64LE-NEXT: lwsync
7386; PPC64LE-NEXT: .LBB438_1:
7387; PPC64LE-NEXT: ldarx 5, 0, 3
7388; PPC64LE-NEXT: nand 6, 4, 5
7389; PPC64LE-NEXT: stdcx. 6, 0, 3
7390; PPC64LE-NEXT: bne 0, .LBB438_1
7391; PPC64LE-NEXT: # BB#2:
7392; PPC64LE-NEXT: mr 3, 5
7393; PPC64LE-NEXT: lwsync
7394; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7395 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7396 ret i64 %ret
7397}
7398
7399define i64 @test439(i64* %ptr, i64 %val) {
7400; PPC64LE-LABEL: test439:
7401; PPC64LE: # BB#0:
7402; PPC64LE-NEXT: sync
7403; PPC64LE-NEXT: .LBB439_1:
7404; PPC64LE-NEXT: ldarx 5, 0, 3
7405; PPC64LE-NEXT: nand 6, 4, 5
7406; PPC64LE-NEXT: stdcx. 6, 0, 3
7407; PPC64LE-NEXT: bne 0, .LBB439_1
7408; PPC64LE-NEXT: # BB#2:
7409; PPC64LE-NEXT: mr 3, 5
7410; PPC64LE-NEXT: lwsync
7411; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7412 %ret = atomicrmw nand i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7413 ret i64 %ret
7414}
7415
7416define i8 @test440(i8* %ptr, i8 %val) {
7417; PPC64LE-LABEL: test440:
7418; PPC64LE: # BB#0:
7419; PPC64LE-NEXT: .LBB440_1:
7420; PPC64LE-NEXT: lbarx 5, 0, 3
7421; PPC64LE-NEXT: or 6, 4, 5
7422; PPC64LE-NEXT: stbcx. 6, 0, 3
7423; PPC64LE-NEXT: bne 0, .LBB440_1
7424; PPC64LE-NEXT: # BB#2:
7425; PPC64LE-NEXT: mr 3, 5
7426; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7427 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7428 ret i8 %ret
7429}
7430
7431define i8 @test441(i8* %ptr, i8 %val) {
7432; PPC64LE-LABEL: test441:
7433; PPC64LE: # BB#0:
7434; PPC64LE-NEXT: mr 5, 3
7435; PPC64LE-NEXT: .LBB441_1:
7436; PPC64LE-NEXT: lbarx 3, 0, 5
7437; PPC64LE-NEXT: or 6, 4, 3
7438; PPC64LE-NEXT: stbcx. 6, 0, 5
7439; PPC64LE-NEXT: bne 0, .LBB441_1
7440; PPC64LE-NEXT: # BB#2:
7441; PPC64LE-NEXT: lwsync
7442; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7443 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7444 ret i8 %ret
7445}
7446
7447define i8 @test442(i8* %ptr, i8 %val) {
7448; PPC64LE-LABEL: test442:
7449; PPC64LE: # BB#0:
7450; PPC64LE-NEXT: lwsync
7451; PPC64LE-NEXT: .LBB442_1:
7452; PPC64LE-NEXT: lbarx 5, 0, 3
7453; PPC64LE-NEXT: or 6, 4, 5
7454; PPC64LE-NEXT: stbcx. 6, 0, 3
7455; PPC64LE-NEXT: bne 0, .LBB442_1
7456; PPC64LE-NEXT: # BB#2:
7457; PPC64LE-NEXT: mr 3, 5
7458; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7459 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7460 ret i8 %ret
7461}
7462
7463define i8 @test443(i8* %ptr, i8 %val) {
7464; PPC64LE-LABEL: test443:
7465; PPC64LE: # BB#0:
7466; PPC64LE-NEXT: lwsync
7467; PPC64LE-NEXT: .LBB443_1:
7468; PPC64LE-NEXT: lbarx 5, 0, 3
7469; PPC64LE-NEXT: or 6, 4, 5
7470; PPC64LE-NEXT: stbcx. 6, 0, 3
7471; PPC64LE-NEXT: bne 0, .LBB443_1
7472; PPC64LE-NEXT: # BB#2:
7473; PPC64LE-NEXT: mr 3, 5
7474; PPC64LE-NEXT: lwsync
7475; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7476 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7477 ret i8 %ret
7478}
7479
7480define i8 @test444(i8* %ptr, i8 %val) {
7481; PPC64LE-LABEL: test444:
7482; PPC64LE: # BB#0:
7483; PPC64LE-NEXT: sync
7484; PPC64LE-NEXT: .LBB444_1:
7485; PPC64LE-NEXT: lbarx 5, 0, 3
7486; PPC64LE-NEXT: or 6, 4, 5
7487; PPC64LE-NEXT: stbcx. 6, 0, 3
7488; PPC64LE-NEXT: bne 0, .LBB444_1
7489; PPC64LE-NEXT: # BB#2:
7490; PPC64LE-NEXT: mr 3, 5
7491; PPC64LE-NEXT: lwsync
7492; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7493 %ret = atomicrmw or i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7494 ret i8 %ret
7495}
7496
7497define i16 @test445(i16* %ptr, i16 %val) {
7498; PPC64LE-LABEL: test445:
7499; PPC64LE: # BB#0:
7500; PPC64LE-NEXT: .LBB445_1:
7501; PPC64LE-NEXT: lharx 5, 0, 3
7502; PPC64LE-NEXT: or 6, 4, 5
7503; PPC64LE-NEXT: sthcx. 6, 0, 3
7504; PPC64LE-NEXT: bne 0, .LBB445_1
7505; PPC64LE-NEXT: # BB#2:
7506; PPC64LE-NEXT: mr 3, 5
7507; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7508 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7509 ret i16 %ret
7510}
7511
7512define i16 @test446(i16* %ptr, i16 %val) {
7513; PPC64LE-LABEL: test446:
7514; PPC64LE: # BB#0:
7515; PPC64LE-NEXT: mr 5, 3
7516; PPC64LE-NEXT: .LBB446_1:
7517; PPC64LE-NEXT: lharx 3, 0, 5
7518; PPC64LE-NEXT: or 6, 4, 3
7519; PPC64LE-NEXT: sthcx. 6, 0, 5
7520; PPC64LE-NEXT: bne 0, .LBB446_1
7521; PPC64LE-NEXT: # BB#2:
7522; PPC64LE-NEXT: lwsync
7523; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7524 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7525 ret i16 %ret
7526}
7527
7528define i16 @test447(i16* %ptr, i16 %val) {
7529; PPC64LE-LABEL: test447:
7530; PPC64LE: # BB#0:
7531; PPC64LE-NEXT: lwsync
7532; PPC64LE-NEXT: .LBB447_1:
7533; PPC64LE-NEXT: lharx 5, 0, 3
7534; PPC64LE-NEXT: or 6, 4, 5
7535; PPC64LE-NEXT: sthcx. 6, 0, 3
7536; PPC64LE-NEXT: bne 0, .LBB447_1
7537; PPC64LE-NEXT: # BB#2:
7538; PPC64LE-NEXT: mr 3, 5
7539; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7540 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7541 ret i16 %ret
7542}
7543
7544define i16 @test448(i16* %ptr, i16 %val) {
7545; PPC64LE-LABEL: test448:
7546; PPC64LE: # BB#0:
7547; PPC64LE-NEXT: lwsync
7548; PPC64LE-NEXT: .LBB448_1:
7549; PPC64LE-NEXT: lharx 5, 0, 3
7550; PPC64LE-NEXT: or 6, 4, 5
7551; PPC64LE-NEXT: sthcx. 6, 0, 3
7552; PPC64LE-NEXT: bne 0, .LBB448_1
7553; PPC64LE-NEXT: # BB#2:
7554; PPC64LE-NEXT: mr 3, 5
7555; PPC64LE-NEXT: lwsync
7556; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7557 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7558 ret i16 %ret
7559}
7560
7561define i16 @test449(i16* %ptr, i16 %val) {
7562; PPC64LE-LABEL: test449:
7563; PPC64LE: # BB#0:
7564; PPC64LE-NEXT: sync
7565; PPC64LE-NEXT: .LBB449_1:
7566; PPC64LE-NEXT: lharx 5, 0, 3
7567; PPC64LE-NEXT: or 6, 4, 5
7568; PPC64LE-NEXT: sthcx. 6, 0, 3
7569; PPC64LE-NEXT: bne 0, .LBB449_1
7570; PPC64LE-NEXT: # BB#2:
7571; PPC64LE-NEXT: mr 3, 5
7572; PPC64LE-NEXT: lwsync
7573; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7574 %ret = atomicrmw or i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7575 ret i16 %ret
7576}
7577
7578define i32 @test450(i32* %ptr, i32 %val) {
7579; PPC64LE-LABEL: test450:
7580; PPC64LE: # BB#0:
7581; PPC64LE-NEXT: .LBB450_1:
7582; PPC64LE-NEXT: lwarx 5, 0, 3
7583; PPC64LE-NEXT: or 6, 4, 5
7584; PPC64LE-NEXT: stwcx. 6, 0, 3
7585; PPC64LE-NEXT: bne 0, .LBB450_1
7586; PPC64LE-NEXT: # BB#2:
7587; PPC64LE-NEXT: mr 3, 5
7588; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7589 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7590 ret i32 %ret
7591}
7592
7593define i32 @test451(i32* %ptr, i32 %val) {
7594; PPC64LE-LABEL: test451:
7595; PPC64LE: # BB#0:
7596; PPC64LE-NEXT: mr 5, 3
7597; PPC64LE-NEXT: .LBB451_1:
7598; PPC64LE-NEXT: lwarx 3, 0, 5
7599; PPC64LE-NEXT: or 6, 4, 3
7600; PPC64LE-NEXT: stwcx. 6, 0, 5
7601; PPC64LE-NEXT: bne 0, .LBB451_1
7602; PPC64LE-NEXT: # BB#2:
7603; PPC64LE-NEXT: lwsync
7604; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7605 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7606 ret i32 %ret
7607}
7608
7609define i32 @test452(i32* %ptr, i32 %val) {
7610; PPC64LE-LABEL: test452:
7611; PPC64LE: # BB#0:
7612; PPC64LE-NEXT: lwsync
7613; PPC64LE-NEXT: .LBB452_1:
7614; PPC64LE-NEXT: lwarx 5, 0, 3
7615; PPC64LE-NEXT: or 6, 4, 5
7616; PPC64LE-NEXT: stwcx. 6, 0, 3
7617; PPC64LE-NEXT: bne 0, .LBB452_1
7618; PPC64LE-NEXT: # BB#2:
7619; PPC64LE-NEXT: mr 3, 5
7620; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7621 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7622 ret i32 %ret
7623}
7624
7625define i32 @test453(i32* %ptr, i32 %val) {
7626; PPC64LE-LABEL: test453:
7627; PPC64LE: # BB#0:
7628; PPC64LE-NEXT: lwsync
7629; PPC64LE-NEXT: .LBB453_1:
7630; PPC64LE-NEXT: lwarx 5, 0, 3
7631; PPC64LE-NEXT: or 6, 4, 5
7632; PPC64LE-NEXT: stwcx. 6, 0, 3
7633; PPC64LE-NEXT: bne 0, .LBB453_1
7634; PPC64LE-NEXT: # BB#2:
7635; PPC64LE-NEXT: mr 3, 5
7636; PPC64LE-NEXT: lwsync
7637; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7638 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7639 ret i32 %ret
7640}
7641
7642define i32 @test454(i32* %ptr, i32 %val) {
7643; PPC64LE-LABEL: test454:
7644; PPC64LE: # BB#0:
7645; PPC64LE-NEXT: sync
7646; PPC64LE-NEXT: .LBB454_1:
7647; PPC64LE-NEXT: lwarx 5, 0, 3
7648; PPC64LE-NEXT: or 6, 4, 5
7649; PPC64LE-NEXT: stwcx. 6, 0, 3
7650; PPC64LE-NEXT: bne 0, .LBB454_1
7651; PPC64LE-NEXT: # BB#2:
7652; PPC64LE-NEXT: mr 3, 5
7653; PPC64LE-NEXT: lwsync
7654; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7655 %ret = atomicrmw or i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7656 ret i32 %ret
7657}
7658
7659define i64 @test455(i64* %ptr, i64 %val) {
7660; PPC64LE-LABEL: test455:
7661; PPC64LE: # BB#0:
7662; PPC64LE-NEXT: .LBB455_1:
7663; PPC64LE-NEXT: ldarx 5, 0, 3
7664; PPC64LE-NEXT: or 6, 4, 5
7665; PPC64LE-NEXT: stdcx. 6, 0, 3
7666; PPC64LE-NEXT: bne 0, .LBB455_1
7667; PPC64LE-NEXT: # BB#2:
7668; PPC64LE-NEXT: mr 3, 5
7669; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7670 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7671 ret i64 %ret
7672}
7673
7674define i64 @test456(i64* %ptr, i64 %val) {
7675; PPC64LE-LABEL: test456:
7676; PPC64LE: # BB#0:
7677; PPC64LE-NEXT: mr 5, 3
7678; PPC64LE-NEXT: .LBB456_1:
7679; PPC64LE-NEXT: ldarx 3, 0, 5
7680; PPC64LE-NEXT: or 6, 4, 3
7681; PPC64LE-NEXT: stdcx. 6, 0, 5
7682; PPC64LE-NEXT: bne 0, .LBB456_1
7683; PPC64LE-NEXT: # BB#2:
7684; PPC64LE-NEXT: lwsync
7685; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7686 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7687 ret i64 %ret
7688}
7689
7690define i64 @test457(i64* %ptr, i64 %val) {
7691; PPC64LE-LABEL: test457:
7692; PPC64LE: # BB#0:
7693; PPC64LE-NEXT: lwsync
7694; PPC64LE-NEXT: .LBB457_1:
7695; PPC64LE-NEXT: ldarx 5, 0, 3
7696; PPC64LE-NEXT: or 6, 4, 5
7697; PPC64LE-NEXT: stdcx. 6, 0, 3
7698; PPC64LE-NEXT: bne 0, .LBB457_1
7699; PPC64LE-NEXT: # BB#2:
7700; PPC64LE-NEXT: mr 3, 5
7701; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7702 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7703 ret i64 %ret
7704}
7705
7706define i64 @test458(i64* %ptr, i64 %val) {
7707; PPC64LE-LABEL: test458:
7708; PPC64LE: # BB#0:
7709; PPC64LE-NEXT: lwsync
7710; PPC64LE-NEXT: .LBB458_1:
7711; PPC64LE-NEXT: ldarx 5, 0, 3
7712; PPC64LE-NEXT: or 6, 4, 5
7713; PPC64LE-NEXT: stdcx. 6, 0, 3
7714; PPC64LE-NEXT: bne 0, .LBB458_1
7715; PPC64LE-NEXT: # BB#2:
7716; PPC64LE-NEXT: mr 3, 5
7717; PPC64LE-NEXT: lwsync
7718; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7719 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7720 ret i64 %ret
7721}
7722
7723define i64 @test459(i64* %ptr, i64 %val) {
7724; PPC64LE-LABEL: test459:
7725; PPC64LE: # BB#0:
7726; PPC64LE-NEXT: sync
7727; PPC64LE-NEXT: .LBB459_1:
7728; PPC64LE-NEXT: ldarx 5, 0, 3
7729; PPC64LE-NEXT: or 6, 4, 5
7730; PPC64LE-NEXT: stdcx. 6, 0, 3
7731; PPC64LE-NEXT: bne 0, .LBB459_1
7732; PPC64LE-NEXT: # BB#2:
7733; PPC64LE-NEXT: mr 3, 5
7734; PPC64LE-NEXT: lwsync
7735; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7736 %ret = atomicrmw or i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7737 ret i64 %ret
7738}
7739
7740define i8 @test460(i8* %ptr, i8 %val) {
7741; PPC64LE-LABEL: test460:
7742; PPC64LE: # BB#0:
7743; PPC64LE-NEXT: .LBB460_1:
7744; PPC64LE-NEXT: lbarx 5, 0, 3
7745; PPC64LE-NEXT: xor 6, 4, 5
7746; PPC64LE-NEXT: stbcx. 6, 0, 3
7747; PPC64LE-NEXT: bne 0, .LBB460_1
7748; PPC64LE-NEXT: # BB#2:
7749; PPC64LE-NEXT: mr 3, 5
7750; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7751 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7752 ret i8 %ret
7753}
7754
7755define i8 @test461(i8* %ptr, i8 %val) {
7756; PPC64LE-LABEL: test461:
7757; PPC64LE: # BB#0:
7758; PPC64LE-NEXT: mr 5, 3
7759; PPC64LE-NEXT: .LBB461_1:
7760; PPC64LE-NEXT: lbarx 3, 0, 5
7761; PPC64LE-NEXT: xor 6, 4, 3
7762; PPC64LE-NEXT: stbcx. 6, 0, 5
7763; PPC64LE-NEXT: bne 0, .LBB461_1
7764; PPC64LE-NEXT: # BB#2:
7765; PPC64LE-NEXT: lwsync
7766; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7767 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7768 ret i8 %ret
7769}
7770
7771define i8 @test462(i8* %ptr, i8 %val) {
7772; PPC64LE-LABEL: test462:
7773; PPC64LE: # BB#0:
7774; PPC64LE-NEXT: lwsync
7775; PPC64LE-NEXT: .LBB462_1:
7776; PPC64LE-NEXT: lbarx 5, 0, 3
7777; PPC64LE-NEXT: xor 6, 4, 5
7778; PPC64LE-NEXT: stbcx. 6, 0, 3
7779; PPC64LE-NEXT: bne 0, .LBB462_1
7780; PPC64LE-NEXT: # BB#2:
7781; PPC64LE-NEXT: mr 3, 5
7782; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7783 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7784 ret i8 %ret
7785}
7786
7787define i8 @test463(i8* %ptr, i8 %val) {
7788; PPC64LE-LABEL: test463:
7789; PPC64LE: # BB#0:
7790; PPC64LE-NEXT: lwsync
7791; PPC64LE-NEXT: .LBB463_1:
7792; PPC64LE-NEXT: lbarx 5, 0, 3
7793; PPC64LE-NEXT: xor 6, 4, 5
7794; PPC64LE-NEXT: stbcx. 6, 0, 3
7795; PPC64LE-NEXT: bne 0, .LBB463_1
7796; PPC64LE-NEXT: # BB#2:
7797; PPC64LE-NEXT: mr 3, 5
7798; PPC64LE-NEXT: lwsync
7799; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7800 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7801 ret i8 %ret
7802}
7803
7804define i8 @test464(i8* %ptr, i8 %val) {
7805; PPC64LE-LABEL: test464:
7806; PPC64LE: # BB#0:
7807; PPC64LE-NEXT: sync
7808; PPC64LE-NEXT: .LBB464_1:
7809; PPC64LE-NEXT: lbarx 5, 0, 3
7810; PPC64LE-NEXT: xor 6, 4, 5
7811; PPC64LE-NEXT: stbcx. 6, 0, 3
7812; PPC64LE-NEXT: bne 0, .LBB464_1
7813; PPC64LE-NEXT: # BB#2:
7814; PPC64LE-NEXT: mr 3, 5
7815; PPC64LE-NEXT: lwsync
7816; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7817 %ret = atomicrmw xor i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7818 ret i8 %ret
7819}
7820
7821define i16 @test465(i16* %ptr, i16 %val) {
7822; PPC64LE-LABEL: test465:
7823; PPC64LE: # BB#0:
7824; PPC64LE-NEXT: .LBB465_1:
7825; PPC64LE-NEXT: lharx 5, 0, 3
7826; PPC64LE-NEXT: xor 6, 4, 5
7827; PPC64LE-NEXT: sthcx. 6, 0, 3
7828; PPC64LE-NEXT: bne 0, .LBB465_1
7829; PPC64LE-NEXT: # BB#2:
7830; PPC64LE-NEXT: mr 3, 5
7831; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7832 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7833 ret i16 %ret
7834}
7835
7836define i16 @test466(i16* %ptr, i16 %val) {
7837; PPC64LE-LABEL: test466:
7838; PPC64LE: # BB#0:
7839; PPC64LE-NEXT: mr 5, 3
7840; PPC64LE-NEXT: .LBB466_1:
7841; PPC64LE-NEXT: lharx 3, 0, 5
7842; PPC64LE-NEXT: xor 6, 4, 3
7843; PPC64LE-NEXT: sthcx. 6, 0, 5
7844; PPC64LE-NEXT: bne 0, .LBB466_1
7845; PPC64LE-NEXT: # BB#2:
7846; PPC64LE-NEXT: lwsync
7847; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7848 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7849 ret i16 %ret
7850}
7851
7852define i16 @test467(i16* %ptr, i16 %val) {
7853; PPC64LE-LABEL: test467:
7854; PPC64LE: # BB#0:
7855; PPC64LE-NEXT: lwsync
7856; PPC64LE-NEXT: .LBB467_1:
7857; PPC64LE-NEXT: lharx 5, 0, 3
7858; PPC64LE-NEXT: xor 6, 4, 5
7859; PPC64LE-NEXT: sthcx. 6, 0, 3
7860; PPC64LE-NEXT: bne 0, .LBB467_1
7861; PPC64LE-NEXT: # BB#2:
7862; PPC64LE-NEXT: mr 3, 5
7863; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7864 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7865 ret i16 %ret
7866}
7867
7868define i16 @test468(i16* %ptr, i16 %val) {
7869; PPC64LE-LABEL: test468:
7870; PPC64LE: # BB#0:
7871; PPC64LE-NEXT: lwsync
7872; PPC64LE-NEXT: .LBB468_1:
7873; PPC64LE-NEXT: lharx 5, 0, 3
7874; PPC64LE-NEXT: xor 6, 4, 5
7875; PPC64LE-NEXT: sthcx. 6, 0, 3
7876; PPC64LE-NEXT: bne 0, .LBB468_1
7877; PPC64LE-NEXT: # BB#2:
7878; PPC64LE-NEXT: mr 3, 5
7879; PPC64LE-NEXT: lwsync
7880; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7881 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7882 ret i16 %ret
7883}
7884
7885define i16 @test469(i16* %ptr, i16 %val) {
7886; PPC64LE-LABEL: test469:
7887; PPC64LE: # BB#0:
7888; PPC64LE-NEXT: sync
7889; PPC64LE-NEXT: .LBB469_1:
7890; PPC64LE-NEXT: lharx 5, 0, 3
7891; PPC64LE-NEXT: xor 6, 4, 5
7892; PPC64LE-NEXT: sthcx. 6, 0, 3
7893; PPC64LE-NEXT: bne 0, .LBB469_1
7894; PPC64LE-NEXT: # BB#2:
7895; PPC64LE-NEXT: mr 3, 5
7896; PPC64LE-NEXT: lwsync
7897; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7898 %ret = atomicrmw xor i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7899 ret i16 %ret
7900}
7901
7902define i32 @test470(i32* %ptr, i32 %val) {
7903; PPC64LE-LABEL: test470:
7904; PPC64LE: # BB#0:
7905; PPC64LE-NEXT: .LBB470_1:
7906; PPC64LE-NEXT: lwarx 5, 0, 3
7907; PPC64LE-NEXT: xor 6, 4, 5
7908; PPC64LE-NEXT: stwcx. 6, 0, 3
7909; PPC64LE-NEXT: bne 0, .LBB470_1
7910; PPC64LE-NEXT: # BB#2:
7911; PPC64LE-NEXT: mr 3, 5
7912; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7913 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7914 ret i32 %ret
7915}
7916
7917define i32 @test471(i32* %ptr, i32 %val) {
7918; PPC64LE-LABEL: test471:
7919; PPC64LE: # BB#0:
7920; PPC64LE-NEXT: mr 5, 3
7921; PPC64LE-NEXT: .LBB471_1:
7922; PPC64LE-NEXT: lwarx 3, 0, 5
7923; PPC64LE-NEXT: xor 6, 4, 3
7924; PPC64LE-NEXT: stwcx. 6, 0, 5
7925; PPC64LE-NEXT: bne 0, .LBB471_1
7926; PPC64LE-NEXT: # BB#2:
7927; PPC64LE-NEXT: lwsync
7928; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7929 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7930 ret i32 %ret
7931}
7932
7933define i32 @test472(i32* %ptr, i32 %val) {
7934; PPC64LE-LABEL: test472:
7935; PPC64LE: # BB#0:
7936; PPC64LE-NEXT: lwsync
7937; PPC64LE-NEXT: .LBB472_1:
7938; PPC64LE-NEXT: lwarx 5, 0, 3
7939; PPC64LE-NEXT: xor 6, 4, 5
7940; PPC64LE-NEXT: stwcx. 6, 0, 3
7941; PPC64LE-NEXT: bne 0, .LBB472_1
7942; PPC64LE-NEXT: # BB#2:
7943; PPC64LE-NEXT: mr 3, 5
7944; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7945 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7946 ret i32 %ret
7947}
7948
7949define i32 @test473(i32* %ptr, i32 %val) {
7950; PPC64LE-LABEL: test473:
7951; PPC64LE: # BB#0:
7952; PPC64LE-NEXT: lwsync
7953; PPC64LE-NEXT: .LBB473_1:
7954; PPC64LE-NEXT: lwarx 5, 0, 3
7955; PPC64LE-NEXT: xor 6, 4, 5
7956; PPC64LE-NEXT: stwcx. 6, 0, 3
7957; PPC64LE-NEXT: bne 0, .LBB473_1
7958; PPC64LE-NEXT: # BB#2:
7959; PPC64LE-NEXT: mr 3, 5
7960; PPC64LE-NEXT: lwsync
7961; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7962 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7963 ret i32 %ret
7964}
7965
7966define i32 @test474(i32* %ptr, i32 %val) {
7967; PPC64LE-LABEL: test474:
7968; PPC64LE: # BB#0:
7969; PPC64LE-NEXT: sync
7970; PPC64LE-NEXT: .LBB474_1:
7971; PPC64LE-NEXT: lwarx 5, 0, 3
7972; PPC64LE-NEXT: xor 6, 4, 5
7973; PPC64LE-NEXT: stwcx. 6, 0, 3
7974; PPC64LE-NEXT: bne 0, .LBB474_1
7975; PPC64LE-NEXT: # BB#2:
7976; PPC64LE-NEXT: mr 3, 5
7977; PPC64LE-NEXT: lwsync
7978; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7979 %ret = atomicrmw xor i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7980 ret i32 %ret
7981}
7982
7983define i64 @test475(i64* %ptr, i64 %val) {
7984; PPC64LE-LABEL: test475:
7985; PPC64LE: # BB#0:
7986; PPC64LE-NEXT: .LBB475_1:
7987; PPC64LE-NEXT: ldarx 5, 0, 3
7988; PPC64LE-NEXT: xor 6, 4, 5
7989; PPC64LE-NEXT: stdcx. 6, 0, 3
7990; PPC64LE-NEXT: bne 0, .LBB475_1
7991; PPC64LE-NEXT: # BB#2:
7992; PPC64LE-NEXT: mr 3, 5
7993; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]7994 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]7995 ret i64 %ret
7996}
7997
7998define i64 @test476(i64* %ptr, i64 %val) {
7999; PPC64LE-LABEL: test476:
8000; PPC64LE: # BB#0:
8001; PPC64LE-NEXT: mr 5, 3
8002; PPC64LE-NEXT: .LBB476_1:
8003; PPC64LE-NEXT: ldarx 3, 0, 5
8004; PPC64LE-NEXT: xor 6, 4, 3
8005; PPC64LE-NEXT: stdcx. 6, 0, 5
8006; PPC64LE-NEXT: bne 0, .LBB476_1
8007; PPC64LE-NEXT: # BB#2:
8008; PPC64LE-NEXT: lwsync
8009; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8010 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8011 ret i64 %ret
8012}
8013
8014define i64 @test477(i64* %ptr, i64 %val) {
8015; PPC64LE-LABEL: test477:
8016; PPC64LE: # BB#0:
8017; PPC64LE-NEXT: lwsync
8018; PPC64LE-NEXT: .LBB477_1:
8019; PPC64LE-NEXT: ldarx 5, 0, 3
8020; PPC64LE-NEXT: xor 6, 4, 5
8021; PPC64LE-NEXT: stdcx. 6, 0, 3
8022; PPC64LE-NEXT: bne 0, .LBB477_1
8023; PPC64LE-NEXT: # BB#2:
8024; PPC64LE-NEXT: mr 3, 5
8025; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8026 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8027 ret i64 %ret
8028}
8029
8030define i64 @test478(i64* %ptr, i64 %val) {
8031; PPC64LE-LABEL: test478:
8032; PPC64LE: # BB#0:
8033; PPC64LE-NEXT: lwsync
8034; PPC64LE-NEXT: .LBB478_1:
8035; PPC64LE-NEXT: ldarx 5, 0, 3
8036; PPC64LE-NEXT: xor 6, 4, 5
8037; PPC64LE-NEXT: stdcx. 6, 0, 3
8038; PPC64LE-NEXT: bne 0, .LBB478_1
8039; PPC64LE-NEXT: # BB#2:
8040; PPC64LE-NEXT: mr 3, 5
8041; PPC64LE-NEXT: lwsync
8042; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8043 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8044 ret i64 %ret
8045}
8046
8047define i64 @test479(i64* %ptr, i64 %val) {
8048; PPC64LE-LABEL: test479:
8049; PPC64LE: # BB#0:
8050; PPC64LE-NEXT: sync
8051; PPC64LE-NEXT: .LBB479_1:
8052; PPC64LE-NEXT: ldarx 5, 0, 3
8053; PPC64LE-NEXT: xor 6, 4, 5
8054; PPC64LE-NEXT: stdcx. 6, 0, 3
8055; PPC64LE-NEXT: bne 0, .LBB479_1
8056; PPC64LE-NEXT: # BB#2:
8057; PPC64LE-NEXT: mr 3, 5
8058; PPC64LE-NEXT: lwsync
8059; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8060 %ret = atomicrmw xor i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8061 ret i64 %ret
8062}
8063
8064define i8 @test480(i8* %ptr, i8 %val) {
8065; PPC64LE-LABEL: test480:
8066; PPC64LE: # BB#0:
8067; PPC64LE-NEXT: .LBB480_1:
8068; PPC64LE-NEXT: lbarx 5, 0, 3
8069; PPC64LE-NEXT: extsb 6, 5
8070; PPC64LE-NEXT: cmpw 4, 6
8071; PPC64LE-NEXT: ble 0, .LBB480_3
8072; PPC64LE-NEXT: # BB#2:
8073; PPC64LE-NEXT: stbcx. 4, 0, 3
8074; PPC64LE-NEXT: bne 0, .LBB480_1
8075; PPC64LE-NEXT: .LBB480_3:
8076; PPC64LE-NEXT: mr 3, 5
8077; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8078 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8079 ret i8 %ret
8080}
8081
8082define i8 @test481(i8* %ptr, i8 %val) {
8083; PPC64LE-LABEL: test481:
8084; PPC64LE: # BB#0:
8085; PPC64LE-NEXT: mr 5, 3
8086; PPC64LE-NEXT: .LBB481_1:
8087; PPC64LE-NEXT: lbarx 3, 0, 5
8088; PPC64LE-NEXT: extsb 6, 3
8089; PPC64LE-NEXT: cmpw 4, 6
8090; PPC64LE-NEXT: ble 0, .LBB481_3
8091; PPC64LE-NEXT: # BB#2:
8092; PPC64LE-NEXT: stbcx. 4, 0, 5
8093; PPC64LE-NEXT: bne 0, .LBB481_1
8094; PPC64LE-NEXT: .LBB481_3:
8095; PPC64LE-NEXT: lwsync
8096; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8097 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8098 ret i8 %ret
8099}
8100
8101define i8 @test482(i8* %ptr, i8 %val) {
8102; PPC64LE-LABEL: test482:
8103; PPC64LE: # BB#0:
8104; PPC64LE-NEXT: lwsync
8105; PPC64LE-NEXT: .LBB482_1:
8106; PPC64LE-NEXT: lbarx 5, 0, 3
8107; PPC64LE-NEXT: extsb 6, 5
8108; PPC64LE-NEXT: cmpw 4, 6
8109; PPC64LE-NEXT: ble 0, .LBB482_3
8110; PPC64LE-NEXT: # BB#2:
8111; PPC64LE-NEXT: stbcx. 4, 0, 3
8112; PPC64LE-NEXT: bne 0, .LBB482_1
8113; PPC64LE-NEXT: .LBB482_3:
8114; PPC64LE-NEXT: mr 3, 5
8115; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8116 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8117 ret i8 %ret
8118}
8119
8120define i8 @test483(i8* %ptr, i8 %val) {
8121; PPC64LE-LABEL: test483:
8122; PPC64LE: # BB#0:
8123; PPC64LE-NEXT: lwsync
8124; PPC64LE-NEXT: .LBB483_1:
8125; PPC64LE-NEXT: lbarx 5, 0, 3
8126; PPC64LE-NEXT: extsb 6, 5
8127; PPC64LE-NEXT: cmpw 4, 6
8128; PPC64LE-NEXT: ble 0, .LBB483_3
8129; PPC64LE-NEXT: # BB#2:
8130; PPC64LE-NEXT: stbcx. 4, 0, 3
8131; PPC64LE-NEXT: bne 0, .LBB483_1
8132; PPC64LE-NEXT: .LBB483_3:
8133; PPC64LE-NEXT: mr 3, 5
8134; PPC64LE-NEXT: lwsync
8135; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8136 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8137 ret i8 %ret
8138}
8139
8140define i8 @test484(i8* %ptr, i8 %val) {
8141; PPC64LE-LABEL: test484:
8142; PPC64LE: # BB#0:
8143; PPC64LE-NEXT: sync
8144; PPC64LE-NEXT: .LBB484_1:
8145; PPC64LE-NEXT: lbarx 5, 0, 3
8146; PPC64LE-NEXT: extsb 6, 5
8147; PPC64LE-NEXT: cmpw 4, 6
8148; PPC64LE-NEXT: ble 0, .LBB484_3
8149; PPC64LE-NEXT: # BB#2:
8150; PPC64LE-NEXT: stbcx. 4, 0, 3
8151; PPC64LE-NEXT: bne 0, .LBB484_1
8152; PPC64LE-NEXT: .LBB484_3:
8153; PPC64LE-NEXT: mr 3, 5
8154; PPC64LE-NEXT: lwsync
8155; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8156 %ret = atomicrmw max i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8157 ret i8 %ret
8158}
8159
8160define i16 @test485(i16* %ptr, i16 %val) {
8161; PPC64LE-LABEL: test485:
8162; PPC64LE: # BB#0:
8163; PPC64LE-NEXT: .LBB485_1:
8164; PPC64LE-NEXT: lharx 5, 0, 3
8165; PPC64LE-NEXT: extsh 6, 5
8166; PPC64LE-NEXT: cmpw 4, 6
8167; PPC64LE-NEXT: ble 0, .LBB485_3
8168; PPC64LE-NEXT: # BB#2:
8169; PPC64LE-NEXT: sthcx. 4, 0, 3
8170; PPC64LE-NEXT: bne 0, .LBB485_1
8171; PPC64LE-NEXT: .LBB485_3:
8172; PPC64LE-NEXT: mr 3, 5
8173; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8174 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8175 ret i16 %ret
8176}
8177
8178define i16 @test486(i16* %ptr, i16 %val) {
8179; PPC64LE-LABEL: test486:
8180; PPC64LE: # BB#0:
8181; PPC64LE-NEXT: mr 5, 3
8182; PPC64LE-NEXT: .LBB486_1:
8183; PPC64LE-NEXT: lharx 3, 0, 5
8184; PPC64LE-NEXT: extsh 6, 3
8185; PPC64LE-NEXT: cmpw 4, 6
8186; PPC64LE-NEXT: ble 0, .LBB486_3
8187; PPC64LE-NEXT: # BB#2:
8188; PPC64LE-NEXT: sthcx. 4, 0, 5
8189; PPC64LE-NEXT: bne 0, .LBB486_1
8190; PPC64LE-NEXT: .LBB486_3:
8191; PPC64LE-NEXT: lwsync
8192; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8193 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8194 ret i16 %ret
8195}
8196
8197define i16 @test487(i16* %ptr, i16 %val) {
8198; PPC64LE-LABEL: test487:
8199; PPC64LE: # BB#0:
8200; PPC64LE-NEXT: lwsync
8201; PPC64LE-NEXT: .LBB487_1:
8202; PPC64LE-NEXT: lharx 5, 0, 3
8203; PPC64LE-NEXT: extsh 6, 5
8204; PPC64LE-NEXT: cmpw 4, 6
8205; PPC64LE-NEXT: ble 0, .LBB487_3
8206; PPC64LE-NEXT: # BB#2:
8207; PPC64LE-NEXT: sthcx. 4, 0, 3
8208; PPC64LE-NEXT: bne 0, .LBB487_1
8209; PPC64LE-NEXT: .LBB487_3:
8210; PPC64LE-NEXT: mr 3, 5
8211; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8212 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8213 ret i16 %ret
8214}
8215
8216define i16 @test488(i16* %ptr, i16 %val) {
8217; PPC64LE-LABEL: test488:
8218; PPC64LE: # BB#0:
8219; PPC64LE-NEXT: lwsync
8220; PPC64LE-NEXT: .LBB488_1:
8221; PPC64LE-NEXT: lharx 5, 0, 3
8222; PPC64LE-NEXT: extsh 6, 5
8223; PPC64LE-NEXT: cmpw 4, 6
8224; PPC64LE-NEXT: ble 0, .LBB488_3
8225; PPC64LE-NEXT: # BB#2:
8226; PPC64LE-NEXT: sthcx. 4, 0, 3
8227; PPC64LE-NEXT: bne 0, .LBB488_1
8228; PPC64LE-NEXT: .LBB488_3:
8229; PPC64LE-NEXT: mr 3, 5
8230; PPC64LE-NEXT: lwsync
8231; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8232 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8233 ret i16 %ret
8234}
8235
8236define i16 @test489(i16* %ptr, i16 %val) {
8237; PPC64LE-LABEL: test489:
8238; PPC64LE: # BB#0:
8239; PPC64LE-NEXT: sync
8240; PPC64LE-NEXT: .LBB489_1:
8241; PPC64LE-NEXT: lharx 5, 0, 3
8242; PPC64LE-NEXT: extsh 6, 5
8243; PPC64LE-NEXT: cmpw 4, 6
8244; PPC64LE-NEXT: ble 0, .LBB489_3
8245; PPC64LE-NEXT: # BB#2:
8246; PPC64LE-NEXT: sthcx. 4, 0, 3
8247; PPC64LE-NEXT: bne 0, .LBB489_1
8248; PPC64LE-NEXT: .LBB489_3:
8249; PPC64LE-NEXT: mr 3, 5
8250; PPC64LE-NEXT: lwsync
8251; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8252 %ret = atomicrmw max i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8253 ret i16 %ret
8254}
8255
8256define i32 @test490(i32* %ptr, i32 %val) {
8257; PPC64LE-LABEL: test490:
8258; PPC64LE: # BB#0:
8259; PPC64LE-NEXT: .LBB490_1:
8260; PPC64LE-NEXT: lwarx 5, 0, 3
8261; PPC64LE-NEXT: cmpw 4, 5
8262; PPC64LE-NEXT: ble 0, .LBB490_3
8263; PPC64LE-NEXT: # BB#2:
8264; PPC64LE-NEXT: stwcx. 4, 0, 3
8265; PPC64LE-NEXT: bne 0, .LBB490_1
8266; PPC64LE-NEXT: .LBB490_3:
8267; PPC64LE-NEXT: mr 3, 5
8268; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8269 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8270 ret i32 %ret
8271}
8272
8273define i32 @test491(i32* %ptr, i32 %val) {
8274; PPC64LE-LABEL: test491:
8275; PPC64LE: # BB#0:
8276; PPC64LE-NEXT: mr 5, 3
8277; PPC64LE-NEXT: .LBB491_1:
8278; PPC64LE-NEXT: lwarx 3, 0, 5
8279; PPC64LE-NEXT: cmpw 4, 3
8280; PPC64LE-NEXT: ble 0, .LBB491_3
8281; PPC64LE-NEXT: # BB#2:
8282; PPC64LE-NEXT: stwcx. 4, 0, 5
8283; PPC64LE-NEXT: bne 0, .LBB491_1
8284; PPC64LE-NEXT: .LBB491_3:
8285; PPC64LE-NEXT: lwsync
8286; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8287 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8288 ret i32 %ret
8289}
8290
8291define i32 @test492(i32* %ptr, i32 %val) {
8292; PPC64LE-LABEL: test492:
8293; PPC64LE: # BB#0:
8294; PPC64LE-NEXT: lwsync
8295; PPC64LE-NEXT: .LBB492_1:
8296; PPC64LE-NEXT: lwarx 5, 0, 3
8297; PPC64LE-NEXT: cmpw 4, 5
8298; PPC64LE-NEXT: ble 0, .LBB492_3
8299; PPC64LE-NEXT: # BB#2:
8300; PPC64LE-NEXT: stwcx. 4, 0, 3
8301; PPC64LE-NEXT: bne 0, .LBB492_1
8302; PPC64LE-NEXT: .LBB492_3:
8303; PPC64LE-NEXT: mr 3, 5
8304; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8305 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8306 ret i32 %ret
8307}
8308
8309define i32 @test493(i32* %ptr, i32 %val) {
8310; PPC64LE-LABEL: test493:
8311; PPC64LE: # BB#0:
8312; PPC64LE-NEXT: lwsync
8313; PPC64LE-NEXT: .LBB493_1:
8314; PPC64LE-NEXT: lwarx 5, 0, 3
8315; PPC64LE-NEXT: cmpw 4, 5
8316; PPC64LE-NEXT: ble 0, .LBB493_3
8317; PPC64LE-NEXT: # BB#2:
8318; PPC64LE-NEXT: stwcx. 4, 0, 3
8319; PPC64LE-NEXT: bne 0, .LBB493_1
8320; PPC64LE-NEXT: .LBB493_3:
8321; PPC64LE-NEXT: mr 3, 5
8322; PPC64LE-NEXT: lwsync
8323; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8324 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8325 ret i32 %ret
8326}
8327
8328define i32 @test494(i32* %ptr, i32 %val) {
8329; PPC64LE-LABEL: test494:
8330; PPC64LE: # BB#0:
8331; PPC64LE-NEXT: sync
8332; PPC64LE-NEXT: .LBB494_1:
8333; PPC64LE-NEXT: lwarx 5, 0, 3
8334; PPC64LE-NEXT: cmpw 4, 5
8335; PPC64LE-NEXT: ble 0, .LBB494_3
8336; PPC64LE-NEXT: # BB#2:
8337; PPC64LE-NEXT: stwcx. 4, 0, 3
8338; PPC64LE-NEXT: bne 0, .LBB494_1
8339; PPC64LE-NEXT: .LBB494_3:
8340; PPC64LE-NEXT: mr 3, 5
8341; PPC64LE-NEXT: lwsync
8342; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8343 %ret = atomicrmw max i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8344 ret i32 %ret
8345}
8346
8347define i64 @test495(i64* %ptr, i64 %val) {
8348; PPC64LE-LABEL: test495:
8349; PPC64LE: # BB#0:
8350; PPC64LE-NEXT: .LBB495_1:
8351; PPC64LE-NEXT: ldarx 5, 0, 3
8352; PPC64LE-NEXT: cmpd 4, 5
8353; PPC64LE-NEXT: ble 0, .LBB495_3
8354; PPC64LE-NEXT: # BB#2:
8355; PPC64LE-NEXT: stdcx. 4, 0, 3
8356; PPC64LE-NEXT: bne 0, .LBB495_1
8357; PPC64LE-NEXT: .LBB495_3:
8358; PPC64LE-NEXT: mr 3, 5
8359; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8360 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8361 ret i64 %ret
8362}
8363
8364define i64 @test496(i64* %ptr, i64 %val) {
8365; PPC64LE-LABEL: test496:
8366; PPC64LE: # BB#0:
8367; PPC64LE-NEXT: mr 5, 3
8368; PPC64LE-NEXT: .LBB496_1:
8369; PPC64LE-NEXT: ldarx 3, 0, 5
8370; PPC64LE-NEXT: cmpd 4, 3
8371; PPC64LE-NEXT: ble 0, .LBB496_3
8372; PPC64LE-NEXT: # BB#2:
8373; PPC64LE-NEXT: stdcx. 4, 0, 5
8374; PPC64LE-NEXT: bne 0, .LBB496_1
8375; PPC64LE-NEXT: .LBB496_3:
8376; PPC64LE-NEXT: lwsync
8377; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8378 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8379 ret i64 %ret
8380}
8381
8382define i64 @test497(i64* %ptr, i64 %val) {
8383; PPC64LE-LABEL: test497:
8384; PPC64LE: # BB#0:
8385; PPC64LE-NEXT: lwsync
8386; PPC64LE-NEXT: .LBB497_1:
8387; PPC64LE-NEXT: ldarx 5, 0, 3
8388; PPC64LE-NEXT: cmpd 4, 5
8389; PPC64LE-NEXT: ble 0, .LBB497_3
8390; PPC64LE-NEXT: # BB#2:
8391; PPC64LE-NEXT: stdcx. 4, 0, 3
8392; PPC64LE-NEXT: bne 0, .LBB497_1
8393; PPC64LE-NEXT: .LBB497_3:
8394; PPC64LE-NEXT: mr 3, 5
8395; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8396 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8397 ret i64 %ret
8398}
8399
8400define i64 @test498(i64* %ptr, i64 %val) {
8401; PPC64LE-LABEL: test498:
8402; PPC64LE: # BB#0:
8403; PPC64LE-NEXT: lwsync
8404; PPC64LE-NEXT: .LBB498_1:
8405; PPC64LE-NEXT: ldarx 5, 0, 3
8406; PPC64LE-NEXT: cmpd 4, 5
8407; PPC64LE-NEXT: ble 0, .LBB498_3
8408; PPC64LE-NEXT: # BB#2:
8409; PPC64LE-NEXT: stdcx. 4, 0, 3
8410; PPC64LE-NEXT: bne 0, .LBB498_1
8411; PPC64LE-NEXT: .LBB498_3:
8412; PPC64LE-NEXT: mr 3, 5
8413; PPC64LE-NEXT: lwsync
8414; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8415 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8416 ret i64 %ret
8417}
8418
8419define i64 @test499(i64* %ptr, i64 %val) {
8420; PPC64LE-LABEL: test499:
8421; PPC64LE: # BB#0:
8422; PPC64LE-NEXT: sync
8423; PPC64LE-NEXT: .LBB499_1:
8424; PPC64LE-NEXT: ldarx 5, 0, 3
8425; PPC64LE-NEXT: cmpd 4, 5
8426; PPC64LE-NEXT: ble 0, .LBB499_3
8427; PPC64LE-NEXT: # BB#2:
8428; PPC64LE-NEXT: stdcx. 4, 0, 3
8429; PPC64LE-NEXT: bne 0, .LBB499_1
8430; PPC64LE-NEXT: .LBB499_3:
8431; PPC64LE-NEXT: mr 3, 5
8432; PPC64LE-NEXT: lwsync
8433; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8434 %ret = atomicrmw max i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8435 ret i64 %ret
8436}
8437
8438define i8 @test500(i8* %ptr, i8 %val) {
8439; PPC64LE-LABEL: test500:
8440; PPC64LE: # BB#0:
8441; PPC64LE-NEXT: .LBB500_1:
8442; PPC64LE-NEXT: lbarx 5, 0, 3
8443; PPC64LE-NEXT: extsb 6, 5
8444; PPC64LE-NEXT: cmpw 4, 6
8445; PPC64LE-NEXT: bge 0, .LBB500_3
8446; PPC64LE-NEXT: # BB#2:
8447; PPC64LE-NEXT: stbcx. 4, 0, 3
8448; PPC64LE-NEXT: bne 0, .LBB500_1
8449; PPC64LE-NEXT: .LBB500_3:
8450; PPC64LE-NEXT: mr 3, 5
8451; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8452 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8453 ret i8 %ret
8454}
8455
8456define i8 @test501(i8* %ptr, i8 %val) {
8457; PPC64LE-LABEL: test501:
8458; PPC64LE: # BB#0:
8459; PPC64LE-NEXT: mr 5, 3
8460; PPC64LE-NEXT: .LBB501_1:
8461; PPC64LE-NEXT: lbarx 3, 0, 5
8462; PPC64LE-NEXT: extsb 6, 3
8463; PPC64LE-NEXT: cmpw 4, 6
8464; PPC64LE-NEXT: bge 0, .LBB501_3
8465; PPC64LE-NEXT: # BB#2:
8466; PPC64LE-NEXT: stbcx. 4, 0, 5
8467; PPC64LE-NEXT: bne 0, .LBB501_1
8468; PPC64LE-NEXT: .LBB501_3:
8469; PPC64LE-NEXT: lwsync
8470; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8471 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8472 ret i8 %ret
8473}
8474
8475define i8 @test502(i8* %ptr, i8 %val) {
8476; PPC64LE-LABEL: test502:
8477; PPC64LE: # BB#0:
8478; PPC64LE-NEXT: lwsync
8479; PPC64LE-NEXT: .LBB502_1:
8480; PPC64LE-NEXT: lbarx 5, 0, 3
8481; PPC64LE-NEXT: extsb 6, 5
8482; PPC64LE-NEXT: cmpw 4, 6
8483; PPC64LE-NEXT: bge 0, .LBB502_3
8484; PPC64LE-NEXT: # BB#2:
8485; PPC64LE-NEXT: stbcx. 4, 0, 3
8486; PPC64LE-NEXT: bne 0, .LBB502_1
8487; PPC64LE-NEXT: .LBB502_3:
8488; PPC64LE-NEXT: mr 3, 5
8489; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8490 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8491 ret i8 %ret
8492}
8493
8494define i8 @test503(i8* %ptr, i8 %val) {
8495; PPC64LE-LABEL: test503:
8496; PPC64LE: # BB#0:
8497; PPC64LE-NEXT: lwsync
8498; PPC64LE-NEXT: .LBB503_1:
8499; PPC64LE-NEXT: lbarx 5, 0, 3
8500; PPC64LE-NEXT: extsb 6, 5
8501; PPC64LE-NEXT: cmpw 4, 6
8502; PPC64LE-NEXT: bge 0, .LBB503_3
8503; PPC64LE-NEXT: # BB#2:
8504; PPC64LE-NEXT: stbcx. 4, 0, 3
8505; PPC64LE-NEXT: bne 0, .LBB503_1
8506; PPC64LE-NEXT: .LBB503_3:
8507; PPC64LE-NEXT: mr 3, 5
8508; PPC64LE-NEXT: lwsync
8509; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8510 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8511 ret i8 %ret
8512}
8513
8514define i8 @test504(i8* %ptr, i8 %val) {
8515; PPC64LE-LABEL: test504:
8516; PPC64LE: # BB#0:
8517; PPC64LE-NEXT: sync
8518; PPC64LE-NEXT: .LBB504_1:
8519; PPC64LE-NEXT: lbarx 5, 0, 3
8520; PPC64LE-NEXT: extsb 6, 5
8521; PPC64LE-NEXT: cmpw 4, 6
8522; PPC64LE-NEXT: bge 0, .LBB504_3
8523; PPC64LE-NEXT: # BB#2:
8524; PPC64LE-NEXT: stbcx. 4, 0, 3
8525; PPC64LE-NEXT: bne 0, .LBB504_1
8526; PPC64LE-NEXT: .LBB504_3:
8527; PPC64LE-NEXT: mr 3, 5
8528; PPC64LE-NEXT: lwsync
8529; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8530 %ret = atomicrmw min i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8531 ret i8 %ret
8532}
8533
8534define i16 @test505(i16* %ptr, i16 %val) {
8535; PPC64LE-LABEL: test505:
8536; PPC64LE: # BB#0:
8537; PPC64LE-NEXT: .LBB505_1:
8538; PPC64LE-NEXT: lharx 5, 0, 3
8539; PPC64LE-NEXT: extsh 6, 5
8540; PPC64LE-NEXT: cmpw 4, 6
8541; PPC64LE-NEXT: bge 0, .LBB505_3
8542; PPC64LE-NEXT: # BB#2:
8543; PPC64LE-NEXT: sthcx. 4, 0, 3
8544; PPC64LE-NEXT: bne 0, .LBB505_1
8545; PPC64LE-NEXT: .LBB505_3:
8546; PPC64LE-NEXT: mr 3, 5
8547; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8548 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8549 ret i16 %ret
8550}
8551
8552define i16 @test506(i16* %ptr, i16 %val) {
8553; PPC64LE-LABEL: test506:
8554; PPC64LE: # BB#0:
8555; PPC64LE-NEXT: mr 5, 3
8556; PPC64LE-NEXT: .LBB506_1:
8557; PPC64LE-NEXT: lharx 3, 0, 5
8558; PPC64LE-NEXT: extsh 6, 3
8559; PPC64LE-NEXT: cmpw 4, 6
8560; PPC64LE-NEXT: bge 0, .LBB506_3
8561; PPC64LE-NEXT: # BB#2:
8562; PPC64LE-NEXT: sthcx. 4, 0, 5
8563; PPC64LE-NEXT: bne 0, .LBB506_1
8564; PPC64LE-NEXT: .LBB506_3:
8565; PPC64LE-NEXT: lwsync
8566; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8567 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8568 ret i16 %ret
8569}
8570
8571define i16 @test507(i16* %ptr, i16 %val) {
8572; PPC64LE-LABEL: test507:
8573; PPC64LE: # BB#0:
8574; PPC64LE-NEXT: lwsync
8575; PPC64LE-NEXT: .LBB507_1:
8576; PPC64LE-NEXT: lharx 5, 0, 3
8577; PPC64LE-NEXT: extsh 6, 5
8578; PPC64LE-NEXT: cmpw 4, 6
8579; PPC64LE-NEXT: bge 0, .LBB507_3
8580; PPC64LE-NEXT: # BB#2:
8581; PPC64LE-NEXT: sthcx. 4, 0, 3
8582; PPC64LE-NEXT: bne 0, .LBB507_1
8583; PPC64LE-NEXT: .LBB507_3:
8584; PPC64LE-NEXT: mr 3, 5
8585; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8586 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8587 ret i16 %ret
8588}
8589
8590define i16 @test508(i16* %ptr, i16 %val) {
8591; PPC64LE-LABEL: test508:
8592; PPC64LE: # BB#0:
8593; PPC64LE-NEXT: lwsync
8594; PPC64LE-NEXT: .LBB508_1:
8595; PPC64LE-NEXT: lharx 5, 0, 3
8596; PPC64LE-NEXT: extsh 6, 5
8597; PPC64LE-NEXT: cmpw 4, 6
8598; PPC64LE-NEXT: bge 0, .LBB508_3
8599; PPC64LE-NEXT: # BB#2:
8600; PPC64LE-NEXT: sthcx. 4, 0, 3
8601; PPC64LE-NEXT: bne 0, .LBB508_1
8602; PPC64LE-NEXT: .LBB508_3:
8603; PPC64LE-NEXT: mr 3, 5
8604; PPC64LE-NEXT: lwsync
8605; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8606 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8607 ret i16 %ret
8608}
8609
8610define i16 @test509(i16* %ptr, i16 %val) {
8611; PPC64LE-LABEL: test509:
8612; PPC64LE: # BB#0:
8613; PPC64LE-NEXT: sync
8614; PPC64LE-NEXT: .LBB509_1:
8615; PPC64LE-NEXT: lharx 5, 0, 3
8616; PPC64LE-NEXT: extsh 6, 5
8617; PPC64LE-NEXT: cmpw 4, 6
8618; PPC64LE-NEXT: bge 0, .LBB509_3
8619; PPC64LE-NEXT: # BB#2:
8620; PPC64LE-NEXT: sthcx. 4, 0, 3
8621; PPC64LE-NEXT: bne 0, .LBB509_1
8622; PPC64LE-NEXT: .LBB509_3:
8623; PPC64LE-NEXT: mr 3, 5
8624; PPC64LE-NEXT: lwsync
8625; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8626 %ret = atomicrmw min i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8627 ret i16 %ret
8628}
8629
8630define i32 @test510(i32* %ptr, i32 %val) {
8631; PPC64LE-LABEL: test510:
8632; PPC64LE: # BB#0:
8633; PPC64LE-NEXT: .LBB510_1:
8634; PPC64LE-NEXT: lwarx 5, 0, 3
8635; PPC64LE-NEXT: cmpw 4, 5
8636; PPC64LE-NEXT: bge 0, .LBB510_3
8637; PPC64LE-NEXT: # BB#2:
8638; PPC64LE-NEXT: stwcx. 4, 0, 3
8639; PPC64LE-NEXT: bne 0, .LBB510_1
8640; PPC64LE-NEXT: .LBB510_3:
8641; PPC64LE-NEXT: mr 3, 5
8642; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8643 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8644 ret i32 %ret
8645}
8646
8647define i32 @test511(i32* %ptr, i32 %val) {
8648; PPC64LE-LABEL: test511:
8649; PPC64LE: # BB#0:
8650; PPC64LE-NEXT: mr 5, 3
8651; PPC64LE-NEXT: .LBB511_1:
8652; PPC64LE-NEXT: lwarx 3, 0, 5
8653; PPC64LE-NEXT: cmpw 4, 3
8654; PPC64LE-NEXT: bge 0, .LBB511_3
8655; PPC64LE-NEXT: # BB#2:
8656; PPC64LE-NEXT: stwcx. 4, 0, 5
8657; PPC64LE-NEXT: bne 0, .LBB511_1
8658; PPC64LE-NEXT: .LBB511_3:
8659; PPC64LE-NEXT: lwsync
8660; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8661 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8662 ret i32 %ret
8663}
8664
8665define i32 @test512(i32* %ptr, i32 %val) {
8666; PPC64LE-LABEL: test512:
8667; PPC64LE: # BB#0:
8668; PPC64LE-NEXT: lwsync
8669; PPC64LE-NEXT: .LBB512_1:
8670; PPC64LE-NEXT: lwarx 5, 0, 3
8671; PPC64LE-NEXT: cmpw 4, 5
8672; PPC64LE-NEXT: bge 0, .LBB512_3
8673; PPC64LE-NEXT: # BB#2:
8674; PPC64LE-NEXT: stwcx. 4, 0, 3
8675; PPC64LE-NEXT: bne 0, .LBB512_1
8676; PPC64LE-NEXT: .LBB512_3:
8677; PPC64LE-NEXT: mr 3, 5
8678; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8679 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8680 ret i32 %ret
8681}
8682
8683define i32 @test513(i32* %ptr, i32 %val) {
8684; PPC64LE-LABEL: test513:
8685; PPC64LE: # BB#0:
8686; PPC64LE-NEXT: lwsync
8687; PPC64LE-NEXT: .LBB513_1:
8688; PPC64LE-NEXT: lwarx 5, 0, 3
8689; PPC64LE-NEXT: cmpw 4, 5
8690; PPC64LE-NEXT: bge 0, .LBB513_3
8691; PPC64LE-NEXT: # BB#2:
8692; PPC64LE-NEXT: stwcx. 4, 0, 3
8693; PPC64LE-NEXT: bne 0, .LBB513_1
8694; PPC64LE-NEXT: .LBB513_3:
8695; PPC64LE-NEXT: mr 3, 5
8696; PPC64LE-NEXT: lwsync
8697; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8698 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8699 ret i32 %ret
8700}
8701
8702define i32 @test514(i32* %ptr, i32 %val) {
8703; PPC64LE-LABEL: test514:
8704; PPC64LE: # BB#0:
8705; PPC64LE-NEXT: sync
8706; PPC64LE-NEXT: .LBB514_1:
8707; PPC64LE-NEXT: lwarx 5, 0, 3
8708; PPC64LE-NEXT: cmpw 4, 5
8709; PPC64LE-NEXT: bge 0, .LBB514_3
8710; PPC64LE-NEXT: # BB#2:
8711; PPC64LE-NEXT: stwcx. 4, 0, 3
8712; PPC64LE-NEXT: bne 0, .LBB514_1
8713; PPC64LE-NEXT: .LBB514_3:
8714; PPC64LE-NEXT: mr 3, 5
8715; PPC64LE-NEXT: lwsync
8716; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8717 %ret = atomicrmw min i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8718 ret i32 %ret
8719}
8720
8721define i64 @test515(i64* %ptr, i64 %val) {
8722; PPC64LE-LABEL: test515:
8723; PPC64LE: # BB#0:
8724; PPC64LE-NEXT: .LBB515_1:
8725; PPC64LE-NEXT: ldarx 5, 0, 3
8726; PPC64LE-NEXT: cmpd 4, 5
8727; PPC64LE-NEXT: bge 0, .LBB515_3
8728; PPC64LE-NEXT: # BB#2:
8729; PPC64LE-NEXT: stdcx. 4, 0, 3
8730; PPC64LE-NEXT: bne 0, .LBB515_1
8731; PPC64LE-NEXT: .LBB515_3:
8732; PPC64LE-NEXT: mr 3, 5
8733; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8734 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8735 ret i64 %ret
8736}
8737
8738define i64 @test516(i64* %ptr, i64 %val) {
8739; PPC64LE-LABEL: test516:
8740; PPC64LE: # BB#0:
8741; PPC64LE-NEXT: mr 5, 3
8742; PPC64LE-NEXT: .LBB516_1:
8743; PPC64LE-NEXT: ldarx 3, 0, 5
8744; PPC64LE-NEXT: cmpd 4, 3
8745; PPC64LE-NEXT: bge 0, .LBB516_3
8746; PPC64LE-NEXT: # BB#2:
8747; PPC64LE-NEXT: stdcx. 4, 0, 5
8748; PPC64LE-NEXT: bne 0, .LBB516_1
8749; PPC64LE-NEXT: .LBB516_3:
8750; PPC64LE-NEXT: lwsync
8751; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8752 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8753 ret i64 %ret
8754}
8755
8756define i64 @test517(i64* %ptr, i64 %val) {
8757; PPC64LE-LABEL: test517:
8758; PPC64LE: # BB#0:
8759; PPC64LE-NEXT: lwsync
8760; PPC64LE-NEXT: .LBB517_1:
8761; PPC64LE-NEXT: ldarx 5, 0, 3
8762; PPC64LE-NEXT: cmpd 4, 5
8763; PPC64LE-NEXT: bge 0, .LBB517_3
8764; PPC64LE-NEXT: # BB#2:
8765; PPC64LE-NEXT: stdcx. 4, 0, 3
8766; PPC64LE-NEXT: bne 0, .LBB517_1
8767; PPC64LE-NEXT: .LBB517_3:
8768; PPC64LE-NEXT: mr 3, 5
8769; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8770 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8771 ret i64 %ret
8772}
8773
8774define i64 @test518(i64* %ptr, i64 %val) {
8775; PPC64LE-LABEL: test518:
8776; PPC64LE: # BB#0:
8777; PPC64LE-NEXT: lwsync
8778; PPC64LE-NEXT: .LBB518_1:
8779; PPC64LE-NEXT: ldarx 5, 0, 3
8780; PPC64LE-NEXT: cmpd 4, 5
8781; PPC64LE-NEXT: bge 0, .LBB518_3
8782; PPC64LE-NEXT: # BB#2:
8783; PPC64LE-NEXT: stdcx. 4, 0, 3
8784; PPC64LE-NEXT: bne 0, .LBB518_1
8785; PPC64LE-NEXT: .LBB518_3:
8786; PPC64LE-NEXT: mr 3, 5
8787; PPC64LE-NEXT: lwsync
8788; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8789 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8790 ret i64 %ret
8791}
8792
8793define i64 @test519(i64* %ptr, i64 %val) {
8794; PPC64LE-LABEL: test519:
8795; PPC64LE: # BB#0:
8796; PPC64LE-NEXT: sync
8797; PPC64LE-NEXT: .LBB519_1:
8798; PPC64LE-NEXT: ldarx 5, 0, 3
8799; PPC64LE-NEXT: cmpd 4, 5
8800; PPC64LE-NEXT: bge 0, .LBB519_3
8801; PPC64LE-NEXT: # BB#2:
8802; PPC64LE-NEXT: stdcx. 4, 0, 3
8803; PPC64LE-NEXT: bne 0, .LBB519_1
8804; PPC64LE-NEXT: .LBB519_3:
8805; PPC64LE-NEXT: mr 3, 5
8806; PPC64LE-NEXT: lwsync
8807; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8808 %ret = atomicrmw min i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8809 ret i64 %ret
8810}
8811
8812define i8 @test520(i8* %ptr, i8 %val) {
8813; PPC64LE-LABEL: test520:
8814; PPC64LE: # BB#0:
8815; PPC64LE-NEXT: .LBB520_1:
8816; PPC64LE-NEXT: lbarx 5, 0, 3
8817; PPC64LE-NEXT: cmplw 4, 5
8818; PPC64LE-NEXT: ble 0, .LBB520_3
8819; PPC64LE-NEXT: # BB#2:
8820; PPC64LE-NEXT: stbcx. 4, 0, 3
8821; PPC64LE-NEXT: bne 0, .LBB520_1
8822; PPC64LE-NEXT: .LBB520_3:
8823; PPC64LE-NEXT: mr 3, 5
8824; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8825 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8826 ret i8 %ret
8827}
8828
8829define i8 @test521(i8* %ptr, i8 %val) {
8830; PPC64LE-LABEL: test521:
8831; PPC64LE: # BB#0:
8832; PPC64LE-NEXT: mr 5, 3
8833; PPC64LE-NEXT: .LBB521_1:
8834; PPC64LE-NEXT: lbarx 3, 0, 5
8835; PPC64LE-NEXT: cmplw 4, 3
8836; PPC64LE-NEXT: ble 0, .LBB521_3
8837; PPC64LE-NEXT: # BB#2:
8838; PPC64LE-NEXT: stbcx. 4, 0, 5
8839; PPC64LE-NEXT: bne 0, .LBB521_1
8840; PPC64LE-NEXT: .LBB521_3:
8841; PPC64LE-NEXT: lwsync
8842; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8843 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8844 ret i8 %ret
8845}
8846
8847define i8 @test522(i8* %ptr, i8 %val) {
8848; PPC64LE-LABEL: test522:
8849; PPC64LE: # BB#0:
8850; PPC64LE-NEXT: lwsync
8851; PPC64LE-NEXT: .LBB522_1:
8852; PPC64LE-NEXT: lbarx 5, 0, 3
8853; PPC64LE-NEXT: cmplw 4, 5
8854; PPC64LE-NEXT: ble 0, .LBB522_3
8855; PPC64LE-NEXT: # BB#2:
8856; PPC64LE-NEXT: stbcx. 4, 0, 3
8857; PPC64LE-NEXT: bne 0, .LBB522_1
8858; PPC64LE-NEXT: .LBB522_3:
8859; PPC64LE-NEXT: mr 3, 5
8860; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8861 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8862 ret i8 %ret
8863}
8864
8865define i8 @test523(i8* %ptr, i8 %val) {
8866; PPC64LE-LABEL: test523:
8867; PPC64LE: # BB#0:
8868; PPC64LE-NEXT: lwsync
8869; PPC64LE-NEXT: .LBB523_1:
8870; PPC64LE-NEXT: lbarx 5, 0, 3
8871; PPC64LE-NEXT: cmplw 4, 5
8872; PPC64LE-NEXT: ble 0, .LBB523_3
8873; PPC64LE-NEXT: # BB#2:
8874; PPC64LE-NEXT: stbcx. 4, 0, 3
8875; PPC64LE-NEXT: bne 0, .LBB523_1
8876; PPC64LE-NEXT: .LBB523_3:
8877; PPC64LE-NEXT: mr 3, 5
8878; PPC64LE-NEXT: lwsync
8879; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8880 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8881 ret i8 %ret
8882}
8883
8884define i8 @test524(i8* %ptr, i8 %val) {
8885; PPC64LE-LABEL: test524:
8886; PPC64LE: # BB#0:
8887; PPC64LE-NEXT: sync
8888; PPC64LE-NEXT: .LBB524_1:
8889; PPC64LE-NEXT: lbarx 5, 0, 3
8890; PPC64LE-NEXT: cmplw 4, 5
8891; PPC64LE-NEXT: ble 0, .LBB524_3
8892; PPC64LE-NEXT: # BB#2:
8893; PPC64LE-NEXT: stbcx. 4, 0, 3
8894; PPC64LE-NEXT: bne 0, .LBB524_1
8895; PPC64LE-NEXT: .LBB524_3:
8896; PPC64LE-NEXT: mr 3, 5
8897; PPC64LE-NEXT: lwsync
8898; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8899 %ret = atomicrmw umax i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8900 ret i8 %ret
8901}
8902
8903define i16 @test525(i16* %ptr, i16 %val) {
8904; PPC64LE-LABEL: test525:
8905; PPC64LE: # BB#0:
8906; PPC64LE-NEXT: .LBB525_1:
8907; PPC64LE-NEXT: lharx 5, 0, 3
8908; PPC64LE-NEXT: cmplw 4, 5
8909; PPC64LE-NEXT: ble 0, .LBB525_3
8910; PPC64LE-NEXT: # BB#2:
8911; PPC64LE-NEXT: sthcx. 4, 0, 3
8912; PPC64LE-NEXT: bne 0, .LBB525_1
8913; PPC64LE-NEXT: .LBB525_3:
8914; PPC64LE-NEXT: mr 3, 5
8915; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8916 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8917 ret i16 %ret
8918}
8919
8920define i16 @test526(i16* %ptr, i16 %val) {
8921; PPC64LE-LABEL: test526:
8922; PPC64LE: # BB#0:
8923; PPC64LE-NEXT: mr 5, 3
8924; PPC64LE-NEXT: .LBB526_1:
8925; PPC64LE-NEXT: lharx 3, 0, 5
8926; PPC64LE-NEXT: cmplw 4, 3
8927; PPC64LE-NEXT: ble 0, .LBB526_3
8928; PPC64LE-NEXT: # BB#2:
8929; PPC64LE-NEXT: sthcx. 4, 0, 5
8930; PPC64LE-NEXT: bne 0, .LBB526_1
8931; PPC64LE-NEXT: .LBB526_3:
8932; PPC64LE-NEXT: lwsync
8933; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8934 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8935 ret i16 %ret
8936}
8937
8938define i16 @test527(i16* %ptr, i16 %val) {
8939; PPC64LE-LABEL: test527:
8940; PPC64LE: # BB#0:
8941; PPC64LE-NEXT: lwsync
8942; PPC64LE-NEXT: .LBB527_1:
8943; PPC64LE-NEXT: lharx 5, 0, 3
8944; PPC64LE-NEXT: cmplw 4, 5
8945; PPC64LE-NEXT: ble 0, .LBB527_3
8946; PPC64LE-NEXT: # BB#2:
8947; PPC64LE-NEXT: sthcx. 4, 0, 3
8948; PPC64LE-NEXT: bne 0, .LBB527_1
8949; PPC64LE-NEXT: .LBB527_3:
8950; PPC64LE-NEXT: mr 3, 5
8951; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8952 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8953 ret i16 %ret
8954}
8955
8956define i16 @test528(i16* %ptr, i16 %val) {
8957; PPC64LE-LABEL: test528:
8958; PPC64LE: # BB#0:
8959; PPC64LE-NEXT: lwsync
8960; PPC64LE-NEXT: .LBB528_1:
8961; PPC64LE-NEXT: lharx 5, 0, 3
8962; PPC64LE-NEXT: cmplw 4, 5
8963; PPC64LE-NEXT: ble 0, .LBB528_3
8964; PPC64LE-NEXT: # BB#2:
8965; PPC64LE-NEXT: sthcx. 4, 0, 3
8966; PPC64LE-NEXT: bne 0, .LBB528_1
8967; PPC64LE-NEXT: .LBB528_3:
8968; PPC64LE-NEXT: mr 3, 5
8969; PPC64LE-NEXT: lwsync
8970; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8971 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8972 ret i16 %ret
8973}
8974
8975define i16 @test529(i16* %ptr, i16 %val) {
8976; PPC64LE-LABEL: test529:
8977; PPC64LE: # BB#0:
8978; PPC64LE-NEXT: sync
8979; PPC64LE-NEXT: .LBB529_1:
8980; PPC64LE-NEXT: lharx 5, 0, 3
8981; PPC64LE-NEXT: cmplw 4, 5
8982; PPC64LE-NEXT: ble 0, .LBB529_3
8983; PPC64LE-NEXT: # BB#2:
8984; PPC64LE-NEXT: sthcx. 4, 0, 3
8985; PPC64LE-NEXT: bne 0, .LBB529_1
8986; PPC64LE-NEXT: .LBB529_3:
8987; PPC64LE-NEXT: mr 3, 5
8988; PPC64LE-NEXT: lwsync
8989; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]8990 %ret = atomicrmw umax i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]8991 ret i16 %ret
8992}
8993
8994define i32 @test530(i32* %ptr, i32 %val) {
8995; PPC64LE-LABEL: test530:
8996; PPC64LE: # BB#0:
8997; PPC64LE-NEXT: .LBB530_1:
8998; PPC64LE-NEXT: lwarx 5, 0, 3
8999; PPC64LE-NEXT: cmplw 4, 5
9000; PPC64LE-NEXT: ble 0, .LBB530_3
9001; PPC64LE-NEXT: # BB#2:
9002; PPC64LE-NEXT: stwcx. 4, 0, 3
9003; PPC64LE-NEXT: bne 0, .LBB530_1
9004; PPC64LE-NEXT: .LBB530_3:
9005; PPC64LE-NEXT: mr 3, 5
9006; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9007 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9008 ret i32 %ret
9009}
9010
9011define i32 @test531(i32* %ptr, i32 %val) {
9012; PPC64LE-LABEL: test531:
9013; PPC64LE: # BB#0:
9014; PPC64LE-NEXT: mr 5, 3
9015; PPC64LE-NEXT: .LBB531_1:
9016; PPC64LE-NEXT: lwarx 3, 0, 5
9017; PPC64LE-NEXT: cmplw 4, 3
9018; PPC64LE-NEXT: ble 0, .LBB531_3
9019; PPC64LE-NEXT: # BB#2:
9020; PPC64LE-NEXT: stwcx. 4, 0, 5
9021; PPC64LE-NEXT: bne 0, .LBB531_1
9022; PPC64LE-NEXT: .LBB531_3:
9023; PPC64LE-NEXT: lwsync
9024; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9025 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9026 ret i32 %ret
9027}
9028
9029define i32 @test532(i32* %ptr, i32 %val) {
9030; PPC64LE-LABEL: test532:
9031; PPC64LE: # BB#0:
9032; PPC64LE-NEXT: lwsync
9033; PPC64LE-NEXT: .LBB532_1:
9034; PPC64LE-NEXT: lwarx 5, 0, 3
9035; PPC64LE-NEXT: cmplw 4, 5
9036; PPC64LE-NEXT: ble 0, .LBB532_3
9037; PPC64LE-NEXT: # BB#2:
9038; PPC64LE-NEXT: stwcx. 4, 0, 3
9039; PPC64LE-NEXT: bne 0, .LBB532_1
9040; PPC64LE-NEXT: .LBB532_3:
9041; PPC64LE-NEXT: mr 3, 5
9042; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9043 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9044 ret i32 %ret
9045}
9046
9047define i32 @test533(i32* %ptr, i32 %val) {
9048; PPC64LE-LABEL: test533:
9049; PPC64LE: # BB#0:
9050; PPC64LE-NEXT: lwsync
9051; PPC64LE-NEXT: .LBB533_1:
9052; PPC64LE-NEXT: lwarx 5, 0, 3
9053; PPC64LE-NEXT: cmplw 4, 5
9054; PPC64LE-NEXT: ble 0, .LBB533_3
9055; PPC64LE-NEXT: # BB#2:
9056; PPC64LE-NEXT: stwcx. 4, 0, 3
9057; PPC64LE-NEXT: bne 0, .LBB533_1
9058; PPC64LE-NEXT: .LBB533_3:
9059; PPC64LE-NEXT: mr 3, 5
9060; PPC64LE-NEXT: lwsync
9061; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9062 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9063 ret i32 %ret
9064}
9065
9066define i32 @test534(i32* %ptr, i32 %val) {
9067; PPC64LE-LABEL: test534:
9068; PPC64LE: # BB#0:
9069; PPC64LE-NEXT: sync
9070; PPC64LE-NEXT: .LBB534_1:
9071; PPC64LE-NEXT: lwarx 5, 0, 3
9072; PPC64LE-NEXT: cmplw 4, 5
9073; PPC64LE-NEXT: ble 0, .LBB534_3
9074; PPC64LE-NEXT: # BB#2:
9075; PPC64LE-NEXT: stwcx. 4, 0, 3
9076; PPC64LE-NEXT: bne 0, .LBB534_1
9077; PPC64LE-NEXT: .LBB534_3:
9078; PPC64LE-NEXT: mr 3, 5
9079; PPC64LE-NEXT: lwsync
9080; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9081 %ret = atomicrmw umax i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9082 ret i32 %ret
9083}
9084
9085define i64 @test535(i64* %ptr, i64 %val) {
9086; PPC64LE-LABEL: test535:
9087; PPC64LE: # BB#0:
9088; PPC64LE-NEXT: .LBB535_1:
9089; PPC64LE-NEXT: ldarx 5, 0, 3
9090; PPC64LE-NEXT: cmpld 4, 5
9091; PPC64LE-NEXT: ble 0, .LBB535_3
9092; PPC64LE-NEXT: # BB#2:
9093; PPC64LE-NEXT: stdcx. 4, 0, 3
9094; PPC64LE-NEXT: bne 0, .LBB535_1
9095; PPC64LE-NEXT: .LBB535_3:
9096; PPC64LE-NEXT: mr 3, 5
9097; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9098 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9099 ret i64 %ret
9100}
9101
9102define i64 @test536(i64* %ptr, i64 %val) {
9103; PPC64LE-LABEL: test536:
9104; PPC64LE: # BB#0:
9105; PPC64LE-NEXT: mr 5, 3
9106; PPC64LE-NEXT: .LBB536_1:
9107; PPC64LE-NEXT: ldarx 3, 0, 5
9108; PPC64LE-NEXT: cmpld 4, 3
9109; PPC64LE-NEXT: ble 0, .LBB536_3
9110; PPC64LE-NEXT: # BB#2:
9111; PPC64LE-NEXT: stdcx. 4, 0, 5
9112; PPC64LE-NEXT: bne 0, .LBB536_1
9113; PPC64LE-NEXT: .LBB536_3:
9114; PPC64LE-NEXT: lwsync
9115; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9116 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9117 ret i64 %ret
9118}
9119
9120define i64 @test537(i64* %ptr, i64 %val) {
9121; PPC64LE-LABEL: test537:
9122; PPC64LE: # BB#0:
9123; PPC64LE-NEXT: lwsync
9124; PPC64LE-NEXT: .LBB537_1:
9125; PPC64LE-NEXT: ldarx 5, 0, 3
9126; PPC64LE-NEXT: cmpld 4, 5
9127; PPC64LE-NEXT: ble 0, .LBB537_3
9128; PPC64LE-NEXT: # BB#2:
9129; PPC64LE-NEXT: stdcx. 4, 0, 3
9130; PPC64LE-NEXT: bne 0, .LBB537_1
9131; PPC64LE-NEXT: .LBB537_3:
9132; PPC64LE-NEXT: mr 3, 5
9133; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9134 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9135 ret i64 %ret
9136}
9137
9138define i64 @test538(i64* %ptr, i64 %val) {
9139; PPC64LE-LABEL: test538:
9140; PPC64LE: # BB#0:
9141; PPC64LE-NEXT: lwsync
9142; PPC64LE-NEXT: .LBB538_1:
9143; PPC64LE-NEXT: ldarx 5, 0, 3
9144; PPC64LE-NEXT: cmpld 4, 5
9145; PPC64LE-NEXT: ble 0, .LBB538_3
9146; PPC64LE-NEXT: # BB#2:
9147; PPC64LE-NEXT: stdcx. 4, 0, 3
9148; PPC64LE-NEXT: bne 0, .LBB538_1
9149; PPC64LE-NEXT: .LBB538_3:
9150; PPC64LE-NEXT: mr 3, 5
9151; PPC64LE-NEXT: lwsync
9152; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9153 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9154 ret i64 %ret
9155}
9156
9157define i64 @test539(i64* %ptr, i64 %val) {
9158; PPC64LE-LABEL: test539:
9159; PPC64LE: # BB#0:
9160; PPC64LE-NEXT: sync
9161; PPC64LE-NEXT: .LBB539_1:
9162; PPC64LE-NEXT: ldarx 5, 0, 3
9163; PPC64LE-NEXT: cmpld 4, 5
9164; PPC64LE-NEXT: ble 0, .LBB539_3
9165; PPC64LE-NEXT: # BB#2:
9166; PPC64LE-NEXT: stdcx. 4, 0, 3
9167; PPC64LE-NEXT: bne 0, .LBB539_1
9168; PPC64LE-NEXT: .LBB539_3:
9169; PPC64LE-NEXT: mr 3, 5
9170; PPC64LE-NEXT: lwsync
9171; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9172 %ret = atomicrmw umax i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9173 ret i64 %ret
9174}
9175
9176define i8 @test540(i8* %ptr, i8 %val) {
9177; PPC64LE-LABEL: test540:
9178; PPC64LE: # BB#0:
9179; PPC64LE-NEXT: .LBB540_1:
9180; PPC64LE-NEXT: lbarx 5, 0, 3
9181; PPC64LE-NEXT: cmplw 4, 5
9182; PPC64LE-NEXT: bge 0, .LBB540_3
9183; PPC64LE-NEXT: # BB#2:
9184; PPC64LE-NEXT: stbcx. 4, 0, 3
9185; PPC64LE-NEXT: bne 0, .LBB540_1
9186; PPC64LE-NEXT: .LBB540_3:
9187; PPC64LE-NEXT: mr 3, 5
9188; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9189 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9190 ret i8 %ret
9191}
9192
9193define i8 @test541(i8* %ptr, i8 %val) {
9194; PPC64LE-LABEL: test541:
9195; PPC64LE: # BB#0:
9196; PPC64LE-NEXT: mr 5, 3
9197; PPC64LE-NEXT: .LBB541_1:
9198; PPC64LE-NEXT: lbarx 3, 0, 5
9199; PPC64LE-NEXT: cmplw 4, 3
9200; PPC64LE-NEXT: bge 0, .LBB541_3
9201; PPC64LE-NEXT: # BB#2:
9202; PPC64LE-NEXT: stbcx. 4, 0, 5
9203; PPC64LE-NEXT: bne 0, .LBB541_1
9204; PPC64LE-NEXT: .LBB541_3:
9205; PPC64LE-NEXT: lwsync
9206; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9207 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9208 ret i8 %ret
9209}
9210
9211define i8 @test542(i8* %ptr, i8 %val) {
9212; PPC64LE-LABEL: test542:
9213; PPC64LE: # BB#0:
9214; PPC64LE-NEXT: lwsync
9215; PPC64LE-NEXT: .LBB542_1:
9216; PPC64LE-NEXT: lbarx 5, 0, 3
9217; PPC64LE-NEXT: cmplw 4, 5
9218; PPC64LE-NEXT: bge 0, .LBB542_3
9219; PPC64LE-NEXT: # BB#2:
9220; PPC64LE-NEXT: stbcx. 4, 0, 3
9221; PPC64LE-NEXT: bne 0, .LBB542_1
9222; PPC64LE-NEXT: .LBB542_3:
9223; PPC64LE-NEXT: mr 3, 5
9224; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9225 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9226 ret i8 %ret
9227}
9228
9229define i8 @test543(i8* %ptr, i8 %val) {
9230; PPC64LE-LABEL: test543:
9231; PPC64LE: # BB#0:
9232; PPC64LE-NEXT: lwsync
9233; PPC64LE-NEXT: .LBB543_1:
9234; PPC64LE-NEXT: lbarx 5, 0, 3
9235; PPC64LE-NEXT: cmplw 4, 5
9236; PPC64LE-NEXT: bge 0, .LBB543_3
9237; PPC64LE-NEXT: # BB#2:
9238; PPC64LE-NEXT: stbcx. 4, 0, 3
9239; PPC64LE-NEXT: bne 0, .LBB543_1
9240; PPC64LE-NEXT: .LBB543_3:
9241; PPC64LE-NEXT: mr 3, 5
9242; PPC64LE-NEXT: lwsync
9243; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9244 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9245 ret i8 %ret
9246}
9247
9248define i8 @test544(i8* %ptr, i8 %val) {
9249; PPC64LE-LABEL: test544:
9250; PPC64LE: # BB#0:
9251; PPC64LE-NEXT: sync
9252; PPC64LE-NEXT: .LBB544_1:
9253; PPC64LE-NEXT: lbarx 5, 0, 3
9254; PPC64LE-NEXT: cmplw 4, 5
9255; PPC64LE-NEXT: bge 0, .LBB544_3
9256; PPC64LE-NEXT: # BB#2:
9257; PPC64LE-NEXT: stbcx. 4, 0, 3
9258; PPC64LE-NEXT: bne 0, .LBB544_1
9259; PPC64LE-NEXT: .LBB544_3:
9260; PPC64LE-NEXT: mr 3, 5
9261; PPC64LE-NEXT: lwsync
9262; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9263 %ret = atomicrmw umin i8* %ptr, i8 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9264 ret i8 %ret
9265}
9266
9267define i16 @test545(i16* %ptr, i16 %val) {
9268; PPC64LE-LABEL: test545:
9269; PPC64LE: # BB#0:
9270; PPC64LE-NEXT: .LBB545_1:
9271; PPC64LE-NEXT: lharx 5, 0, 3
9272; PPC64LE-NEXT: cmplw 4, 5
9273; PPC64LE-NEXT: bge 0, .LBB545_3
9274; PPC64LE-NEXT: # BB#2:
9275; PPC64LE-NEXT: sthcx. 4, 0, 3
9276; PPC64LE-NEXT: bne 0, .LBB545_1
9277; PPC64LE-NEXT: .LBB545_3:
9278; PPC64LE-NEXT: mr 3, 5
9279; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9280 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9281 ret i16 %ret
9282}
9283
9284define i16 @test546(i16* %ptr, i16 %val) {
9285; PPC64LE-LABEL: test546:
9286; PPC64LE: # BB#0:
9287; PPC64LE-NEXT: mr 5, 3
9288; PPC64LE-NEXT: .LBB546_1:
9289; PPC64LE-NEXT: lharx 3, 0, 5
9290; PPC64LE-NEXT: cmplw 4, 3
9291; PPC64LE-NEXT: bge 0, .LBB546_3
9292; PPC64LE-NEXT: # BB#2:
9293; PPC64LE-NEXT: sthcx. 4, 0, 5
9294; PPC64LE-NEXT: bne 0, .LBB546_1
9295; PPC64LE-NEXT: .LBB546_3:
9296; PPC64LE-NEXT: lwsync
9297; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9298 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9299 ret i16 %ret
9300}
9301
9302define i16 @test547(i16* %ptr, i16 %val) {
9303; PPC64LE-LABEL: test547:
9304; PPC64LE: # BB#0:
9305; PPC64LE-NEXT: lwsync
9306; PPC64LE-NEXT: .LBB547_1:
9307; PPC64LE-NEXT: lharx 5, 0, 3
9308; PPC64LE-NEXT: cmplw 4, 5
9309; PPC64LE-NEXT: bge 0, .LBB547_3
9310; PPC64LE-NEXT: # BB#2:
9311; PPC64LE-NEXT: sthcx. 4, 0, 3
9312; PPC64LE-NEXT: bne 0, .LBB547_1
9313; PPC64LE-NEXT: .LBB547_3:
9314; PPC64LE-NEXT: mr 3, 5
9315; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9316 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9317 ret i16 %ret
9318}
9319
9320define i16 @test548(i16* %ptr, i16 %val) {
9321; PPC64LE-LABEL: test548:
9322; PPC64LE: # BB#0:
9323; PPC64LE-NEXT: lwsync
9324; PPC64LE-NEXT: .LBB548_1:
9325; PPC64LE-NEXT: lharx 5, 0, 3
9326; PPC64LE-NEXT: cmplw 4, 5
9327; PPC64LE-NEXT: bge 0, .LBB548_3
9328; PPC64LE-NEXT: # BB#2:
9329; PPC64LE-NEXT: sthcx. 4, 0, 3
9330; PPC64LE-NEXT: bne 0, .LBB548_1
9331; PPC64LE-NEXT: .LBB548_3:
9332; PPC64LE-NEXT: mr 3, 5
9333; PPC64LE-NEXT: lwsync
9334; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9335 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9336 ret i16 %ret
9337}
9338
9339define i16 @test549(i16* %ptr, i16 %val) {
9340; PPC64LE-LABEL: test549:
9341; PPC64LE: # BB#0:
9342; PPC64LE-NEXT: sync
9343; PPC64LE-NEXT: .LBB549_1:
9344; PPC64LE-NEXT: lharx 5, 0, 3
9345; PPC64LE-NEXT: cmplw 4, 5
9346; PPC64LE-NEXT: bge 0, .LBB549_3
9347; PPC64LE-NEXT: # BB#2:
9348; PPC64LE-NEXT: sthcx. 4, 0, 3
9349; PPC64LE-NEXT: bne 0, .LBB549_1
9350; PPC64LE-NEXT: .LBB549_3:
9351; PPC64LE-NEXT: mr 3, 5
9352; PPC64LE-NEXT: lwsync
9353; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9354 %ret = atomicrmw umin i16* %ptr, i16 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9355 ret i16 %ret
9356}
9357
9358define i32 @test550(i32* %ptr, i32 %val) {
9359; PPC64LE-LABEL: test550:
9360; PPC64LE: # BB#0:
9361; PPC64LE-NEXT: .LBB550_1:
9362; PPC64LE-NEXT: lwarx 5, 0, 3
9363; PPC64LE-NEXT: cmplw 4, 5
9364; PPC64LE-NEXT: bge 0, .LBB550_3
9365; PPC64LE-NEXT: # BB#2:
9366; PPC64LE-NEXT: stwcx. 4, 0, 3
9367; PPC64LE-NEXT: bne 0, .LBB550_1
9368; PPC64LE-NEXT: .LBB550_3:
9369; PPC64LE-NEXT: mr 3, 5
9370; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9371 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9372 ret i32 %ret
9373}
9374
9375define i32 @test551(i32* %ptr, i32 %val) {
9376; PPC64LE-LABEL: test551:
9377; PPC64LE: # BB#0:
9378; PPC64LE-NEXT: mr 5, 3
9379; PPC64LE-NEXT: .LBB551_1:
9380; PPC64LE-NEXT: lwarx 3, 0, 5
9381; PPC64LE-NEXT: cmplw 4, 3
9382; PPC64LE-NEXT: bge 0, .LBB551_3
9383; PPC64LE-NEXT: # BB#2:
9384; PPC64LE-NEXT: stwcx. 4, 0, 5
9385; PPC64LE-NEXT: bne 0, .LBB551_1
9386; PPC64LE-NEXT: .LBB551_3:
9387; PPC64LE-NEXT: lwsync
9388; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9389 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9390 ret i32 %ret
9391}
9392
9393define i32 @test552(i32* %ptr, i32 %val) {
9394; PPC64LE-LABEL: test552:
9395; PPC64LE: # BB#0:
9396; PPC64LE-NEXT: lwsync
9397; PPC64LE-NEXT: .LBB552_1:
9398; PPC64LE-NEXT: lwarx 5, 0, 3
9399; PPC64LE-NEXT: cmplw 4, 5
9400; PPC64LE-NEXT: bge 0, .LBB552_3
9401; PPC64LE-NEXT: # BB#2:
9402; PPC64LE-NEXT: stwcx. 4, 0, 3
9403; PPC64LE-NEXT: bne 0, .LBB552_1
9404; PPC64LE-NEXT: .LBB552_3:
9405; PPC64LE-NEXT: mr 3, 5
9406; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9407 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9408 ret i32 %ret
9409}
9410
9411define i32 @test553(i32* %ptr, i32 %val) {
9412; PPC64LE-LABEL: test553:
9413; PPC64LE: # BB#0:
9414; PPC64LE-NEXT: lwsync
9415; PPC64LE-NEXT: .LBB553_1:
9416; PPC64LE-NEXT: lwarx 5, 0, 3
9417; PPC64LE-NEXT: cmplw 4, 5
9418; PPC64LE-NEXT: bge 0, .LBB553_3
9419; PPC64LE-NEXT: # BB#2:
9420; PPC64LE-NEXT: stwcx. 4, 0, 3
9421; PPC64LE-NEXT: bne 0, .LBB553_1
9422; PPC64LE-NEXT: .LBB553_3:
9423; PPC64LE-NEXT: mr 3, 5
9424; PPC64LE-NEXT: lwsync
9425; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9426 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9427 ret i32 %ret
9428}
9429
9430define i32 @test554(i32* %ptr, i32 %val) {
9431; PPC64LE-LABEL: test554:
9432; PPC64LE: # BB#0:
9433; PPC64LE-NEXT: sync
9434; PPC64LE-NEXT: .LBB554_1:
9435; PPC64LE-NEXT: lwarx 5, 0, 3
9436; PPC64LE-NEXT: cmplw 4, 5
9437; PPC64LE-NEXT: bge 0, .LBB554_3
9438; PPC64LE-NEXT: # BB#2:
9439; PPC64LE-NEXT: stwcx. 4, 0, 3
9440; PPC64LE-NEXT: bne 0, .LBB554_1
9441; PPC64LE-NEXT: .LBB554_3:
9442; PPC64LE-NEXT: mr 3, 5
9443; PPC64LE-NEXT: lwsync
9444; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9445 %ret = atomicrmw umin i32* %ptr, i32 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9446 ret i32 %ret
9447}
9448
9449define i64 @test555(i64* %ptr, i64 %val) {
9450; PPC64LE-LABEL: test555:
9451; PPC64LE: # BB#0:
9452; PPC64LE-NEXT: .LBB555_1:
9453; PPC64LE-NEXT: ldarx 5, 0, 3
9454; PPC64LE-NEXT: cmpld 4, 5
9455; PPC64LE-NEXT: bge 0, .LBB555_3
9456; PPC64LE-NEXT: # BB#2:
9457; PPC64LE-NEXT: stdcx. 4, 0, 3
9458; PPC64LE-NEXT: bne 0, .LBB555_1
9459; PPC64LE-NEXT: .LBB555_3:
9460; PPC64LE-NEXT: mr 3, 5
9461; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9462 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") monotonic
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9463 ret i64 %ret
9464}
9465
9466define i64 @test556(i64* %ptr, i64 %val) {
9467; PPC64LE-LABEL: test556:
9468; PPC64LE: # BB#0:
9469; PPC64LE-NEXT: mr 5, 3
9470; PPC64LE-NEXT: .LBB556_1:
9471; PPC64LE-NEXT: ldarx 3, 0, 5
9472; PPC64LE-NEXT: cmpld 4, 3
9473; PPC64LE-NEXT: bge 0, .LBB556_3
9474; PPC64LE-NEXT: # BB#2:
9475; PPC64LE-NEXT: stdcx. 4, 0, 5
9476; PPC64LE-NEXT: bne 0, .LBB556_1
9477; PPC64LE-NEXT: .LBB556_3:
9478; PPC64LE-NEXT: lwsync
9479; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9480 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") acquire
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9481 ret i64 %ret
9482}
9483
9484define i64 @test557(i64* %ptr, i64 %val) {
9485; PPC64LE-LABEL: test557:
9486; PPC64LE: # BB#0:
9487; PPC64LE-NEXT: lwsync
9488; PPC64LE-NEXT: .LBB557_1:
9489; PPC64LE-NEXT: ldarx 5, 0, 3
9490; PPC64LE-NEXT: cmpld 4, 5
9491; PPC64LE-NEXT: bge 0, .LBB557_3
9492; PPC64LE-NEXT: # BB#2:
9493; PPC64LE-NEXT: stdcx. 4, 0, 3
9494; PPC64LE-NEXT: bne 0, .LBB557_1
9495; PPC64LE-NEXT: .LBB557_3:
9496; PPC64LE-NEXT: mr 3, 5
9497; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9498 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") release
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9499 ret i64 %ret
9500}
9501
9502define i64 @test558(i64* %ptr, i64 %val) {
9503; PPC64LE-LABEL: test558:
9504; PPC64LE: # BB#0:
9505; PPC64LE-NEXT: lwsync
9506; PPC64LE-NEXT: .LBB558_1:
9507; PPC64LE-NEXT: ldarx 5, 0, 3
9508; PPC64LE-NEXT: cmpld 4, 5
9509; PPC64LE-NEXT: bge 0, .LBB558_3
9510; PPC64LE-NEXT: # BB#2:
9511; PPC64LE-NEXT: stdcx. 4, 0, 3
9512; PPC64LE-NEXT: bne 0, .LBB558_1
9513; PPC64LE-NEXT: .LBB558_3:
9514; PPC64LE-NEXT: mr 3, 5
9515; PPC64LE-NEXT: lwsync
9516; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9517 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") acq_rel
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9518 ret i64 %ret
9519}
9520
9521define i64 @test559(i64* %ptr, i64 %val) {
9522; PPC64LE-LABEL: test559:
9523; PPC64LE: # BB#0:
9524; PPC64LE-NEXT: sync
9525; PPC64LE-NEXT: .LBB559_1:
9526; PPC64LE-NEXT: ldarx 5, 0, 3
9527; PPC64LE-NEXT: cmpld 4, 5
9528; PPC64LE-NEXT: bge 0, .LBB559_3
9529; PPC64LE-NEXT: # BB#2:
9530; PPC64LE-NEXT: stdcx. 4, 0, 3
9531; PPC64LE-NEXT: bne 0, .LBB559_1
9532; PPC64LE-NEXT: .LBB559_3:
9533; PPC64LE-NEXT: mr 3, 5
9534; PPC64LE-NEXT: lwsync
9535; PPC64LE-NEXT: blr
Konstantin Zhuravlyovbb80d3e2017-07-11 22:23:00 +0000[diff] [blame]9536 %ret = atomicrmw umin i64* %ptr, i64 %val syncscope("singlethread") seq_cst
Tim Shence26a452017-03-23 16:02:47 +0000[diff] [blame]9537 ret i64 %ret
9538}
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]9539
9540; The second load should never be scheduled before isync.
9541define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) {
9542; PPC64LE-LABEL: test_ordering0:
9543; PPC64LE: # BB#0:
9544; PPC64LE-NEXT: lwz 4, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]9545; PPC64LE-NEXT: cmpd 7, 4, 4
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]9546; PPC64LE-NEXT: bne- 7, .+4
9547; PPC64LE-NEXT: isync
9548; PPC64LE-NEXT: lwz 3, 0(3)
9549; PPC64LE-NEXT: add 3, 4, 3
9550; PPC64LE-NEXT: blr
9551 %val1 = load atomic i32, i32* %ptr1 acquire, align 4
9552 %val2 = load i32, i32* %ptr1
9553 %add = add i32 %val1, %val2
9554 ret i32 %add
9555}
9556
9557; The second store should never be scheduled before isync.
9558define i32 @test_ordering1(i32* %ptr1, i32 %val1, i32* %ptr2) {
9559; PPC64LE-LABEL: test_ordering1:
9560; PPC64LE: # BB#0:
9561; PPC64LE-NEXT: lwz 3, 0(3)
Hiroshi Inoue7a08bb12017-06-15 16:51:28 +0000[diff] [blame]9562; PPC64LE-NEXT: cmpd 7, 3, 3
Tim Shen3bef27c2017-05-16 20:18:06 +0000[diff] [blame]9563; PPC64LE-NEXT: bne- 7, .+4
9564; PPC64LE-NEXT: isync
9565; PPC64LE-NEXT: stw 4, 0(5)
9566; PPC64LE-NEXT: blr
9567 %val2 = load atomic i32, i32* %ptr1 acquire, align 4
9568 store i32 %val1, i32* %ptr2
9569 ret i32 %val2
9570}