Tim Shen | ce26a45 | 2017-03-23 16:02:47 +0000 | [diff] [blame] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | ; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s -check-prefix=PPC64LE |
| 3 | |
| 4 | define i8 @test0(i8* %ptr) { |
| 5 | ; PPC64LE-LABEL: test0: |
| 6 | ; PPC64LE: # BB#0: |
| 7 | ; PPC64LE-NEXT: lbz 3, 0(3) |
| 8 | ; PPC64LE-NEXT: blr |
| 9 | %val = load atomic i8, i8* %ptr unordered, align 1 |
| 10 | ret i8 %val |
| 11 | } |
| 12 | |
| 13 | define i8 @test1(i8* %ptr) { |
| 14 | ; PPC64LE-LABEL: test1: |
| 15 | ; PPC64LE: # BB#0: |
| 16 | ; PPC64LE-NEXT: lbz 3, 0(3) |
| 17 | ; PPC64LE-NEXT: blr |
| 18 | %val = load atomic i8, i8* %ptr monotonic, align 1 |
| 19 | ret i8 %val |
| 20 | } |
| 21 | |
| 22 | define i8 @test2(i8* %ptr) { |
| 23 | ; PPC64LE-LABEL: test2: |
| 24 | ; PPC64LE: # BB#0: |
| 25 | ; PPC64LE-NEXT: lbz 3, 0(3) |
Hiroshi Inoue | 7a08bb1 | 2017-06-15 16:51:28 +0000 | [diff] [blame^] | 26 | ; PPC64LE-NEXT: cmpd 7, 3, 3 |
Tim Shen | 3bef27c | 2017-05-16 20:18:06 +0000 | [diff] [blame] | 27 | ; PPC64LE-NEXT: bne- 7, .+4 |
| 28 | ; PPC64LE-NEXT: isync |
Tim Shen | ce26a45 | 2017-03-23 16:02:47 +0000 | [diff] [blame] | 29 | ; PPC64LE-NEXT: blr |
| 30 | %val = load atomic i8, i8* %ptr acquire, align 1 |
| 31 | ret i8 %val |
| 32 | } |
| 33 | |
| 34 | define i8 @test3(i8* %ptr) { |
| 35 | ; PPC64LE-LABEL: test3: |
| 36 | ; PPC64LE: # BB#0: |
| 37 | ; PPC64LE-NEXT: sync |
| 38 | ; PPC64LE-NEXT: ori 2, 2, 0 |
| 39 | ; PPC64LE-NEXT: lbz 3, 0(3) |
Hiroshi Inoue | 7a08bb1 | 2017-06-15 16:51:28 +0000 | [diff] [blame^] | 40 | ; PPC64LE-NEXT: cmpd 7, 3, 3 |
Tim Shen | 3bef27c | 2017-05-16 20:18:06 +0000 | [diff] [blame] | 41 | ; PPC64LE-NEXT: bne- 7, .+4 |
| 42 | ; PPC64LE-NEXT: isync |
Tim Shen | ce26a45 | 2017-03-23 16:02:47 +0000 | [diff] [blame] | 43 | ; PPC64LE-NEXT: blr |
| 44 | %val = load atomic i8, i8* %ptr seq_cst, align 1 |
| 45 | ret i8 %val |
| 46 | } |
| 47 | |
| 48 | define i16 @test4(i16* %ptr) { |
| 49 | ; PPC64LE-LABEL: test4: |
| 50 | ; PPC64LE: # BB#0: |
| 51 | ; PPC64LE-NEXT: lhz 3, 0(3) |
| 52 | ; PPC64LE-NEXT: blr |
| 53 | %val = load atomic i16, i16* %ptr unordered, align 2 |
| 54 | ret i16 %val |
| 55 | } |
| 56 | |
| 57 | define i16 @test5(i16* %ptr) { |
| 58 | ; PPC64LE-LABEL: test5: |
| 59 | ; PPC64LE: # BB#0: |
| 60 | ; PPC64LE-NEXT: lhz 3, 0(3) |
| 61 | ; PPC64LE-NEXT: blr |
| 62 | %val = load atomic i16, i16* %ptr monotonic, align 2 |
| 63 | ret i16 %val |
| 64 | } |
| 65 | |
| 66 | define i16 @test6(i16* %ptr) { |
| 67 | ; PPC64LE-LABEL: test6: |
| 68 | ; PPC64LE: # BB#0: |
| 69 | ; PPC64LE-NEXT: lhz 3, 0(3) |
Hiroshi Inoue | 7a08bb1 | 2017-06-15 16:51:28 +0000 | [diff] [blame^] | 70 | ; PPC64LE-NEXT: cmpd 7, 3, 3 |
Tim Shen | 3bef27c | 2017-05-16 20:18:06 +0000 | [diff] [blame] | 71 | ; PPC64LE-NEXT: bne- 7, .+4 |
| 72 | ; PPC64LE-NEXT: isync |
Tim Shen | ce26a45 | 2017-03-23 16:02:47 +0000 | [diff] [blame] | 73 | ; PPC64LE-NEXT: blr |
| 74 | %val = load atomic i16, i16* %ptr acquire, align 2 |
| 75 | ret i16 %val |
| 76 | } |
| 77 | |
| 78 | define i16 @test7(i16* %ptr) { |
| 79 | ; PPC64LE-LABEL: test7: |
| 80 | ; PPC64LE: # BB#0: |
| 81 | ; PPC64LE-NEXT: sync |
| 82 | ; PPC64LE-NEXT: ori 2, 2, 0 |
| 83 | ; PPC64LE-NEXT: lhz 3, 0(3) |
Hiroshi Inoue | 7a08bb1 | 2017-06-15 16:51:28 +0000 | [diff] [blame^] | 84 | ; PPC64LE-NEXT: cmpd 7, 3, 3 |
Tim Shen | 3bef27c | 2017-05-16 20:18:06 +0000 | [diff] [blame] | 85 | ; PPC64LE-NEXT: bne- 7, .+4 |
| 86 | ; PPC64LE-NEXT: isync |
Tim Shen | ce26a45 | 2017-03-23 16:02:47 +0000 | [diff] [blame] | 87 | ; PPC64LE-NEXT: blr |
| 88 | %val = load atomic i16, i16* %ptr seq_cst, align 2 |
| 89 | ret i16 %val |
| 90 | } |
| 91 | |
| 92 | define i32 @test8(i32* %ptr) { |
| 93 | ; PPC64LE-LABEL: test8: |
| 94 | ; PPC64LE: # BB#0: |
| 95 | ; PPC64LE-NEXT: lwz 3, 0(3) |
| 96 | ; PPC64LE-NEXT: blr |
| 97 | %val = load atomic i32, i32* %ptr unordered, align 4 |
| 98 | ret i32 %val |
| 99 | } |
| 100 | |
| 101 | define i32 @test9(i32* %ptr) { |
| 102 | ; PPC64LE-LABEL: test9: |
| 103 | ; PPC64LE: # BB#0: |
| 104 | ; PPC64LE-NEXT: lwz 3, 0(3) |
| 105 | ; PPC64LE-NEXT: blr |
| 106 | %val = load atomic i32, i32* %ptr monotonic, align 4 |
| 107 | ret i32 %val |
| 108 | } |
| 109 | |
| 110 | define i32 @test10(i32* %ptr) { |
| 111 | ; PPC64LE-LABEL: test10: |
| 112 | ; PPC64LE: # BB#0: |
| 113 | ; PPC64LE-NEXT: lwz 3, 0(3) |
Hiroshi Inoue | 7a08bb1 | 2017-06-15 16:51:28 +0000 | [diff] [blame^] | 114 | ; PPC64LE-NEXT: cmpd 7, 3, 3 |
Tim Shen | 3bef27c | 2017-05-16 20:18:06 +0000 | [diff] [blame] | 115 | ; PPC64LE-NEXT: bne- 7, .+4 |
| 116 | ; PPC64LE-NEXT: isync |
Tim Shen | ce26a45 | 2017-03-23 16:02:47 +0000 | [diff] [blame] | 117 | ; PPC64LE-NEXT: blr |
| 118 | %val = load atomic i32, i32* %ptr acquire, align 4 |
| 119 | ret i32 %val |
| 120 | } |
| 121 | |
| 122 | define i32 @test11(i32* %ptr) { |
| 123 | ; PPC64LE-LABEL: test11: |
| 124 | ; PPC64LE: # BB#0: |
| 125 | ; PPC64LE-NEXT: sync |
| 126 | ; PPC64LE-NEXT: ori 2, 2, 0 |
| 127 | ; PPC64LE-NEXT: lwz 3, 0(3) |
Hiroshi Inoue | 7a08bb1 | 2017-06-15 16:51:28 +0000 | [diff] [blame^] | 128 | ; PPC64LE-NEXT: cmpd 7, 3, 3 |
Tim Shen | 3bef27c | 2017-05-16 20:18:06 +0000 | [diff] [blame] | 129 | ; PPC64LE-NEXT: bne- 7, .+4 |
| 130 | ; PPC64LE-NEXT: isync |
Tim Shen | ce26a45 | 2017-03-23 16:02:47 +0000 | [diff] [blame] | 131 | ; PPC64LE-NEXT: blr |
| 132 | %val = load atomic i32, i32* %ptr seq_cst, align 4 |
| 133 | ret i32 %val |
| 134 | } |
| 135 | |
| 136 | define i64 @test12(i64* %ptr) { |
| 137 | ; PPC64LE-LABEL: test12: |
| 138 | ; PPC64LE: # BB#0: |
| 139 | ; PPC64LE-NEXT: ld 3, 0(3) |
| 140 | ; PPC64LE-NEXT: blr |
| 141 | %val = load atomic i64, i64* %ptr unordered, align 8 |
| 142 | ret i64 %val |
| 143 | } |
| 144 | |
| 145 | define i64 @test13(i64* %ptr) { |
| 146 | ; PPC64LE-LABEL: test13: |
| 147 | ; PPC64LE: # BB#0: |
| 148 | ; PPC64LE-NEXT: ld 3, 0(3) |
| 149 | ; PPC64LE-NEXT: blr |
| 150 | %val = load atomic i64, i64* %ptr monotonic, align 8 |
| 151 | ret i64 %val |
| 152 | } |
| 153 | |
| 154 | define i64 @test14(i64* %ptr) { |
| 155 | ; PPC64LE-LABEL: test14: |
| 156 | ; PPC64LE: # BB#0: |
| 157 | ; PPC64LE-NEXT: ld 3, 0(3) |
Hiroshi Inoue | 7a08bb1 | 2017-06-15 16:51:28 +0000 | [diff] [blame^] | 158 | ; PPC64LE-NEXT: cmpd 7, 3, 3 |
Tim Shen | 3bef27c | 2017-05-16 20:18:06 +0000 | [diff] [blame] | 159 | ; PPC64LE-NEXT: bne- 7, .+4 |
| 160 | ; PPC64LE-NEXT: isync |
Tim Shen | ce26a45 | 2017-03-23 16:02:47 +0000 | [diff] [blame] | 161 | ; PPC64LE-NEXT: blr |
| 162 | %val = load atomic i64, i64* %ptr acquire, align 8 |
| 163 | ret i64 %val |
| 164 | } |
| 165 | |
| 166 | define i64 @test15(i64* %ptr) { |
| 167 | ; PPC64LE-LABEL: test15: |
| 168 | ; PPC64LE: # BB#0: |
| 169 | ; PPC64LE-NEXT: sync |
| 170 | ; PPC64LE-NEXT: ori 2, 2, 0 |
| 171 | ; PPC64LE-NEXT: ld 3, 0(3) |
Hiroshi Inoue | 7a08bb1 | 2017-06-15 16:51:28 +0000 | [diff] [blame^] | 172 | ; PPC64LE-NEXT: cmpd 7, 3, 3 |
Tim Shen | 3bef27c | 2017-05-16 20:18:06 +0000 | [diff] [blame] | 173 | ; PPC64LE-NEXT: bne- 7, .+4 |
| 174 | ; PPC64LE-NEXT: isync |
Tim Shen | ce26a45 | 2017-03-23 16:02:47 +0000 | [diff] [blame] | 175 | ; PPC64LE-NEXT: blr |
| 176 | %val = load atomic i64, i64* %ptr seq_cst, align 8 |
| 177 | ret i64 %val |
| 178 | } |
| 179 | |
| 180 | define void @test16(i8* %ptr, i8 %val) { |
| 181 | ; PPC64LE-LABEL: test16: |
| 182 | ; PPC64LE: # BB#0: |
| 183 | ; PPC64LE-NEXT: stb 4, 0(3) |
| 184 | ; PPC64LE-NEXT: blr |
| 185 | store atomic i8 %val, i8* %ptr unordered, align 1 |
| 186 | ret void |
| 187 | } |
| 188 | |
| 189 | define void @test17(i8* %ptr, i8 %val) { |
| 190 | ; PPC64LE-LABEL: test17: |
| 191 | ; PPC64LE: # BB#0: |
| 192 | ; PPC64LE-NEXT: stb 4, 0(3) |
| 193 | ; PPC64LE-NEXT: blr |
| 194 | store atomic i8 %val, i8* %ptr monotonic, align 1 |
| 195 | ret void |
| 196 | } |
| 197 | |
| 198 | define void @test18(i8* %ptr, i8 %val) { |
| 199 | ; PPC64LE-LABEL: test18: |
| 200 | ; PPC64LE: # BB#0: |
| 201 | ; PPC64LE-NEXT: lwsync |
| 202 | ; PPC64LE-NEXT: stb 4, 0(3) |
| 203 | ; PPC64LE-NEXT: blr |
| 204 | store atomic i8 %val, i8* %ptr release, align 1 |
| 205 | ret void |
| 206 | } |
| 207 | |
| 208 | define void @test19(i8* %ptr, i8 %val) { |
| 209 | ; PPC64LE-LABEL: test19: |
| 210 | ; PPC64LE: # BB#0: |
| 211 | ; PPC64LE-NEXT: sync |
| 212 | ; PPC64LE-NEXT: stb 4, 0(3) |
| 213 | ; PPC64LE-NEXT: blr |
| 214 | store atomic i8 %val, i8* %ptr seq_cst, align 1 |
| 215 | ret void |
| 216 | } |
| 217 | |
| 218 | define void @test20(i16* %ptr, i16 %val) { |
| 219 | ; PPC64LE-LABEL: test20: |
| 220 | ; PPC64LE: # BB#0: |
| 221 | ; PPC64LE-NEXT: sth 4, 0(3) |
| 222 | ; PPC64LE-NEXT: blr |
| 223 | store atomic i16 %val, i16* %ptr unordered, align 2 |
| 224 | ret void |
| 225 | } |
| 226 | |
| 227 | define void @test21(i16* %ptr, i16 %val) { |
| 228 | ; PPC64LE-LABEL: test21: |
| 229 | ; PPC64LE: # BB#0: |
| 230 | ; PPC64LE-NEXT: sth 4, 0(3) |
| 231 | ; PPC64LE-NEXT: blr |
| 232 | store atomic i16 %val, i16* %ptr monotonic, align 2 |
| 233 | ret void |
| 234 | } |
| 235 | |
| 236 | define void @test22(i16* %ptr, i16 %val) { |
| 237 | ; PPC64LE-LABEL: test22: |
| 238 | ; PPC64LE: # BB#0: |
| 239 | ; PPC64LE-NEXT: lwsync |
| 240 | ; PPC64LE-NEXT: sth 4, 0(3) |
| 241 | ; PPC64LE-NEXT: blr |
| 242 | store atomic i16 %val, i16* %ptr release, align 2 |
| 243 | ret void |
| 244 | } |
| 245 | |
| 246 | define void @test23(i16* %ptr, i16 %val) { |
| 247 | ; PPC64LE-LABEL: test23: |
| 248 | ; PPC64LE: # BB#0: |
| 249 | ; PPC64LE-NEXT: sync |
| 250 | ; PPC64LE-NEXT: sth 4, 0(3) |
| 251 | ; PPC64LE-NEXT: blr |
| 252 | store atomic i16 %val, i16* %ptr seq_cst, align 2 |
| 253 | ret void |
| 254 | } |
| 255 | |
| 256 | define void @test24(i32* %ptr, i32 %val) { |
| 257 | ; PPC64LE-LABEL: test24: |
| 258 | ; PPC64LE: # BB#0: |
| 259 | ; PPC64LE-NEXT: stw 4, 0(3) |
| 260 | ; PPC64LE-NEXT: blr |
| 261 | store atomic i32 %val, i32* %ptr unordered, align 4 |
| 262 | ret void |
| 263 | } |
| 264 | |
| 265 | define void @test25(i32* %ptr, i32 %val) { |
| 266 | ; PPC64LE-LABEL: test25: |
| 267 | ; PPC64LE: # BB#0: |
| 268 | ; PPC64LE-NEXT: stw 4, 0(3) |
| 269 | ; PPC64LE-NEXT: blr |
| 270 | store atomic i32 %val, i32* %ptr monotonic, align 4 |
| 271 | ret void |
| 272 | } |
| 273 | |
| 274 | define void @test26(i32* %ptr, i32 %val) { |
| 275 | ; PPC64LE-LABEL: test26: |
| 276 | ; PPC64LE: # BB#0: |
| 277 | ; PPC64LE-NEXT: lwsync |
| 278 | ; PPC64LE-NEXT: stw 4, 0(3) |
| 279 | ; PPC64LE-NEXT: blr |
| 280 | store atomic i32 %val, i32* %ptr release, align 4 |
| 281 | ret void |
| 282 | } |
| 283 | |
| 284 | define void @test27(i32* %ptr, i32 %val) { |
| 285 | ; PPC64LE-LABEL: test27: |
| 286 | ; PPC64LE: # BB#0: |
| 287 | ; PPC64LE-NEXT: sync |
| 288 | ; PPC64LE-NEXT: stw 4, 0(3) |
| 289 | ; PPC64LE-NEXT: blr |
| 290 | store atomic i32 %val, i32* %ptr seq_cst, align 4 |
| 291 | ret void |
| 292 | } |
| 293 | |
| 294 | define void @test28(i64* %ptr, i64 %val) { |
| 295 | ; PPC64LE-LABEL: test28: |
| 296 | ; PPC64LE: # BB#0: |
| 297 | ; PPC64LE-NEXT: std 4, 0(3) |
| 298 | ; PPC64LE-NEXT: blr |
| 299 | store atomic i64 %val, i64* %ptr unordered, align 8 |
| 300 | ret void |
| 301 | } |
| 302 | |
| 303 | define void @test29(i64* %ptr, i64 %val) { |
| 304 | ; PPC64LE-LABEL: test29: |
| 305 | ; PPC64LE: # BB#0: |
| 306 | ; PPC64LE-NEXT: std 4, 0(3) |
| 307 | ; PPC64LE-NEXT: blr |
| 308 | store atomic i64 %val, i64* %ptr monotonic, align 8 |
| 309 | ret void |
| 310 | } |
| 311 | |
| 312 | define void @test30(i64* %ptr, i64 %val) { |
| 313 | ; PPC64LE-LABEL: test30: |
| 314 | ; PPC64LE: # BB#0: |
| 315 | ; PPC64LE-NEXT: lwsync |
| 316 | ; PPC64LE-NEXT: std 4, 0(3) |
| 317 | ; PPC64LE-NEXT: blr |
| 318 | store atomic i64 %val, i64* %ptr release, align 8 |
| 319 | ret void |
| 320 | } |
| 321 | |
| 322 | define void @test31(i64* %ptr, i64 %val) { |
| 323 | ; PPC64LE-LABEL: test31: |
| 324 | ; PPC64LE: # BB#0: |
| 325 | ; PPC64LE-NEXT: sync |
| 326 | ; PPC64LE-NEXT: std 4, 0(3) |
| 327 | ; PPC64LE-NEXT: blr |
| 328 | store atomic i64 %val, i64* %ptr seq_cst, align 8 |
| 329 | ret void |
| 330 | } |
| 331 | |
| 332 | define void @test32() { |
| 333 | ; PPC64LE-LABEL: test32: |
| 334 | ; PPC64LE: # BB#0: |
| 335 | ; PPC64LE-NEXT: lwsync |
| 336 | ; PPC64LE-NEXT: blr |
| 337 | fence acquire |
| 338 | ret void |
| 339 | } |
| 340 | |
| 341 | define void @test33() { |
| 342 | ; PPC64LE-LABEL: test33: |
| 343 | ; PPC64LE: # BB#0: |
| 344 | ; PPC64LE-NEXT: lwsync |
| 345 | ; PPC64LE-NEXT: blr |
| 346 | fence release |
| 347 | ret void |
| 348 | } |
| 349 | |
| 350 | define void @test34() { |
| 351 | ; PPC64LE-LABEL: test34: |
| 352 | ; PPC64LE: # BB#0: |
| 353 | ; PPC64LE-NEXT: lwsync |
| 354 | ; PPC64LE-NEXT: blr |
| 355 | fence acq_rel |
| 356 | ret void |
| 357 | } |
| 358 | |
| 359 | define void @test35() { |
| 360 | ; PPC64LE-LABEL: test35: |
| 361 | ; PPC64LE: # BB#0: |
| 362 | ; PPC64LE-NEXT: sync |
| 363 | ; PPC64LE-NEXT: blr |
| 364 | fence seq_cst |
| 365 | ret void |
| 366 | } |
| 367 | |
| 368 | define void @test36() { |
| 369 | ; PPC64LE-LABEL: test36: |
| 370 | ; PPC64LE: # BB#0: |
| 371 | ; PPC64LE-NEXT: lwsync |
| 372 | ; PPC64LE-NEXT: blr |
| 373 | fence singlethread acquire |
| 374 | ret void |
| 375 | } |
| 376 | |
| 377 | define void @test37() { |
| 378 | ; PPC64LE-LABEL: test37: |
| 379 | ; PPC64LE: # BB#0: |
| 380 | ; PPC64LE-NEXT: lwsync |
| 381 | ; PPC64LE-NEXT: blr |
| 382 | fence singlethread release |
| 383 | ret void |
| 384 | } |
| 385 | |
| 386 | define void @test38() { |
| 387 | ; PPC64LE-LABEL: test38: |
| 388 | ; PPC64LE: # BB#0: |
| 389 | ; PPC64LE-NEXT: lwsync |
| 390 | ; PPC64LE-NEXT: blr |
| 391 | fence singlethread acq_rel |
| 392 | ret void |
| 393 | } |
| 394 | |
| 395 | define void @test39() { |
| 396 | ; PPC64LE-LABEL: test39: |
| 397 | ; PPC64LE: # BB#0: |
| 398 | ; PPC64LE-NEXT: sync |
| 399 | ; PPC64LE-NEXT: blr |
| 400 | fence singlethread seq_cst |
| 401 | ret void |
| 402 | } |
| 403 | |
| 404 | define void @test40(i8* %ptr, i8 %cmp, i8 %val) { |
| 405 | ; PPC64LE-LABEL: test40: |
| 406 | ; PPC64LE: # BB#0: |
| 407 | ; PPC64LE-NEXT: b .LBB40_2 |
| 408 | ; PPC64LE-NEXT: .p2align 5 |
| 409 | ; PPC64LE-NEXT: .LBB40_1: |
| 410 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 411 | ; PPC64LE-NEXT: beqlr 0 |
| 412 | ; PPC64LE-NEXT: b .LBB40_2 |
| 413 | ; PPC64LE-NEXT: .LBB40_2: |
| 414 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 415 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 416 | ; PPC64LE-NEXT: beq 0, .LBB40_1 |
| 417 | ; PPC64LE-NEXT: # BB#3: |
| 418 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 419 | ; PPC64LE-NEXT: blr |
| 420 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic |
| 421 | ret void |
| 422 | } |
| 423 | |
| 424 | define void @test41(i8* %ptr, i8 %cmp, i8 %val) { |
| 425 | ; PPC64LE-LABEL: test41: |
| 426 | ; PPC64LE: # BB#0: |
| 427 | ; PPC64LE-NEXT: .LBB41_1: |
| 428 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 429 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 430 | ; PPC64LE-NEXT: bne 0, .LBB41_4 |
| 431 | ; PPC64LE-NEXT: # BB#2: |
| 432 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 433 | ; PPC64LE-NEXT: bne 0, .LBB41_1 |
| 434 | ; PPC64LE-NEXT: # BB#3: |
| 435 | ; PPC64LE-NEXT: lwsync |
| 436 | ; PPC64LE-NEXT: blr |
| 437 | ; PPC64LE-NEXT: .LBB41_4: |
| 438 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 439 | ; PPC64LE-NEXT: lwsync |
| 440 | ; PPC64LE-NEXT: blr |
| 441 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic |
| 442 | ret void |
| 443 | } |
| 444 | |
| 445 | define void @test42(i8* %ptr, i8 %cmp, i8 %val) { |
| 446 | ; PPC64LE-LABEL: test42: |
| 447 | ; PPC64LE: # BB#0: |
| 448 | ; PPC64LE-NEXT: .LBB42_1: |
| 449 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 450 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 451 | ; PPC64LE-NEXT: bne 0, .LBB42_4 |
| 452 | ; PPC64LE-NEXT: # BB#2: |
| 453 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 454 | ; PPC64LE-NEXT: bne 0, .LBB42_1 |
| 455 | ; PPC64LE-NEXT: # BB#3: |
| 456 | ; PPC64LE-NEXT: lwsync |
| 457 | ; PPC64LE-NEXT: blr |
| 458 | ; PPC64LE-NEXT: .LBB42_4: |
| 459 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 460 | ; PPC64LE-NEXT: lwsync |
| 461 | ; PPC64LE-NEXT: blr |
| 462 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire |
| 463 | ret void |
| 464 | } |
| 465 | |
| 466 | define void @test43(i8* %ptr, i8 %cmp, i8 %val) { |
| 467 | ; PPC64LE-LABEL: test43: |
| 468 | ; PPC64LE: # BB#0: |
| 469 | ; PPC64LE-NEXT: lwsync |
| 470 | ; PPC64LE-NEXT: b .LBB43_2 |
| 471 | ; PPC64LE-NEXT: .p2align 5 |
| 472 | ; PPC64LE-NEXT: .LBB43_1: |
| 473 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 474 | ; PPC64LE-NEXT: beqlr 0 |
| 475 | ; PPC64LE-NEXT: b .LBB43_2 |
| 476 | ; PPC64LE-NEXT: .LBB43_2: |
| 477 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 478 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 479 | ; PPC64LE-NEXT: beq 0, .LBB43_1 |
| 480 | ; PPC64LE-NEXT: # BB#3: |
| 481 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 482 | ; PPC64LE-NEXT: blr |
| 483 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic |
| 484 | ret void |
| 485 | } |
| 486 | |
| 487 | define void @test44(i8* %ptr, i8 %cmp, i8 %val) { |
| 488 | ; PPC64LE-LABEL: test44: |
| 489 | ; PPC64LE: # BB#0: |
| 490 | ; PPC64LE-NEXT: lwsync |
| 491 | ; PPC64LE-NEXT: b .LBB44_2 |
| 492 | ; PPC64LE-NEXT: .p2align 5 |
| 493 | ; PPC64LE-NEXT: .LBB44_1: |
| 494 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 495 | ; PPC64LE-NEXT: beqlr 0 |
| 496 | ; PPC64LE-NEXT: b .LBB44_2 |
| 497 | ; PPC64LE-NEXT: .LBB44_2: |
| 498 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 499 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 500 | ; PPC64LE-NEXT: beq 0, .LBB44_1 |
| 501 | ; PPC64LE-NEXT: # BB#3: |
| 502 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 503 | ; PPC64LE-NEXT: blr |
| 504 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire |
| 505 | ret void |
| 506 | } |
| 507 | |
| 508 | define void @test45(i8* %ptr, i8 %cmp, i8 %val) { |
| 509 | ; PPC64LE-LABEL: test45: |
| 510 | ; PPC64LE: # BB#0: |
| 511 | ; PPC64LE-NEXT: lwsync |
| 512 | ; PPC64LE-NEXT: .LBB45_1: |
| 513 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 514 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 515 | ; PPC64LE-NEXT: bne 0, .LBB45_4 |
| 516 | ; PPC64LE-NEXT: # BB#2: |
| 517 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 518 | ; PPC64LE-NEXT: bne 0, .LBB45_1 |
| 519 | ; PPC64LE-NEXT: # BB#3: |
| 520 | ; PPC64LE-NEXT: lwsync |
| 521 | ; PPC64LE-NEXT: blr |
| 522 | ; PPC64LE-NEXT: .LBB45_4: |
| 523 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 524 | ; PPC64LE-NEXT: lwsync |
| 525 | ; PPC64LE-NEXT: blr |
| 526 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic |
| 527 | ret void |
| 528 | } |
| 529 | |
| 530 | define void @test46(i8* %ptr, i8 %cmp, i8 %val) { |
| 531 | ; PPC64LE-LABEL: test46: |
| 532 | ; PPC64LE: # BB#0: |
| 533 | ; PPC64LE-NEXT: lwsync |
| 534 | ; PPC64LE-NEXT: .LBB46_1: |
| 535 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 536 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 537 | ; PPC64LE-NEXT: bne 0, .LBB46_4 |
| 538 | ; PPC64LE-NEXT: # BB#2: |
| 539 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 540 | ; PPC64LE-NEXT: bne 0, .LBB46_1 |
| 541 | ; PPC64LE-NEXT: # BB#3: |
| 542 | ; PPC64LE-NEXT: lwsync |
| 543 | ; PPC64LE-NEXT: blr |
| 544 | ; PPC64LE-NEXT: .LBB46_4: |
| 545 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 546 | ; PPC64LE-NEXT: lwsync |
| 547 | ; PPC64LE-NEXT: blr |
| 548 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire |
| 549 | ret void |
| 550 | } |
| 551 | |
| 552 | define void @test47(i8* %ptr, i8 %cmp, i8 %val) { |
| 553 | ; PPC64LE-LABEL: test47: |
| 554 | ; PPC64LE: # BB#0: |
| 555 | ; PPC64LE-NEXT: sync |
| 556 | ; PPC64LE-NEXT: .LBB47_1: |
| 557 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 558 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 559 | ; PPC64LE-NEXT: bne 0, .LBB47_4 |
| 560 | ; PPC64LE-NEXT: # BB#2: |
| 561 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 562 | ; PPC64LE-NEXT: bne 0, .LBB47_1 |
| 563 | ; PPC64LE-NEXT: # BB#3: |
| 564 | ; PPC64LE-NEXT: lwsync |
| 565 | ; PPC64LE-NEXT: blr |
| 566 | ; PPC64LE-NEXT: .LBB47_4: |
| 567 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 568 | ; PPC64LE-NEXT: lwsync |
| 569 | ; PPC64LE-NEXT: blr |
| 570 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic |
| 571 | ret void |
| 572 | } |
| 573 | |
| 574 | define void @test48(i8* %ptr, i8 %cmp, i8 %val) { |
| 575 | ; PPC64LE-LABEL: test48: |
| 576 | ; PPC64LE: # BB#0: |
| 577 | ; PPC64LE-NEXT: sync |
| 578 | ; PPC64LE-NEXT: .LBB48_1: |
| 579 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 580 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 581 | ; PPC64LE-NEXT: bne 0, .LBB48_4 |
| 582 | ; PPC64LE-NEXT: # BB#2: |
| 583 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 584 | ; PPC64LE-NEXT: bne 0, .LBB48_1 |
| 585 | ; PPC64LE-NEXT: # BB#3: |
| 586 | ; PPC64LE-NEXT: lwsync |
| 587 | ; PPC64LE-NEXT: blr |
| 588 | ; PPC64LE-NEXT: .LBB48_4: |
| 589 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 590 | ; PPC64LE-NEXT: lwsync |
| 591 | ; PPC64LE-NEXT: blr |
| 592 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire |
| 593 | ret void |
| 594 | } |
| 595 | |
| 596 | define void @test49(i8* %ptr, i8 %cmp, i8 %val) { |
| 597 | ; PPC64LE-LABEL: test49: |
| 598 | ; PPC64LE: # BB#0: |
| 599 | ; PPC64LE-NEXT: sync |
| 600 | ; PPC64LE-NEXT: .LBB49_1: |
| 601 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 602 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 603 | ; PPC64LE-NEXT: bne 0, .LBB49_4 |
| 604 | ; PPC64LE-NEXT: # BB#2: |
| 605 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 606 | ; PPC64LE-NEXT: bne 0, .LBB49_1 |
| 607 | ; PPC64LE-NEXT: # BB#3: |
| 608 | ; PPC64LE-NEXT: lwsync |
| 609 | ; PPC64LE-NEXT: blr |
| 610 | ; PPC64LE-NEXT: .LBB49_4: |
| 611 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 612 | ; PPC64LE-NEXT: lwsync |
| 613 | ; PPC64LE-NEXT: blr |
| 614 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst |
| 615 | ret void |
| 616 | } |
| 617 | |
| 618 | define void @test50(i16* %ptr, i16 %cmp, i16 %val) { |
| 619 | ; PPC64LE-LABEL: test50: |
| 620 | ; PPC64LE: # BB#0: |
| 621 | ; PPC64LE-NEXT: b .LBB50_2 |
| 622 | ; PPC64LE-NEXT: .p2align 5 |
| 623 | ; PPC64LE-NEXT: .LBB50_1: |
| 624 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 625 | ; PPC64LE-NEXT: beqlr 0 |
| 626 | ; PPC64LE-NEXT: b .LBB50_2 |
| 627 | ; PPC64LE-NEXT: .LBB50_2: |
| 628 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 629 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 630 | ; PPC64LE-NEXT: beq 0, .LBB50_1 |
| 631 | ; PPC64LE-NEXT: # BB#3: |
| 632 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 633 | ; PPC64LE-NEXT: blr |
| 634 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic |
| 635 | ret void |
| 636 | } |
| 637 | |
| 638 | define void @test51(i16* %ptr, i16 %cmp, i16 %val) { |
| 639 | ; PPC64LE-LABEL: test51: |
| 640 | ; PPC64LE: # BB#0: |
| 641 | ; PPC64LE-NEXT: .LBB51_1: |
| 642 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 643 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 644 | ; PPC64LE-NEXT: bne 0, .LBB51_4 |
| 645 | ; PPC64LE-NEXT: # BB#2: |
| 646 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 647 | ; PPC64LE-NEXT: bne 0, .LBB51_1 |
| 648 | ; PPC64LE-NEXT: # BB#3: |
| 649 | ; PPC64LE-NEXT: lwsync |
| 650 | ; PPC64LE-NEXT: blr |
| 651 | ; PPC64LE-NEXT: .LBB51_4: |
| 652 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 653 | ; PPC64LE-NEXT: lwsync |
| 654 | ; PPC64LE-NEXT: blr |
| 655 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic |
| 656 | ret void |
| 657 | } |
| 658 | |
| 659 | define void @test52(i16* %ptr, i16 %cmp, i16 %val) { |
| 660 | ; PPC64LE-LABEL: test52: |
| 661 | ; PPC64LE: # BB#0: |
| 662 | ; PPC64LE-NEXT: .LBB52_1: |
| 663 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 664 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 665 | ; PPC64LE-NEXT: bne 0, .LBB52_4 |
| 666 | ; PPC64LE-NEXT: # BB#2: |
| 667 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 668 | ; PPC64LE-NEXT: bne 0, .LBB52_1 |
| 669 | ; PPC64LE-NEXT: # BB#3: |
| 670 | ; PPC64LE-NEXT: lwsync |
| 671 | ; PPC64LE-NEXT: blr |
| 672 | ; PPC64LE-NEXT: .LBB52_4: |
| 673 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 674 | ; PPC64LE-NEXT: lwsync |
| 675 | ; PPC64LE-NEXT: blr |
| 676 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire |
| 677 | ret void |
| 678 | } |
| 679 | |
| 680 | define void @test53(i16* %ptr, i16 %cmp, i16 %val) { |
| 681 | ; PPC64LE-LABEL: test53: |
| 682 | ; PPC64LE: # BB#0: |
| 683 | ; PPC64LE-NEXT: lwsync |
| 684 | ; PPC64LE-NEXT: b .LBB53_2 |
| 685 | ; PPC64LE-NEXT: .p2align 5 |
| 686 | ; PPC64LE-NEXT: .LBB53_1: |
| 687 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 688 | ; PPC64LE-NEXT: beqlr 0 |
| 689 | ; PPC64LE-NEXT: b .LBB53_2 |
| 690 | ; PPC64LE-NEXT: .LBB53_2: |
| 691 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 692 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 693 | ; PPC64LE-NEXT: beq 0, .LBB53_1 |
| 694 | ; PPC64LE-NEXT: # BB#3: |
| 695 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 696 | ; PPC64LE-NEXT: blr |
| 697 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic |
| 698 | ret void |
| 699 | } |
| 700 | |
| 701 | define void @test54(i16* %ptr, i16 %cmp, i16 %val) { |
| 702 | ; PPC64LE-LABEL: test54: |
| 703 | ; PPC64LE: # BB#0: |
| 704 | ; PPC64LE-NEXT: lwsync |
| 705 | ; PPC64LE-NEXT: b .LBB54_2 |
| 706 | ; PPC64LE-NEXT: .p2align 5 |
| 707 | ; PPC64LE-NEXT: .LBB54_1: |
| 708 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 709 | ; PPC64LE-NEXT: beqlr 0 |
| 710 | ; PPC64LE-NEXT: b .LBB54_2 |
| 711 | ; PPC64LE-NEXT: .LBB54_2: |
| 712 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 713 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 714 | ; PPC64LE-NEXT: beq 0, .LBB54_1 |
| 715 | ; PPC64LE-NEXT: # BB#3: |
| 716 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 717 | ; PPC64LE-NEXT: blr |
| 718 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire |
| 719 | ret void |
| 720 | } |
| 721 | |
| 722 | define void @test55(i16* %ptr, i16 %cmp, i16 %val) { |
| 723 | ; PPC64LE-LABEL: test55: |
| 724 | ; PPC64LE: # BB#0: |
| 725 | ; PPC64LE-NEXT: lwsync |
| 726 | ; PPC64LE-NEXT: .LBB55_1: |
| 727 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 728 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 729 | ; PPC64LE-NEXT: bne 0, .LBB55_4 |
| 730 | ; PPC64LE-NEXT: # BB#2: |
| 731 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 732 | ; PPC64LE-NEXT: bne 0, .LBB55_1 |
| 733 | ; PPC64LE-NEXT: # BB#3: |
| 734 | ; PPC64LE-NEXT: lwsync |
| 735 | ; PPC64LE-NEXT: blr |
| 736 | ; PPC64LE-NEXT: .LBB55_4: |
| 737 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 738 | ; PPC64LE-NEXT: lwsync |
| 739 | ; PPC64LE-NEXT: blr |
| 740 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic |
| 741 | ret void |
| 742 | } |
| 743 | |
| 744 | define void @test56(i16* %ptr, i16 %cmp, i16 %val) { |
| 745 | ; PPC64LE-LABEL: test56: |
| 746 | ; PPC64LE: # BB#0: |
| 747 | ; PPC64LE-NEXT: lwsync |
| 748 | ; PPC64LE-NEXT: .LBB56_1: |
| 749 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 750 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 751 | ; PPC64LE-NEXT: bne 0, .LBB56_4 |
| 752 | ; PPC64LE-NEXT: # BB#2: |
| 753 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 754 | ; PPC64LE-NEXT: bne 0, .LBB56_1 |
| 755 | ; PPC64LE-NEXT: # BB#3: |
| 756 | ; PPC64LE-NEXT: lwsync |
| 757 | ; PPC64LE-NEXT: blr |
| 758 | ; PPC64LE-NEXT: .LBB56_4: |
| 759 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 760 | ; PPC64LE-NEXT: lwsync |
| 761 | ; PPC64LE-NEXT: blr |
| 762 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire |
| 763 | ret void |
| 764 | } |
| 765 | |
| 766 | define void @test57(i16* %ptr, i16 %cmp, i16 %val) { |
| 767 | ; PPC64LE-LABEL: test57: |
| 768 | ; PPC64LE: # BB#0: |
| 769 | ; PPC64LE-NEXT: sync |
| 770 | ; PPC64LE-NEXT: .LBB57_1: |
| 771 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 772 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 773 | ; PPC64LE-NEXT: bne 0, .LBB57_4 |
| 774 | ; PPC64LE-NEXT: # BB#2: |
| 775 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 776 | ; PPC64LE-NEXT: bne 0, .LBB57_1 |
| 777 | ; PPC64LE-NEXT: # BB#3: |
| 778 | ; PPC64LE-NEXT: lwsync |
| 779 | ; PPC64LE-NEXT: blr |
| 780 | ; PPC64LE-NEXT: .LBB57_4: |
| 781 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 782 | ; PPC64LE-NEXT: lwsync |
| 783 | ; PPC64LE-NEXT: blr |
| 784 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic |
| 785 | ret void |
| 786 | } |
| 787 | |
| 788 | define void @test58(i16* %ptr, i16 %cmp, i16 %val) { |
| 789 | ; PPC64LE-LABEL: test58: |
| 790 | ; PPC64LE: # BB#0: |
| 791 | ; PPC64LE-NEXT: sync |
| 792 | ; PPC64LE-NEXT: .LBB58_1: |
| 793 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 794 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 795 | ; PPC64LE-NEXT: bne 0, .LBB58_4 |
| 796 | ; PPC64LE-NEXT: # BB#2: |
| 797 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 798 | ; PPC64LE-NEXT: bne 0, .LBB58_1 |
| 799 | ; PPC64LE-NEXT: # BB#3: |
| 800 | ; PPC64LE-NEXT: lwsync |
| 801 | ; PPC64LE-NEXT: blr |
| 802 | ; PPC64LE-NEXT: .LBB58_4: |
| 803 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 804 | ; PPC64LE-NEXT: lwsync |
| 805 | ; PPC64LE-NEXT: blr |
| 806 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire |
| 807 | ret void |
| 808 | } |
| 809 | |
| 810 | define void @test59(i16* %ptr, i16 %cmp, i16 %val) { |
| 811 | ; PPC64LE-LABEL: test59: |
| 812 | ; PPC64LE: # BB#0: |
| 813 | ; PPC64LE-NEXT: sync |
| 814 | ; PPC64LE-NEXT: .LBB59_1: |
| 815 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 816 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 817 | ; PPC64LE-NEXT: bne 0, .LBB59_4 |
| 818 | ; PPC64LE-NEXT: # BB#2: |
| 819 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 820 | ; PPC64LE-NEXT: bne 0, .LBB59_1 |
| 821 | ; PPC64LE-NEXT: # BB#3: |
| 822 | ; PPC64LE-NEXT: lwsync |
| 823 | ; PPC64LE-NEXT: blr |
| 824 | ; PPC64LE-NEXT: .LBB59_4: |
| 825 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 826 | ; PPC64LE-NEXT: lwsync |
| 827 | ; PPC64LE-NEXT: blr |
| 828 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst |
| 829 | ret void |
| 830 | } |
| 831 | |
| 832 | define void @test60(i32* %ptr, i32 %cmp, i32 %val) { |
| 833 | ; PPC64LE-LABEL: test60: |
| 834 | ; PPC64LE: # BB#0: |
| 835 | ; PPC64LE-NEXT: b .LBB60_2 |
| 836 | ; PPC64LE-NEXT: .p2align 5 |
| 837 | ; PPC64LE-NEXT: .LBB60_1: |
| 838 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 839 | ; PPC64LE-NEXT: beqlr 0 |
| 840 | ; PPC64LE-NEXT: b .LBB60_2 |
| 841 | ; PPC64LE-NEXT: .LBB60_2: |
| 842 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 843 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 844 | ; PPC64LE-NEXT: beq 0, .LBB60_1 |
| 845 | ; PPC64LE-NEXT: # BB#3: |
| 846 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 847 | ; PPC64LE-NEXT: blr |
| 848 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic |
| 849 | ret void |
| 850 | } |
| 851 | |
| 852 | define void @test61(i32* %ptr, i32 %cmp, i32 %val) { |
| 853 | ; PPC64LE-LABEL: test61: |
| 854 | ; PPC64LE: # BB#0: |
| 855 | ; PPC64LE-NEXT: .LBB61_1: |
| 856 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 857 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 858 | ; PPC64LE-NEXT: bne 0, .LBB61_4 |
| 859 | ; PPC64LE-NEXT: # BB#2: |
| 860 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 861 | ; PPC64LE-NEXT: bne 0, .LBB61_1 |
| 862 | ; PPC64LE-NEXT: # BB#3: |
| 863 | ; PPC64LE-NEXT: lwsync |
| 864 | ; PPC64LE-NEXT: blr |
| 865 | ; PPC64LE-NEXT: .LBB61_4: |
| 866 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 867 | ; PPC64LE-NEXT: lwsync |
| 868 | ; PPC64LE-NEXT: blr |
| 869 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic |
| 870 | ret void |
| 871 | } |
| 872 | |
| 873 | define void @test62(i32* %ptr, i32 %cmp, i32 %val) { |
| 874 | ; PPC64LE-LABEL: test62: |
| 875 | ; PPC64LE: # BB#0: |
| 876 | ; PPC64LE-NEXT: .LBB62_1: |
| 877 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 878 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 879 | ; PPC64LE-NEXT: bne 0, .LBB62_4 |
| 880 | ; PPC64LE-NEXT: # BB#2: |
| 881 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 882 | ; PPC64LE-NEXT: bne 0, .LBB62_1 |
| 883 | ; PPC64LE-NEXT: # BB#3: |
| 884 | ; PPC64LE-NEXT: lwsync |
| 885 | ; PPC64LE-NEXT: blr |
| 886 | ; PPC64LE-NEXT: .LBB62_4: |
| 887 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 888 | ; PPC64LE-NEXT: lwsync |
| 889 | ; PPC64LE-NEXT: blr |
| 890 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire |
| 891 | ret void |
| 892 | } |
| 893 | |
| 894 | define void @test63(i32* %ptr, i32 %cmp, i32 %val) { |
| 895 | ; PPC64LE-LABEL: test63: |
| 896 | ; PPC64LE: # BB#0: |
| 897 | ; PPC64LE-NEXT: lwsync |
| 898 | ; PPC64LE-NEXT: b .LBB63_2 |
| 899 | ; PPC64LE-NEXT: .p2align 5 |
| 900 | ; PPC64LE-NEXT: .LBB63_1: |
| 901 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 902 | ; PPC64LE-NEXT: beqlr 0 |
| 903 | ; PPC64LE-NEXT: b .LBB63_2 |
| 904 | ; PPC64LE-NEXT: .LBB63_2: |
| 905 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 906 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 907 | ; PPC64LE-NEXT: beq 0, .LBB63_1 |
| 908 | ; PPC64LE-NEXT: # BB#3: |
| 909 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 910 | ; PPC64LE-NEXT: blr |
| 911 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic |
| 912 | ret void |
| 913 | } |
| 914 | |
| 915 | define void @test64(i32* %ptr, i32 %cmp, i32 %val) { |
| 916 | ; PPC64LE-LABEL: test64: |
| 917 | ; PPC64LE: # BB#0: |
| 918 | ; PPC64LE-NEXT: lwsync |
| 919 | ; PPC64LE-NEXT: b .LBB64_2 |
| 920 | ; PPC64LE-NEXT: .p2align 5 |
| 921 | ; PPC64LE-NEXT: .LBB64_1: |
| 922 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 923 | ; PPC64LE-NEXT: beqlr 0 |
| 924 | ; PPC64LE-NEXT: b .LBB64_2 |
| 925 | ; PPC64LE-NEXT: .LBB64_2: |
| 926 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 927 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 928 | ; PPC64LE-NEXT: beq 0, .LBB64_1 |
| 929 | ; PPC64LE-NEXT: # BB#3: |
| 930 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 931 | ; PPC64LE-NEXT: blr |
| 932 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire |
| 933 | ret void |
| 934 | } |
| 935 | |
| 936 | define void @test65(i32* %ptr, i32 %cmp, i32 %val) { |
| 937 | ; PPC64LE-LABEL: test65: |
| 938 | ; PPC64LE: # BB#0: |
| 939 | ; PPC64LE-NEXT: lwsync |
| 940 | ; PPC64LE-NEXT: .LBB65_1: |
| 941 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 942 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 943 | ; PPC64LE-NEXT: bne 0, .LBB65_4 |
| 944 | ; PPC64LE-NEXT: # BB#2: |
| 945 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 946 | ; PPC64LE-NEXT: bne 0, .LBB65_1 |
| 947 | ; PPC64LE-NEXT: # BB#3: |
| 948 | ; PPC64LE-NEXT: lwsync |
| 949 | ; PPC64LE-NEXT: blr |
| 950 | ; PPC64LE-NEXT: .LBB65_4: |
| 951 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 952 | ; PPC64LE-NEXT: lwsync |
| 953 | ; PPC64LE-NEXT: blr |
| 954 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic |
| 955 | ret void |
| 956 | } |
| 957 | |
| 958 | define void @test66(i32* %ptr, i32 %cmp, i32 %val) { |
| 959 | ; PPC64LE-LABEL: test66: |
| 960 | ; PPC64LE: # BB#0: |
| 961 | ; PPC64LE-NEXT: lwsync |
| 962 | ; PPC64LE-NEXT: .LBB66_1: |
| 963 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 964 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 965 | ; PPC64LE-NEXT: bne 0, .LBB66_4 |
| 966 | ; PPC64LE-NEXT: # BB#2: |
| 967 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 968 | ; PPC64LE-NEXT: bne 0, .LBB66_1 |
| 969 | ; PPC64LE-NEXT: # BB#3: |
| 970 | ; PPC64LE-NEXT: lwsync |
| 971 | ; PPC64LE-NEXT: blr |
| 972 | ; PPC64LE-NEXT: .LBB66_4: |
| 973 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 974 | ; PPC64LE-NEXT: lwsync |
| 975 | ; PPC64LE-NEXT: blr |
| 976 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire |
| 977 | ret void |
| 978 | } |
| 979 | |
| 980 | define void @test67(i32* %ptr, i32 %cmp, i32 %val) { |
| 981 | ; PPC64LE-LABEL: test67: |
| 982 | ; PPC64LE: # BB#0: |
| 983 | ; PPC64LE-NEXT: sync |
| 984 | ; PPC64LE-NEXT: .LBB67_1: |
| 985 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 986 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 987 | ; PPC64LE-NEXT: bne 0, .LBB67_4 |
| 988 | ; PPC64LE-NEXT: # BB#2: |
| 989 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 990 | ; PPC64LE-NEXT: bne 0, .LBB67_1 |
| 991 | ; PPC64LE-NEXT: # BB#3: |
| 992 | ; PPC64LE-NEXT: lwsync |
| 993 | ; PPC64LE-NEXT: blr |
| 994 | ; PPC64LE-NEXT: .LBB67_4: |
| 995 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 996 | ; PPC64LE-NEXT: lwsync |
| 997 | ; PPC64LE-NEXT: blr |
| 998 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic |
| 999 | ret void |
| 1000 | } |
| 1001 | |
| 1002 | define void @test68(i32* %ptr, i32 %cmp, i32 %val) { |
| 1003 | ; PPC64LE-LABEL: test68: |
| 1004 | ; PPC64LE: # BB#0: |
| 1005 | ; PPC64LE-NEXT: sync |
| 1006 | ; PPC64LE-NEXT: .LBB68_1: |
| 1007 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 1008 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1009 | ; PPC64LE-NEXT: bne 0, .LBB68_4 |
| 1010 | ; PPC64LE-NEXT: # BB#2: |
| 1011 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 1012 | ; PPC64LE-NEXT: bne 0, .LBB68_1 |
| 1013 | ; PPC64LE-NEXT: # BB#3: |
| 1014 | ; PPC64LE-NEXT: lwsync |
| 1015 | ; PPC64LE-NEXT: blr |
| 1016 | ; PPC64LE-NEXT: .LBB68_4: |
| 1017 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 1018 | ; PPC64LE-NEXT: lwsync |
| 1019 | ; PPC64LE-NEXT: blr |
| 1020 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire |
| 1021 | ret void |
| 1022 | } |
| 1023 | |
| 1024 | define void @test69(i32* %ptr, i32 %cmp, i32 %val) { |
| 1025 | ; PPC64LE-LABEL: test69: |
| 1026 | ; PPC64LE: # BB#0: |
| 1027 | ; PPC64LE-NEXT: sync |
| 1028 | ; PPC64LE-NEXT: .LBB69_1: |
| 1029 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 1030 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1031 | ; PPC64LE-NEXT: bne 0, .LBB69_4 |
| 1032 | ; PPC64LE-NEXT: # BB#2: |
| 1033 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 1034 | ; PPC64LE-NEXT: bne 0, .LBB69_1 |
| 1035 | ; PPC64LE-NEXT: # BB#3: |
| 1036 | ; PPC64LE-NEXT: lwsync |
| 1037 | ; PPC64LE-NEXT: blr |
| 1038 | ; PPC64LE-NEXT: .LBB69_4: |
| 1039 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 1040 | ; PPC64LE-NEXT: lwsync |
| 1041 | ; PPC64LE-NEXT: blr |
| 1042 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst |
| 1043 | ret void |
| 1044 | } |
| 1045 | |
| 1046 | define void @test70(i64* %ptr, i64 %cmp, i64 %val) { |
| 1047 | ; PPC64LE-LABEL: test70: |
| 1048 | ; PPC64LE: # BB#0: |
| 1049 | ; PPC64LE-NEXT: b .LBB70_2 |
| 1050 | ; PPC64LE-NEXT: .p2align 5 |
| 1051 | ; PPC64LE-NEXT: .LBB70_1: |
| 1052 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1053 | ; PPC64LE-NEXT: beqlr 0 |
| 1054 | ; PPC64LE-NEXT: b .LBB70_2 |
| 1055 | ; PPC64LE-NEXT: .LBB70_2: |
| 1056 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1057 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1058 | ; PPC64LE-NEXT: beq 0, .LBB70_1 |
| 1059 | ; PPC64LE-NEXT: # BB#3: |
| 1060 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1061 | ; PPC64LE-NEXT: blr |
| 1062 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic |
| 1063 | ret void |
| 1064 | } |
| 1065 | |
| 1066 | define void @test71(i64* %ptr, i64 %cmp, i64 %val) { |
| 1067 | ; PPC64LE-LABEL: test71: |
| 1068 | ; PPC64LE: # BB#0: |
| 1069 | ; PPC64LE-NEXT: .LBB71_1: |
| 1070 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1071 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1072 | ; PPC64LE-NEXT: bne 0, .LBB71_4 |
| 1073 | ; PPC64LE-NEXT: # BB#2: |
| 1074 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1075 | ; PPC64LE-NEXT: bne 0, .LBB71_1 |
| 1076 | ; PPC64LE-NEXT: # BB#3: |
| 1077 | ; PPC64LE-NEXT: lwsync |
| 1078 | ; PPC64LE-NEXT: blr |
| 1079 | ; PPC64LE-NEXT: .LBB71_4: |
| 1080 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1081 | ; PPC64LE-NEXT: lwsync |
| 1082 | ; PPC64LE-NEXT: blr |
| 1083 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic |
| 1084 | ret void |
| 1085 | } |
| 1086 | |
| 1087 | define void @test72(i64* %ptr, i64 %cmp, i64 %val) { |
| 1088 | ; PPC64LE-LABEL: test72: |
| 1089 | ; PPC64LE: # BB#0: |
| 1090 | ; PPC64LE-NEXT: .LBB72_1: |
| 1091 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1092 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1093 | ; PPC64LE-NEXT: bne 0, .LBB72_4 |
| 1094 | ; PPC64LE-NEXT: # BB#2: |
| 1095 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1096 | ; PPC64LE-NEXT: bne 0, .LBB72_1 |
| 1097 | ; PPC64LE-NEXT: # BB#3: |
| 1098 | ; PPC64LE-NEXT: lwsync |
| 1099 | ; PPC64LE-NEXT: blr |
| 1100 | ; PPC64LE-NEXT: .LBB72_4: |
| 1101 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1102 | ; PPC64LE-NEXT: lwsync |
| 1103 | ; PPC64LE-NEXT: blr |
| 1104 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire |
| 1105 | ret void |
| 1106 | } |
| 1107 | |
| 1108 | define void @test73(i64* %ptr, i64 %cmp, i64 %val) { |
| 1109 | ; PPC64LE-LABEL: test73: |
| 1110 | ; PPC64LE: # BB#0: |
| 1111 | ; PPC64LE-NEXT: lwsync |
| 1112 | ; PPC64LE-NEXT: b .LBB73_2 |
| 1113 | ; PPC64LE-NEXT: .p2align 5 |
| 1114 | ; PPC64LE-NEXT: .LBB73_1: |
| 1115 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1116 | ; PPC64LE-NEXT: beqlr 0 |
| 1117 | ; PPC64LE-NEXT: b .LBB73_2 |
| 1118 | ; PPC64LE-NEXT: .LBB73_2: |
| 1119 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1120 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1121 | ; PPC64LE-NEXT: beq 0, .LBB73_1 |
| 1122 | ; PPC64LE-NEXT: # BB#3: |
| 1123 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1124 | ; PPC64LE-NEXT: blr |
| 1125 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic |
| 1126 | ret void |
| 1127 | } |
| 1128 | |
| 1129 | define void @test74(i64* %ptr, i64 %cmp, i64 %val) { |
| 1130 | ; PPC64LE-LABEL: test74: |
| 1131 | ; PPC64LE: # BB#0: |
| 1132 | ; PPC64LE-NEXT: lwsync |
| 1133 | ; PPC64LE-NEXT: b .LBB74_2 |
| 1134 | ; PPC64LE-NEXT: .p2align 5 |
| 1135 | ; PPC64LE-NEXT: .LBB74_1: |
| 1136 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1137 | ; PPC64LE-NEXT: beqlr 0 |
| 1138 | ; PPC64LE-NEXT: b .LBB74_2 |
| 1139 | ; PPC64LE-NEXT: .LBB74_2: |
| 1140 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1141 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1142 | ; PPC64LE-NEXT: beq 0, .LBB74_1 |
| 1143 | ; PPC64LE-NEXT: # BB#3: |
| 1144 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1145 | ; PPC64LE-NEXT: blr |
| 1146 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire |
| 1147 | ret void |
| 1148 | } |
| 1149 | |
| 1150 | define void @test75(i64* %ptr, i64 %cmp, i64 %val) { |
| 1151 | ; PPC64LE-LABEL: test75: |
| 1152 | ; PPC64LE: # BB#0: |
| 1153 | ; PPC64LE-NEXT: lwsync |
| 1154 | ; PPC64LE-NEXT: .LBB75_1: |
| 1155 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1156 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1157 | ; PPC64LE-NEXT: bne 0, .LBB75_4 |
| 1158 | ; PPC64LE-NEXT: # BB#2: |
| 1159 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1160 | ; PPC64LE-NEXT: bne 0, .LBB75_1 |
| 1161 | ; PPC64LE-NEXT: # BB#3: |
| 1162 | ; PPC64LE-NEXT: lwsync |
| 1163 | ; PPC64LE-NEXT: blr |
| 1164 | ; PPC64LE-NEXT: .LBB75_4: |
| 1165 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1166 | ; PPC64LE-NEXT: lwsync |
| 1167 | ; PPC64LE-NEXT: blr |
| 1168 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic |
| 1169 | ret void |
| 1170 | } |
| 1171 | |
| 1172 | define void @test76(i64* %ptr, i64 %cmp, i64 %val) { |
| 1173 | ; PPC64LE-LABEL: test76: |
| 1174 | ; PPC64LE: # BB#0: |
| 1175 | ; PPC64LE-NEXT: lwsync |
| 1176 | ; PPC64LE-NEXT: .LBB76_1: |
| 1177 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1178 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1179 | ; PPC64LE-NEXT: bne 0, .LBB76_4 |
| 1180 | ; PPC64LE-NEXT: # BB#2: |
| 1181 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1182 | ; PPC64LE-NEXT: bne 0, .LBB76_1 |
| 1183 | ; PPC64LE-NEXT: # BB#3: |
| 1184 | ; PPC64LE-NEXT: lwsync |
| 1185 | ; PPC64LE-NEXT: blr |
| 1186 | ; PPC64LE-NEXT: .LBB76_4: |
| 1187 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1188 | ; PPC64LE-NEXT: lwsync |
| 1189 | ; PPC64LE-NEXT: blr |
| 1190 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire |
| 1191 | ret void |
| 1192 | } |
| 1193 | |
| 1194 | define void @test77(i64* %ptr, i64 %cmp, i64 %val) { |
| 1195 | ; PPC64LE-LABEL: test77: |
| 1196 | ; PPC64LE: # BB#0: |
| 1197 | ; PPC64LE-NEXT: sync |
| 1198 | ; PPC64LE-NEXT: .LBB77_1: |
| 1199 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1200 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1201 | ; PPC64LE-NEXT: bne 0, .LBB77_4 |
| 1202 | ; PPC64LE-NEXT: # BB#2: |
| 1203 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1204 | ; PPC64LE-NEXT: bne 0, .LBB77_1 |
| 1205 | ; PPC64LE-NEXT: # BB#3: |
| 1206 | ; PPC64LE-NEXT: lwsync |
| 1207 | ; PPC64LE-NEXT: blr |
| 1208 | ; PPC64LE-NEXT: .LBB77_4: |
| 1209 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1210 | ; PPC64LE-NEXT: lwsync |
| 1211 | ; PPC64LE-NEXT: blr |
| 1212 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic |
| 1213 | ret void |
| 1214 | } |
| 1215 | |
| 1216 | define void @test78(i64* %ptr, i64 %cmp, i64 %val) { |
| 1217 | ; PPC64LE-LABEL: test78: |
| 1218 | ; PPC64LE: # BB#0: |
| 1219 | ; PPC64LE-NEXT: sync |
| 1220 | ; PPC64LE-NEXT: .LBB78_1: |
| 1221 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1222 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1223 | ; PPC64LE-NEXT: bne 0, .LBB78_4 |
| 1224 | ; PPC64LE-NEXT: # BB#2: |
| 1225 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1226 | ; PPC64LE-NEXT: bne 0, .LBB78_1 |
| 1227 | ; PPC64LE-NEXT: # BB#3: |
| 1228 | ; PPC64LE-NEXT: lwsync |
| 1229 | ; PPC64LE-NEXT: blr |
| 1230 | ; PPC64LE-NEXT: .LBB78_4: |
| 1231 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1232 | ; PPC64LE-NEXT: lwsync |
| 1233 | ; PPC64LE-NEXT: blr |
| 1234 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire |
| 1235 | ret void |
| 1236 | } |
| 1237 | |
| 1238 | define void @test79(i64* %ptr, i64 %cmp, i64 %val) { |
| 1239 | ; PPC64LE-LABEL: test79: |
| 1240 | ; PPC64LE: # BB#0: |
| 1241 | ; PPC64LE-NEXT: sync |
| 1242 | ; PPC64LE-NEXT: .LBB79_1: |
| 1243 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1244 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1245 | ; PPC64LE-NEXT: bne 0, .LBB79_4 |
| 1246 | ; PPC64LE-NEXT: # BB#2: |
| 1247 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1248 | ; PPC64LE-NEXT: bne 0, .LBB79_1 |
| 1249 | ; PPC64LE-NEXT: # BB#3: |
| 1250 | ; PPC64LE-NEXT: lwsync |
| 1251 | ; PPC64LE-NEXT: blr |
| 1252 | ; PPC64LE-NEXT: .LBB79_4: |
| 1253 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1254 | ; PPC64LE-NEXT: lwsync |
| 1255 | ; PPC64LE-NEXT: blr |
| 1256 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst |
| 1257 | ret void |
| 1258 | } |
| 1259 | |
| 1260 | define void @test80(i8* %ptr, i8 %cmp, i8 %val) { |
| 1261 | ; PPC64LE-LABEL: test80: |
| 1262 | ; PPC64LE: # BB#0: |
| 1263 | ; PPC64LE-NEXT: b .LBB80_2 |
| 1264 | ; PPC64LE-NEXT: .p2align 5 |
| 1265 | ; PPC64LE-NEXT: .LBB80_1: |
| 1266 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 1267 | ; PPC64LE-NEXT: beqlr 0 |
| 1268 | ; PPC64LE-NEXT: b .LBB80_2 |
| 1269 | ; PPC64LE-NEXT: .LBB80_2: |
| 1270 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 1271 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1272 | ; PPC64LE-NEXT: beq 0, .LBB80_1 |
| 1273 | ; PPC64LE-NEXT: # BB#3: |
| 1274 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 1275 | ; PPC64LE-NEXT: blr |
| 1276 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val singlethread monotonic monotonic |
| 1277 | ret void |
| 1278 | } |
| 1279 | |
| 1280 | define void @test81(i8* %ptr, i8 %cmp, i8 %val) { |
| 1281 | ; PPC64LE-LABEL: test81: |
| 1282 | ; PPC64LE: # BB#0: |
| 1283 | ; PPC64LE-NEXT: .LBB81_1: |
| 1284 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 1285 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1286 | ; PPC64LE-NEXT: bne 0, .LBB81_4 |
| 1287 | ; PPC64LE-NEXT: # BB#2: |
| 1288 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 1289 | ; PPC64LE-NEXT: bne 0, .LBB81_1 |
| 1290 | ; PPC64LE-NEXT: # BB#3: |
| 1291 | ; PPC64LE-NEXT: lwsync |
| 1292 | ; PPC64LE-NEXT: blr |
| 1293 | ; PPC64LE-NEXT: .LBB81_4: |
| 1294 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 1295 | ; PPC64LE-NEXT: lwsync |
| 1296 | ; PPC64LE-NEXT: blr |
| 1297 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val singlethread acquire monotonic |
| 1298 | ret void |
| 1299 | } |
| 1300 | |
| 1301 | define void @test82(i8* %ptr, i8 %cmp, i8 %val) { |
| 1302 | ; PPC64LE-LABEL: test82: |
| 1303 | ; PPC64LE: # BB#0: |
| 1304 | ; PPC64LE-NEXT: .LBB82_1: |
| 1305 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 1306 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1307 | ; PPC64LE-NEXT: bne 0, .LBB82_4 |
| 1308 | ; PPC64LE-NEXT: # BB#2: |
| 1309 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 1310 | ; PPC64LE-NEXT: bne 0, .LBB82_1 |
| 1311 | ; PPC64LE-NEXT: # BB#3: |
| 1312 | ; PPC64LE-NEXT: lwsync |
| 1313 | ; PPC64LE-NEXT: blr |
| 1314 | ; PPC64LE-NEXT: .LBB82_4: |
| 1315 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 1316 | ; PPC64LE-NEXT: lwsync |
| 1317 | ; PPC64LE-NEXT: blr |
| 1318 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val singlethread acquire acquire |
| 1319 | ret void |
| 1320 | } |
| 1321 | |
| 1322 | define void @test83(i8* %ptr, i8 %cmp, i8 %val) { |
| 1323 | ; PPC64LE-LABEL: test83: |
| 1324 | ; PPC64LE: # BB#0: |
| 1325 | ; PPC64LE-NEXT: lwsync |
| 1326 | ; PPC64LE-NEXT: b .LBB83_2 |
| 1327 | ; PPC64LE-NEXT: .p2align 5 |
| 1328 | ; PPC64LE-NEXT: .LBB83_1: |
| 1329 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 1330 | ; PPC64LE-NEXT: beqlr 0 |
| 1331 | ; PPC64LE-NEXT: b .LBB83_2 |
| 1332 | ; PPC64LE-NEXT: .LBB83_2: |
| 1333 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 1334 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1335 | ; PPC64LE-NEXT: beq 0, .LBB83_1 |
| 1336 | ; PPC64LE-NEXT: # BB#3: |
| 1337 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 1338 | ; PPC64LE-NEXT: blr |
| 1339 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val singlethread release monotonic |
| 1340 | ret void |
| 1341 | } |
| 1342 | |
| 1343 | define void @test84(i8* %ptr, i8 %cmp, i8 %val) { |
| 1344 | ; PPC64LE-LABEL: test84: |
| 1345 | ; PPC64LE: # BB#0: |
| 1346 | ; PPC64LE-NEXT: lwsync |
| 1347 | ; PPC64LE-NEXT: b .LBB84_2 |
| 1348 | ; PPC64LE-NEXT: .p2align 5 |
| 1349 | ; PPC64LE-NEXT: .LBB84_1: |
| 1350 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 1351 | ; PPC64LE-NEXT: beqlr 0 |
| 1352 | ; PPC64LE-NEXT: b .LBB84_2 |
| 1353 | ; PPC64LE-NEXT: .LBB84_2: |
| 1354 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 1355 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1356 | ; PPC64LE-NEXT: beq 0, .LBB84_1 |
| 1357 | ; PPC64LE-NEXT: # BB#3: |
| 1358 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 1359 | ; PPC64LE-NEXT: blr |
| 1360 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val singlethread release acquire |
| 1361 | ret void |
| 1362 | } |
| 1363 | |
| 1364 | define void @test85(i8* %ptr, i8 %cmp, i8 %val) { |
| 1365 | ; PPC64LE-LABEL: test85: |
| 1366 | ; PPC64LE: # BB#0: |
| 1367 | ; PPC64LE-NEXT: lwsync |
| 1368 | ; PPC64LE-NEXT: .LBB85_1: |
| 1369 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 1370 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1371 | ; PPC64LE-NEXT: bne 0, .LBB85_4 |
| 1372 | ; PPC64LE-NEXT: # BB#2: |
| 1373 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 1374 | ; PPC64LE-NEXT: bne 0, .LBB85_1 |
| 1375 | ; PPC64LE-NEXT: # BB#3: |
| 1376 | ; PPC64LE-NEXT: lwsync |
| 1377 | ; PPC64LE-NEXT: blr |
| 1378 | ; PPC64LE-NEXT: .LBB85_4: |
| 1379 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 1380 | ; PPC64LE-NEXT: lwsync |
| 1381 | ; PPC64LE-NEXT: blr |
| 1382 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val singlethread acq_rel monotonic |
| 1383 | ret void |
| 1384 | } |
| 1385 | |
| 1386 | define void @test86(i8* %ptr, i8 %cmp, i8 %val) { |
| 1387 | ; PPC64LE-LABEL: test86: |
| 1388 | ; PPC64LE: # BB#0: |
| 1389 | ; PPC64LE-NEXT: lwsync |
| 1390 | ; PPC64LE-NEXT: .LBB86_1: |
| 1391 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 1392 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1393 | ; PPC64LE-NEXT: bne 0, .LBB86_4 |
| 1394 | ; PPC64LE-NEXT: # BB#2: |
| 1395 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 1396 | ; PPC64LE-NEXT: bne 0, .LBB86_1 |
| 1397 | ; PPC64LE-NEXT: # BB#3: |
| 1398 | ; PPC64LE-NEXT: lwsync |
| 1399 | ; PPC64LE-NEXT: blr |
| 1400 | ; PPC64LE-NEXT: .LBB86_4: |
| 1401 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 1402 | ; PPC64LE-NEXT: lwsync |
| 1403 | ; PPC64LE-NEXT: blr |
| 1404 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val singlethread acq_rel acquire |
| 1405 | ret void |
| 1406 | } |
| 1407 | |
| 1408 | define void @test87(i8* %ptr, i8 %cmp, i8 %val) { |
| 1409 | ; PPC64LE-LABEL: test87: |
| 1410 | ; PPC64LE: # BB#0: |
| 1411 | ; PPC64LE-NEXT: sync |
| 1412 | ; PPC64LE-NEXT: .LBB87_1: |
| 1413 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 1414 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1415 | ; PPC64LE-NEXT: bne 0, .LBB87_4 |
| 1416 | ; PPC64LE-NEXT: # BB#2: |
| 1417 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 1418 | ; PPC64LE-NEXT: bne 0, .LBB87_1 |
| 1419 | ; PPC64LE-NEXT: # BB#3: |
| 1420 | ; PPC64LE-NEXT: lwsync |
| 1421 | ; PPC64LE-NEXT: blr |
| 1422 | ; PPC64LE-NEXT: .LBB87_4: |
| 1423 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 1424 | ; PPC64LE-NEXT: lwsync |
| 1425 | ; PPC64LE-NEXT: blr |
| 1426 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val singlethread seq_cst monotonic |
| 1427 | ret void |
| 1428 | } |
| 1429 | |
| 1430 | define void @test88(i8* %ptr, i8 %cmp, i8 %val) { |
| 1431 | ; PPC64LE-LABEL: test88: |
| 1432 | ; PPC64LE: # BB#0: |
| 1433 | ; PPC64LE-NEXT: sync |
| 1434 | ; PPC64LE-NEXT: .LBB88_1: |
| 1435 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 1436 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1437 | ; PPC64LE-NEXT: bne 0, .LBB88_4 |
| 1438 | ; PPC64LE-NEXT: # BB#2: |
| 1439 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 1440 | ; PPC64LE-NEXT: bne 0, .LBB88_1 |
| 1441 | ; PPC64LE-NEXT: # BB#3: |
| 1442 | ; PPC64LE-NEXT: lwsync |
| 1443 | ; PPC64LE-NEXT: blr |
| 1444 | ; PPC64LE-NEXT: .LBB88_4: |
| 1445 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 1446 | ; PPC64LE-NEXT: lwsync |
| 1447 | ; PPC64LE-NEXT: blr |
| 1448 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val singlethread seq_cst acquire |
| 1449 | ret void |
| 1450 | } |
| 1451 | |
| 1452 | define void @test89(i8* %ptr, i8 %cmp, i8 %val) { |
| 1453 | ; PPC64LE-LABEL: test89: |
| 1454 | ; PPC64LE: # BB#0: |
| 1455 | ; PPC64LE-NEXT: sync |
| 1456 | ; PPC64LE-NEXT: .LBB89_1: |
| 1457 | ; PPC64LE-NEXT: lbarx 6, 0, 3 |
| 1458 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1459 | ; PPC64LE-NEXT: bne 0, .LBB89_4 |
| 1460 | ; PPC64LE-NEXT: # BB#2: |
| 1461 | ; PPC64LE-NEXT: stbcx. 5, 0, 3 |
| 1462 | ; PPC64LE-NEXT: bne 0, .LBB89_1 |
| 1463 | ; PPC64LE-NEXT: # BB#3: |
| 1464 | ; PPC64LE-NEXT: lwsync |
| 1465 | ; PPC64LE-NEXT: blr |
| 1466 | ; PPC64LE-NEXT: .LBB89_4: |
| 1467 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 1468 | ; PPC64LE-NEXT: lwsync |
| 1469 | ; PPC64LE-NEXT: blr |
| 1470 | %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val singlethread seq_cst seq_cst |
| 1471 | ret void |
| 1472 | } |
| 1473 | |
| 1474 | define void @test90(i16* %ptr, i16 %cmp, i16 %val) { |
| 1475 | ; PPC64LE-LABEL: test90: |
| 1476 | ; PPC64LE: # BB#0: |
| 1477 | ; PPC64LE-NEXT: b .LBB90_2 |
| 1478 | ; PPC64LE-NEXT: .p2align 5 |
| 1479 | ; PPC64LE-NEXT: .LBB90_1: |
| 1480 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 1481 | ; PPC64LE-NEXT: beqlr 0 |
| 1482 | ; PPC64LE-NEXT: b .LBB90_2 |
| 1483 | ; PPC64LE-NEXT: .LBB90_2: |
| 1484 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 1485 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1486 | ; PPC64LE-NEXT: beq 0, .LBB90_1 |
| 1487 | ; PPC64LE-NEXT: # BB#3: |
| 1488 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 1489 | ; PPC64LE-NEXT: blr |
| 1490 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val singlethread monotonic monotonic |
| 1491 | ret void |
| 1492 | } |
| 1493 | |
| 1494 | define void @test91(i16* %ptr, i16 %cmp, i16 %val) { |
| 1495 | ; PPC64LE-LABEL: test91: |
| 1496 | ; PPC64LE: # BB#0: |
| 1497 | ; PPC64LE-NEXT: .LBB91_1: |
| 1498 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 1499 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1500 | ; PPC64LE-NEXT: bne 0, .LBB91_4 |
| 1501 | ; PPC64LE-NEXT: # BB#2: |
| 1502 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 1503 | ; PPC64LE-NEXT: bne 0, .LBB91_1 |
| 1504 | ; PPC64LE-NEXT: # BB#3: |
| 1505 | ; PPC64LE-NEXT: lwsync |
| 1506 | ; PPC64LE-NEXT: blr |
| 1507 | ; PPC64LE-NEXT: .LBB91_4: |
| 1508 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 1509 | ; PPC64LE-NEXT: lwsync |
| 1510 | ; PPC64LE-NEXT: blr |
| 1511 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val singlethread acquire monotonic |
| 1512 | ret void |
| 1513 | } |
| 1514 | |
| 1515 | define void @test92(i16* %ptr, i16 %cmp, i16 %val) { |
| 1516 | ; PPC64LE-LABEL: test92: |
| 1517 | ; PPC64LE: # BB#0: |
| 1518 | ; PPC64LE-NEXT: .LBB92_1: |
| 1519 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 1520 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1521 | ; PPC64LE-NEXT: bne 0, .LBB92_4 |
| 1522 | ; PPC64LE-NEXT: # BB#2: |
| 1523 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 1524 | ; PPC64LE-NEXT: bne 0, .LBB92_1 |
| 1525 | ; PPC64LE-NEXT: # BB#3: |
| 1526 | ; PPC64LE-NEXT: lwsync |
| 1527 | ; PPC64LE-NEXT: blr |
| 1528 | ; PPC64LE-NEXT: .LBB92_4: |
| 1529 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 1530 | ; PPC64LE-NEXT: lwsync |
| 1531 | ; PPC64LE-NEXT: blr |
| 1532 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val singlethread acquire acquire |
| 1533 | ret void |
| 1534 | } |
| 1535 | |
| 1536 | define void @test93(i16* %ptr, i16 %cmp, i16 %val) { |
| 1537 | ; PPC64LE-LABEL: test93: |
| 1538 | ; PPC64LE: # BB#0: |
| 1539 | ; PPC64LE-NEXT: lwsync |
| 1540 | ; PPC64LE-NEXT: b .LBB93_2 |
| 1541 | ; PPC64LE-NEXT: .p2align 5 |
| 1542 | ; PPC64LE-NEXT: .LBB93_1: |
| 1543 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 1544 | ; PPC64LE-NEXT: beqlr 0 |
| 1545 | ; PPC64LE-NEXT: b .LBB93_2 |
| 1546 | ; PPC64LE-NEXT: .LBB93_2: |
| 1547 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 1548 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1549 | ; PPC64LE-NEXT: beq 0, .LBB93_1 |
| 1550 | ; PPC64LE-NEXT: # BB#3: |
| 1551 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 1552 | ; PPC64LE-NEXT: blr |
| 1553 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val singlethread release monotonic |
| 1554 | ret void |
| 1555 | } |
| 1556 | |
| 1557 | define void @test94(i16* %ptr, i16 %cmp, i16 %val) { |
| 1558 | ; PPC64LE-LABEL: test94: |
| 1559 | ; PPC64LE: # BB#0: |
| 1560 | ; PPC64LE-NEXT: lwsync |
| 1561 | ; PPC64LE-NEXT: b .LBB94_2 |
| 1562 | ; PPC64LE-NEXT: .p2align 5 |
| 1563 | ; PPC64LE-NEXT: .LBB94_1: |
| 1564 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 1565 | ; PPC64LE-NEXT: beqlr 0 |
| 1566 | ; PPC64LE-NEXT: b .LBB94_2 |
| 1567 | ; PPC64LE-NEXT: .LBB94_2: |
| 1568 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 1569 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1570 | ; PPC64LE-NEXT: beq 0, .LBB94_1 |
| 1571 | ; PPC64LE-NEXT: # BB#3: |
| 1572 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 1573 | ; PPC64LE-NEXT: blr |
| 1574 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val singlethread release acquire |
| 1575 | ret void |
| 1576 | } |
| 1577 | |
| 1578 | define void @test95(i16* %ptr, i16 %cmp, i16 %val) { |
| 1579 | ; PPC64LE-LABEL: test95: |
| 1580 | ; PPC64LE: # BB#0: |
| 1581 | ; PPC64LE-NEXT: lwsync |
| 1582 | ; PPC64LE-NEXT: .LBB95_1: |
| 1583 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 1584 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1585 | ; PPC64LE-NEXT: bne 0, .LBB95_4 |
| 1586 | ; PPC64LE-NEXT: # BB#2: |
| 1587 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 1588 | ; PPC64LE-NEXT: bne 0, .LBB95_1 |
| 1589 | ; PPC64LE-NEXT: # BB#3: |
| 1590 | ; PPC64LE-NEXT: lwsync |
| 1591 | ; PPC64LE-NEXT: blr |
| 1592 | ; PPC64LE-NEXT: .LBB95_4: |
| 1593 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 1594 | ; PPC64LE-NEXT: lwsync |
| 1595 | ; PPC64LE-NEXT: blr |
| 1596 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val singlethread acq_rel monotonic |
| 1597 | ret void |
| 1598 | } |
| 1599 | |
| 1600 | define void @test96(i16* %ptr, i16 %cmp, i16 %val) { |
| 1601 | ; PPC64LE-LABEL: test96: |
| 1602 | ; PPC64LE: # BB#0: |
| 1603 | ; PPC64LE-NEXT: lwsync |
| 1604 | ; PPC64LE-NEXT: .LBB96_1: |
| 1605 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 1606 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1607 | ; PPC64LE-NEXT: bne 0, .LBB96_4 |
| 1608 | ; PPC64LE-NEXT: # BB#2: |
| 1609 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 1610 | ; PPC64LE-NEXT: bne 0, .LBB96_1 |
| 1611 | ; PPC64LE-NEXT: # BB#3: |
| 1612 | ; PPC64LE-NEXT: lwsync |
| 1613 | ; PPC64LE-NEXT: blr |
| 1614 | ; PPC64LE-NEXT: .LBB96_4: |
| 1615 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 1616 | ; PPC64LE-NEXT: lwsync |
| 1617 | ; PPC64LE-NEXT: blr |
| 1618 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val singlethread acq_rel acquire |
| 1619 | ret void |
| 1620 | } |
| 1621 | |
| 1622 | define void @test97(i16* %ptr, i16 %cmp, i16 %val) { |
| 1623 | ; PPC64LE-LABEL: test97: |
| 1624 | ; PPC64LE: # BB#0: |
| 1625 | ; PPC64LE-NEXT: sync |
| 1626 | ; PPC64LE-NEXT: .LBB97_1: |
| 1627 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 1628 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1629 | ; PPC64LE-NEXT: bne 0, .LBB97_4 |
| 1630 | ; PPC64LE-NEXT: # BB#2: |
| 1631 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 1632 | ; PPC64LE-NEXT: bne 0, .LBB97_1 |
| 1633 | ; PPC64LE-NEXT: # BB#3: |
| 1634 | ; PPC64LE-NEXT: lwsync |
| 1635 | ; PPC64LE-NEXT: blr |
| 1636 | ; PPC64LE-NEXT: .LBB97_4: |
| 1637 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 1638 | ; PPC64LE-NEXT: lwsync |
| 1639 | ; PPC64LE-NEXT: blr |
| 1640 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val singlethread seq_cst monotonic |
| 1641 | ret void |
| 1642 | } |
| 1643 | |
| 1644 | define void @test98(i16* %ptr, i16 %cmp, i16 %val) { |
| 1645 | ; PPC64LE-LABEL: test98: |
| 1646 | ; PPC64LE: # BB#0: |
| 1647 | ; PPC64LE-NEXT: sync |
| 1648 | ; PPC64LE-NEXT: .LBB98_1: |
| 1649 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 1650 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1651 | ; PPC64LE-NEXT: bne 0, .LBB98_4 |
| 1652 | ; PPC64LE-NEXT: # BB#2: |
| 1653 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 1654 | ; PPC64LE-NEXT: bne 0, .LBB98_1 |
| 1655 | ; PPC64LE-NEXT: # BB#3: |
| 1656 | ; PPC64LE-NEXT: lwsync |
| 1657 | ; PPC64LE-NEXT: blr |
| 1658 | ; PPC64LE-NEXT: .LBB98_4: |
| 1659 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 1660 | ; PPC64LE-NEXT: lwsync |
| 1661 | ; PPC64LE-NEXT: blr |
| 1662 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val singlethread seq_cst acquire |
| 1663 | ret void |
| 1664 | } |
| 1665 | |
| 1666 | define void @test99(i16* %ptr, i16 %cmp, i16 %val) { |
| 1667 | ; PPC64LE-LABEL: test99: |
| 1668 | ; PPC64LE: # BB#0: |
| 1669 | ; PPC64LE-NEXT: sync |
| 1670 | ; PPC64LE-NEXT: .LBB99_1: |
| 1671 | ; PPC64LE-NEXT: lharx 6, 0, 3 |
| 1672 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1673 | ; PPC64LE-NEXT: bne 0, .LBB99_4 |
| 1674 | ; PPC64LE-NEXT: # BB#2: |
| 1675 | ; PPC64LE-NEXT: sthcx. 5, 0, 3 |
| 1676 | ; PPC64LE-NEXT: bne 0, .LBB99_1 |
| 1677 | ; PPC64LE-NEXT: # BB#3: |
| 1678 | ; PPC64LE-NEXT: lwsync |
| 1679 | ; PPC64LE-NEXT: blr |
| 1680 | ; PPC64LE-NEXT: .LBB99_4: |
| 1681 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 1682 | ; PPC64LE-NEXT: lwsync |
| 1683 | ; PPC64LE-NEXT: blr |
| 1684 | %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val singlethread seq_cst seq_cst |
| 1685 | ret void |
| 1686 | } |
| 1687 | |
| 1688 | define void @test100(i32* %ptr, i32 %cmp, i32 %val) { |
| 1689 | ; PPC64LE-LABEL: test100: |
| 1690 | ; PPC64LE: # BB#0: |
| 1691 | ; PPC64LE-NEXT: b .LBB100_2 |
| 1692 | ; PPC64LE-NEXT: .p2align 5 |
| 1693 | ; PPC64LE-NEXT: .LBB100_1: |
| 1694 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 1695 | ; PPC64LE-NEXT: beqlr 0 |
| 1696 | ; PPC64LE-NEXT: b .LBB100_2 |
| 1697 | ; PPC64LE-NEXT: .LBB100_2: |
| 1698 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 1699 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1700 | ; PPC64LE-NEXT: beq 0, .LBB100_1 |
| 1701 | ; PPC64LE-NEXT: # BB#3: |
| 1702 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 1703 | ; PPC64LE-NEXT: blr |
| 1704 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val singlethread monotonic monotonic |
| 1705 | ret void |
| 1706 | } |
| 1707 | |
| 1708 | define void @test101(i32* %ptr, i32 %cmp, i32 %val) { |
| 1709 | ; PPC64LE-LABEL: test101: |
| 1710 | ; PPC64LE: # BB#0: |
| 1711 | ; PPC64LE-NEXT: .LBB101_1: |
| 1712 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 1713 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1714 | ; PPC64LE-NEXT: bne 0, .LBB101_4 |
| 1715 | ; PPC64LE-NEXT: # BB#2: |
| 1716 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 1717 | ; PPC64LE-NEXT: bne 0, .LBB101_1 |
| 1718 | ; PPC64LE-NEXT: # BB#3: |
| 1719 | ; PPC64LE-NEXT: lwsync |
| 1720 | ; PPC64LE-NEXT: blr |
| 1721 | ; PPC64LE-NEXT: .LBB101_4: |
| 1722 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 1723 | ; PPC64LE-NEXT: lwsync |
| 1724 | ; PPC64LE-NEXT: blr |
| 1725 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val singlethread acquire monotonic |
| 1726 | ret void |
| 1727 | } |
| 1728 | |
| 1729 | define void @test102(i32* %ptr, i32 %cmp, i32 %val) { |
| 1730 | ; PPC64LE-LABEL: test102: |
| 1731 | ; PPC64LE: # BB#0: |
| 1732 | ; PPC64LE-NEXT: .LBB102_1: |
| 1733 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 1734 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1735 | ; PPC64LE-NEXT: bne 0, .LBB102_4 |
| 1736 | ; PPC64LE-NEXT: # BB#2: |
| 1737 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 1738 | ; PPC64LE-NEXT: bne 0, .LBB102_1 |
| 1739 | ; PPC64LE-NEXT: # BB#3: |
| 1740 | ; PPC64LE-NEXT: lwsync |
| 1741 | ; PPC64LE-NEXT: blr |
| 1742 | ; PPC64LE-NEXT: .LBB102_4: |
| 1743 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 1744 | ; PPC64LE-NEXT: lwsync |
| 1745 | ; PPC64LE-NEXT: blr |
| 1746 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val singlethread acquire acquire |
| 1747 | ret void |
| 1748 | } |
| 1749 | |
| 1750 | define void @test103(i32* %ptr, i32 %cmp, i32 %val) { |
| 1751 | ; PPC64LE-LABEL: test103: |
| 1752 | ; PPC64LE: # BB#0: |
| 1753 | ; PPC64LE-NEXT: lwsync |
| 1754 | ; PPC64LE-NEXT: b .LBB103_2 |
| 1755 | ; PPC64LE-NEXT: .p2align 5 |
| 1756 | ; PPC64LE-NEXT: .LBB103_1: |
| 1757 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 1758 | ; PPC64LE-NEXT: beqlr 0 |
| 1759 | ; PPC64LE-NEXT: b .LBB103_2 |
| 1760 | ; PPC64LE-NEXT: .LBB103_2: |
| 1761 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 1762 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1763 | ; PPC64LE-NEXT: beq 0, .LBB103_1 |
| 1764 | ; PPC64LE-NEXT: # BB#3: |
| 1765 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 1766 | ; PPC64LE-NEXT: blr |
| 1767 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val singlethread release monotonic |
| 1768 | ret void |
| 1769 | } |
| 1770 | |
| 1771 | define void @test104(i32* %ptr, i32 %cmp, i32 %val) { |
| 1772 | ; PPC64LE-LABEL: test104: |
| 1773 | ; PPC64LE: # BB#0: |
| 1774 | ; PPC64LE-NEXT: lwsync |
| 1775 | ; PPC64LE-NEXT: b .LBB104_2 |
| 1776 | ; PPC64LE-NEXT: .p2align 5 |
| 1777 | ; PPC64LE-NEXT: .LBB104_1: |
| 1778 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 1779 | ; PPC64LE-NEXT: beqlr 0 |
| 1780 | ; PPC64LE-NEXT: b .LBB104_2 |
| 1781 | ; PPC64LE-NEXT: .LBB104_2: |
| 1782 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 1783 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1784 | ; PPC64LE-NEXT: beq 0, .LBB104_1 |
| 1785 | ; PPC64LE-NEXT: # BB#3: |
| 1786 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 1787 | ; PPC64LE-NEXT: blr |
| 1788 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val singlethread release acquire |
| 1789 | ret void |
| 1790 | } |
| 1791 | |
| 1792 | define void @test105(i32* %ptr, i32 %cmp, i32 %val) { |
| 1793 | ; PPC64LE-LABEL: test105: |
| 1794 | ; PPC64LE: # BB#0: |
| 1795 | ; PPC64LE-NEXT: lwsync |
| 1796 | ; PPC64LE-NEXT: .LBB105_1: |
| 1797 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 1798 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1799 | ; PPC64LE-NEXT: bne 0, .LBB105_4 |
| 1800 | ; PPC64LE-NEXT: # BB#2: |
| 1801 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 1802 | ; PPC64LE-NEXT: bne 0, .LBB105_1 |
| 1803 | ; PPC64LE-NEXT: # BB#3: |
| 1804 | ; PPC64LE-NEXT: lwsync |
| 1805 | ; PPC64LE-NEXT: blr |
| 1806 | ; PPC64LE-NEXT: .LBB105_4: |
| 1807 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 1808 | ; PPC64LE-NEXT: lwsync |
| 1809 | ; PPC64LE-NEXT: blr |
| 1810 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val singlethread acq_rel monotonic |
| 1811 | ret void |
| 1812 | } |
| 1813 | |
| 1814 | define void @test106(i32* %ptr, i32 %cmp, i32 %val) { |
| 1815 | ; PPC64LE-LABEL: test106: |
| 1816 | ; PPC64LE: # BB#0: |
| 1817 | ; PPC64LE-NEXT: lwsync |
| 1818 | ; PPC64LE-NEXT: .LBB106_1: |
| 1819 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 1820 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1821 | ; PPC64LE-NEXT: bne 0, .LBB106_4 |
| 1822 | ; PPC64LE-NEXT: # BB#2: |
| 1823 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 1824 | ; PPC64LE-NEXT: bne 0, .LBB106_1 |
| 1825 | ; PPC64LE-NEXT: # BB#3: |
| 1826 | ; PPC64LE-NEXT: lwsync |
| 1827 | ; PPC64LE-NEXT: blr |
| 1828 | ; PPC64LE-NEXT: .LBB106_4: |
| 1829 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 1830 | ; PPC64LE-NEXT: lwsync |
| 1831 | ; PPC64LE-NEXT: blr |
| 1832 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val singlethread acq_rel acquire |
| 1833 | ret void |
| 1834 | } |
| 1835 | |
| 1836 | define void @test107(i32* %ptr, i32 %cmp, i32 %val) { |
| 1837 | ; PPC64LE-LABEL: test107: |
| 1838 | ; PPC64LE: # BB#0: |
| 1839 | ; PPC64LE-NEXT: sync |
| 1840 | ; PPC64LE-NEXT: .LBB107_1: |
| 1841 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 1842 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1843 | ; PPC64LE-NEXT: bne 0, .LBB107_4 |
| 1844 | ; PPC64LE-NEXT: # BB#2: |
| 1845 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 1846 | ; PPC64LE-NEXT: bne 0, .LBB107_1 |
| 1847 | ; PPC64LE-NEXT: # BB#3: |
| 1848 | ; PPC64LE-NEXT: lwsync |
| 1849 | ; PPC64LE-NEXT: blr |
| 1850 | ; PPC64LE-NEXT: .LBB107_4: |
| 1851 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 1852 | ; PPC64LE-NEXT: lwsync |
| 1853 | ; PPC64LE-NEXT: blr |
| 1854 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val singlethread seq_cst monotonic |
| 1855 | ret void |
| 1856 | } |
| 1857 | |
| 1858 | define void @test108(i32* %ptr, i32 %cmp, i32 %val) { |
| 1859 | ; PPC64LE-LABEL: test108: |
| 1860 | ; PPC64LE: # BB#0: |
| 1861 | ; PPC64LE-NEXT: sync |
| 1862 | ; PPC64LE-NEXT: .LBB108_1: |
| 1863 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 1864 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1865 | ; PPC64LE-NEXT: bne 0, .LBB108_4 |
| 1866 | ; PPC64LE-NEXT: # BB#2: |
| 1867 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 1868 | ; PPC64LE-NEXT: bne 0, .LBB108_1 |
| 1869 | ; PPC64LE-NEXT: # BB#3: |
| 1870 | ; PPC64LE-NEXT: lwsync |
| 1871 | ; PPC64LE-NEXT: blr |
| 1872 | ; PPC64LE-NEXT: .LBB108_4: |
| 1873 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 1874 | ; PPC64LE-NEXT: lwsync |
| 1875 | ; PPC64LE-NEXT: blr |
| 1876 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val singlethread seq_cst acquire |
| 1877 | ret void |
| 1878 | } |
| 1879 | |
| 1880 | define void @test109(i32* %ptr, i32 %cmp, i32 %val) { |
| 1881 | ; PPC64LE-LABEL: test109: |
| 1882 | ; PPC64LE: # BB#0: |
| 1883 | ; PPC64LE-NEXT: sync |
| 1884 | ; PPC64LE-NEXT: .LBB109_1: |
| 1885 | ; PPC64LE-NEXT: lwarx 6, 0, 3 |
| 1886 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 1887 | ; PPC64LE-NEXT: bne 0, .LBB109_4 |
| 1888 | ; PPC64LE-NEXT: # BB#2: |
| 1889 | ; PPC64LE-NEXT: stwcx. 5, 0, 3 |
| 1890 | ; PPC64LE-NEXT: bne 0, .LBB109_1 |
| 1891 | ; PPC64LE-NEXT: # BB#3: |
| 1892 | ; PPC64LE-NEXT: lwsync |
| 1893 | ; PPC64LE-NEXT: blr |
| 1894 | ; PPC64LE-NEXT: .LBB109_4: |
| 1895 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 1896 | ; PPC64LE-NEXT: lwsync |
| 1897 | ; PPC64LE-NEXT: blr |
| 1898 | %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val singlethread seq_cst seq_cst |
| 1899 | ret void |
| 1900 | } |
| 1901 | |
| 1902 | define void @test110(i64* %ptr, i64 %cmp, i64 %val) { |
| 1903 | ; PPC64LE-LABEL: test110: |
| 1904 | ; PPC64LE: # BB#0: |
| 1905 | ; PPC64LE-NEXT: b .LBB110_2 |
| 1906 | ; PPC64LE-NEXT: .p2align 5 |
| 1907 | ; PPC64LE-NEXT: .LBB110_1: |
| 1908 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1909 | ; PPC64LE-NEXT: beqlr 0 |
| 1910 | ; PPC64LE-NEXT: b .LBB110_2 |
| 1911 | ; PPC64LE-NEXT: .LBB110_2: |
| 1912 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1913 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1914 | ; PPC64LE-NEXT: beq 0, .LBB110_1 |
| 1915 | ; PPC64LE-NEXT: # BB#3: |
| 1916 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1917 | ; PPC64LE-NEXT: blr |
| 1918 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val singlethread monotonic monotonic |
| 1919 | ret void |
| 1920 | } |
| 1921 | |
| 1922 | define void @test111(i64* %ptr, i64 %cmp, i64 %val) { |
| 1923 | ; PPC64LE-LABEL: test111: |
| 1924 | ; PPC64LE: # BB#0: |
| 1925 | ; PPC64LE-NEXT: .LBB111_1: |
| 1926 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1927 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1928 | ; PPC64LE-NEXT: bne 0, .LBB111_4 |
| 1929 | ; PPC64LE-NEXT: # BB#2: |
| 1930 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1931 | ; PPC64LE-NEXT: bne 0, .LBB111_1 |
| 1932 | ; PPC64LE-NEXT: # BB#3: |
| 1933 | ; PPC64LE-NEXT: lwsync |
| 1934 | ; PPC64LE-NEXT: blr |
| 1935 | ; PPC64LE-NEXT: .LBB111_4: |
| 1936 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1937 | ; PPC64LE-NEXT: lwsync |
| 1938 | ; PPC64LE-NEXT: blr |
| 1939 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val singlethread acquire monotonic |
| 1940 | ret void |
| 1941 | } |
| 1942 | |
| 1943 | define void @test112(i64* %ptr, i64 %cmp, i64 %val) { |
| 1944 | ; PPC64LE-LABEL: test112: |
| 1945 | ; PPC64LE: # BB#0: |
| 1946 | ; PPC64LE-NEXT: .LBB112_1: |
| 1947 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1948 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1949 | ; PPC64LE-NEXT: bne 0, .LBB112_4 |
| 1950 | ; PPC64LE-NEXT: # BB#2: |
| 1951 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1952 | ; PPC64LE-NEXT: bne 0, .LBB112_1 |
| 1953 | ; PPC64LE-NEXT: # BB#3: |
| 1954 | ; PPC64LE-NEXT: lwsync |
| 1955 | ; PPC64LE-NEXT: blr |
| 1956 | ; PPC64LE-NEXT: .LBB112_4: |
| 1957 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1958 | ; PPC64LE-NEXT: lwsync |
| 1959 | ; PPC64LE-NEXT: blr |
| 1960 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val singlethread acquire acquire |
| 1961 | ret void |
| 1962 | } |
| 1963 | |
| 1964 | define void @test113(i64* %ptr, i64 %cmp, i64 %val) { |
| 1965 | ; PPC64LE-LABEL: test113: |
| 1966 | ; PPC64LE: # BB#0: |
| 1967 | ; PPC64LE-NEXT: lwsync |
| 1968 | ; PPC64LE-NEXT: b .LBB113_2 |
| 1969 | ; PPC64LE-NEXT: .p2align 5 |
| 1970 | ; PPC64LE-NEXT: .LBB113_1: |
| 1971 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1972 | ; PPC64LE-NEXT: beqlr 0 |
| 1973 | ; PPC64LE-NEXT: b .LBB113_2 |
| 1974 | ; PPC64LE-NEXT: .LBB113_2: |
| 1975 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1976 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1977 | ; PPC64LE-NEXT: beq 0, .LBB113_1 |
| 1978 | ; PPC64LE-NEXT: # BB#3: |
| 1979 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 1980 | ; PPC64LE-NEXT: blr |
| 1981 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val singlethread release monotonic |
| 1982 | ret void |
| 1983 | } |
| 1984 | |
| 1985 | define void @test114(i64* %ptr, i64 %cmp, i64 %val) { |
| 1986 | ; PPC64LE-LABEL: test114: |
| 1987 | ; PPC64LE: # BB#0: |
| 1988 | ; PPC64LE-NEXT: lwsync |
| 1989 | ; PPC64LE-NEXT: b .LBB114_2 |
| 1990 | ; PPC64LE-NEXT: .p2align 5 |
| 1991 | ; PPC64LE-NEXT: .LBB114_1: |
| 1992 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 1993 | ; PPC64LE-NEXT: beqlr 0 |
| 1994 | ; PPC64LE-NEXT: b .LBB114_2 |
| 1995 | ; PPC64LE-NEXT: .LBB114_2: |
| 1996 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 1997 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 1998 | ; PPC64LE-NEXT: beq 0, .LBB114_1 |
| 1999 | ; PPC64LE-NEXT: # BB#3: |
| 2000 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 2001 | ; PPC64LE-NEXT: blr |
| 2002 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val singlethread release acquire |
| 2003 | ret void |
| 2004 | } |
| 2005 | |
| 2006 | define void @test115(i64* %ptr, i64 %cmp, i64 %val) { |
| 2007 | ; PPC64LE-LABEL: test115: |
| 2008 | ; PPC64LE: # BB#0: |
| 2009 | ; PPC64LE-NEXT: lwsync |
| 2010 | ; PPC64LE-NEXT: .LBB115_1: |
| 2011 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 2012 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 2013 | ; PPC64LE-NEXT: bne 0, .LBB115_4 |
| 2014 | ; PPC64LE-NEXT: # BB#2: |
| 2015 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 2016 | ; PPC64LE-NEXT: bne 0, .LBB115_1 |
| 2017 | ; PPC64LE-NEXT: # BB#3: |
| 2018 | ; PPC64LE-NEXT: lwsync |
| 2019 | ; PPC64LE-NEXT: blr |
| 2020 | ; PPC64LE-NEXT: .LBB115_4: |
| 2021 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 2022 | ; PPC64LE-NEXT: lwsync |
| 2023 | ; PPC64LE-NEXT: blr |
| 2024 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val singlethread acq_rel monotonic |
| 2025 | ret void |
| 2026 | } |
| 2027 | |
| 2028 | define void @test116(i64* %ptr, i64 %cmp, i64 %val) { |
| 2029 | ; PPC64LE-LABEL: test116: |
| 2030 | ; PPC64LE: # BB#0: |
| 2031 | ; PPC64LE-NEXT: lwsync |
| 2032 | ; PPC64LE-NEXT: .LBB116_1: |
| 2033 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 2034 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 2035 | ; PPC64LE-NEXT: bne 0, .LBB116_4 |
| 2036 | ; PPC64LE-NEXT: # BB#2: |
| 2037 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 2038 | ; PPC64LE-NEXT: bne 0, .LBB116_1 |
| 2039 | ; PPC64LE-NEXT: # BB#3: |
| 2040 | ; PPC64LE-NEXT: lwsync |
| 2041 | ; PPC64LE-NEXT: blr |
| 2042 | ; PPC64LE-NEXT: .LBB116_4: |
| 2043 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 2044 | ; PPC64LE-NEXT: lwsync |
| 2045 | ; PPC64LE-NEXT: blr |
| 2046 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val singlethread acq_rel acquire |
| 2047 | ret void |
| 2048 | } |
| 2049 | |
| 2050 | define void @test117(i64* %ptr, i64 %cmp, i64 %val) { |
| 2051 | ; PPC64LE-LABEL: test117: |
| 2052 | ; PPC64LE: # BB#0: |
| 2053 | ; PPC64LE-NEXT: sync |
| 2054 | ; PPC64LE-NEXT: .LBB117_1: |
| 2055 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 2056 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 2057 | ; PPC64LE-NEXT: bne 0, .LBB117_4 |
| 2058 | ; PPC64LE-NEXT: # BB#2: |
| 2059 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 2060 | ; PPC64LE-NEXT: bne 0, .LBB117_1 |
| 2061 | ; PPC64LE-NEXT: # BB#3: |
| 2062 | ; PPC64LE-NEXT: lwsync |
| 2063 | ; PPC64LE-NEXT: blr |
| 2064 | ; PPC64LE-NEXT: .LBB117_4: |
| 2065 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 2066 | ; PPC64LE-NEXT: lwsync |
| 2067 | ; PPC64LE-NEXT: blr |
| 2068 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val singlethread seq_cst monotonic |
| 2069 | ret void |
| 2070 | } |
| 2071 | |
| 2072 | define void @test118(i64* %ptr, i64 %cmp, i64 %val) { |
| 2073 | ; PPC64LE-LABEL: test118: |
| 2074 | ; PPC64LE: # BB#0: |
| 2075 | ; PPC64LE-NEXT: sync |
| 2076 | ; PPC64LE-NEXT: .LBB118_1: |
| 2077 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 2078 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 2079 | ; PPC64LE-NEXT: bne 0, .LBB118_4 |
| 2080 | ; PPC64LE-NEXT: # BB#2: |
| 2081 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 2082 | ; PPC64LE-NEXT: bne 0, .LBB118_1 |
| 2083 | ; PPC64LE-NEXT: # BB#3: |
| 2084 | ; PPC64LE-NEXT: lwsync |
| 2085 | ; PPC64LE-NEXT: blr |
| 2086 | ; PPC64LE-NEXT: .LBB118_4: |
| 2087 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 2088 | ; PPC64LE-NEXT: lwsync |
| 2089 | ; PPC64LE-NEXT: blr |
| 2090 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val singlethread seq_cst acquire |
| 2091 | ret void |
| 2092 | } |
| 2093 | |
| 2094 | define void @test119(i64* %ptr, i64 %cmp, i64 %val) { |
| 2095 | ; PPC64LE-LABEL: test119: |
| 2096 | ; PPC64LE: # BB#0: |
| 2097 | ; PPC64LE-NEXT: sync |
| 2098 | ; PPC64LE-NEXT: .LBB119_1: |
| 2099 | ; PPC64LE-NEXT: ldarx 6, 0, 3 |
| 2100 | ; PPC64LE-NEXT: cmpd 4, 6 |
| 2101 | ; PPC64LE-NEXT: bne 0, .LBB119_4 |
| 2102 | ; PPC64LE-NEXT: # BB#2: |
| 2103 | ; PPC64LE-NEXT: stdcx. 5, 0, 3 |
| 2104 | ; PPC64LE-NEXT: bne 0, .LBB119_1 |
| 2105 | ; PPC64LE-NEXT: # BB#3: |
| 2106 | ; PPC64LE-NEXT: lwsync |
| 2107 | ; PPC64LE-NEXT: blr |
| 2108 | ; PPC64LE-NEXT: .LBB119_4: |
| 2109 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 2110 | ; PPC64LE-NEXT: lwsync |
| 2111 | ; PPC64LE-NEXT: blr |
| 2112 | %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val singlethread seq_cst seq_cst |
| 2113 | ret void |
| 2114 | } |
| 2115 | |
| 2116 | define i8 @test120(i8* %ptr, i8 %val) { |
| 2117 | ; PPC64LE-LABEL: test120: |
| 2118 | ; PPC64LE: # BB#0: |
| 2119 | ; PPC64LE-NEXT: .LBB120_1: |
| 2120 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 2121 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 2122 | ; PPC64LE-NEXT: bne 0, .LBB120_1 |
| 2123 | ; PPC64LE-NEXT: # BB#2: |
| 2124 | ; PPC64LE-NEXT: mr 3, 5 |
| 2125 | ; PPC64LE-NEXT: blr |
| 2126 | %ret = atomicrmw xchg i8* %ptr, i8 %val monotonic |
| 2127 | ret i8 %ret |
| 2128 | } |
| 2129 | |
| 2130 | define i8 @test121(i8* %ptr, i8 %val) { |
| 2131 | ; PPC64LE-LABEL: test121: |
| 2132 | ; PPC64LE: # BB#0: |
| 2133 | ; PPC64LE-NEXT: mr 5, 3 |
| 2134 | ; PPC64LE-NEXT: .LBB121_1: |
| 2135 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 2136 | ; PPC64LE-NEXT: stbcx. 4, 0, 5 |
| 2137 | ; PPC64LE-NEXT: bne 0, .LBB121_1 |
| 2138 | ; PPC64LE-NEXT: # BB#2: |
| 2139 | ; PPC64LE-NEXT: lwsync |
| 2140 | ; PPC64LE-NEXT: blr |
| 2141 | %ret = atomicrmw xchg i8* %ptr, i8 %val acquire |
| 2142 | ret i8 %ret |
| 2143 | } |
| 2144 | |
| 2145 | define i8 @test122(i8* %ptr, i8 %val) { |
| 2146 | ; PPC64LE-LABEL: test122: |
| 2147 | ; PPC64LE: # BB#0: |
| 2148 | ; PPC64LE-NEXT: lwsync |
| 2149 | ; PPC64LE-NEXT: .LBB122_1: |
| 2150 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 2151 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 2152 | ; PPC64LE-NEXT: bne 0, .LBB122_1 |
| 2153 | ; PPC64LE-NEXT: # BB#2: |
| 2154 | ; PPC64LE-NEXT: mr 3, 5 |
| 2155 | ; PPC64LE-NEXT: blr |
| 2156 | %ret = atomicrmw xchg i8* %ptr, i8 %val release |
| 2157 | ret i8 %ret |
| 2158 | } |
| 2159 | |
| 2160 | define i8 @test123(i8* %ptr, i8 %val) { |
| 2161 | ; PPC64LE-LABEL: test123: |
| 2162 | ; PPC64LE: # BB#0: |
| 2163 | ; PPC64LE-NEXT: lwsync |
| 2164 | ; PPC64LE-NEXT: .LBB123_1: |
| 2165 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 2166 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 2167 | ; PPC64LE-NEXT: bne 0, .LBB123_1 |
| 2168 | ; PPC64LE-NEXT: # BB#2: |
| 2169 | ; PPC64LE-NEXT: mr 3, 5 |
| 2170 | ; PPC64LE-NEXT: lwsync |
| 2171 | ; PPC64LE-NEXT: blr |
| 2172 | %ret = atomicrmw xchg i8* %ptr, i8 %val acq_rel |
| 2173 | ret i8 %ret |
| 2174 | } |
| 2175 | |
| 2176 | define i8 @test124(i8* %ptr, i8 %val) { |
| 2177 | ; PPC64LE-LABEL: test124: |
| 2178 | ; PPC64LE: # BB#0: |
| 2179 | ; PPC64LE-NEXT: sync |
| 2180 | ; PPC64LE-NEXT: .LBB124_1: |
| 2181 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 2182 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 2183 | ; PPC64LE-NEXT: bne 0, .LBB124_1 |
| 2184 | ; PPC64LE-NEXT: # BB#2: |
| 2185 | ; PPC64LE-NEXT: mr 3, 5 |
| 2186 | ; PPC64LE-NEXT: lwsync |
| 2187 | ; PPC64LE-NEXT: blr |
| 2188 | %ret = atomicrmw xchg i8* %ptr, i8 %val seq_cst |
| 2189 | ret i8 %ret |
| 2190 | } |
| 2191 | |
| 2192 | define i16 @test125(i16* %ptr, i16 %val) { |
| 2193 | ; PPC64LE-LABEL: test125: |
| 2194 | ; PPC64LE: # BB#0: |
| 2195 | ; PPC64LE-NEXT: .LBB125_1: |
| 2196 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 2197 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 2198 | ; PPC64LE-NEXT: bne 0, .LBB125_1 |
| 2199 | ; PPC64LE-NEXT: # BB#2: |
| 2200 | ; PPC64LE-NEXT: mr 3, 5 |
| 2201 | ; PPC64LE-NEXT: blr |
| 2202 | %ret = atomicrmw xchg i16* %ptr, i16 %val monotonic |
| 2203 | ret i16 %ret |
| 2204 | } |
| 2205 | |
| 2206 | define i16 @test126(i16* %ptr, i16 %val) { |
| 2207 | ; PPC64LE-LABEL: test126: |
| 2208 | ; PPC64LE: # BB#0: |
| 2209 | ; PPC64LE-NEXT: mr 5, 3 |
| 2210 | ; PPC64LE-NEXT: .LBB126_1: |
| 2211 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 2212 | ; PPC64LE-NEXT: sthcx. 4, 0, 5 |
| 2213 | ; PPC64LE-NEXT: bne 0, .LBB126_1 |
| 2214 | ; PPC64LE-NEXT: # BB#2: |
| 2215 | ; PPC64LE-NEXT: lwsync |
| 2216 | ; PPC64LE-NEXT: blr |
| 2217 | %ret = atomicrmw xchg i16* %ptr, i16 %val acquire |
| 2218 | ret i16 %ret |
| 2219 | } |
| 2220 | |
| 2221 | define i16 @test127(i16* %ptr, i16 %val) { |
| 2222 | ; PPC64LE-LABEL: test127: |
| 2223 | ; PPC64LE: # BB#0: |
| 2224 | ; PPC64LE-NEXT: lwsync |
| 2225 | ; PPC64LE-NEXT: .LBB127_1: |
| 2226 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 2227 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 2228 | ; PPC64LE-NEXT: bne 0, .LBB127_1 |
| 2229 | ; PPC64LE-NEXT: # BB#2: |
| 2230 | ; PPC64LE-NEXT: mr 3, 5 |
| 2231 | ; PPC64LE-NEXT: blr |
| 2232 | %ret = atomicrmw xchg i16* %ptr, i16 %val release |
| 2233 | ret i16 %ret |
| 2234 | } |
| 2235 | |
| 2236 | define i16 @test128(i16* %ptr, i16 %val) { |
| 2237 | ; PPC64LE-LABEL: test128: |
| 2238 | ; PPC64LE: # BB#0: |
| 2239 | ; PPC64LE-NEXT: lwsync |
| 2240 | ; PPC64LE-NEXT: .LBB128_1: |
| 2241 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 2242 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 2243 | ; PPC64LE-NEXT: bne 0, .LBB128_1 |
| 2244 | ; PPC64LE-NEXT: # BB#2: |
| 2245 | ; PPC64LE-NEXT: mr 3, 5 |
| 2246 | ; PPC64LE-NEXT: lwsync |
| 2247 | ; PPC64LE-NEXT: blr |
| 2248 | %ret = atomicrmw xchg i16* %ptr, i16 %val acq_rel |
| 2249 | ret i16 %ret |
| 2250 | } |
| 2251 | |
| 2252 | define i16 @test129(i16* %ptr, i16 %val) { |
| 2253 | ; PPC64LE-LABEL: test129: |
| 2254 | ; PPC64LE: # BB#0: |
| 2255 | ; PPC64LE-NEXT: sync |
| 2256 | ; PPC64LE-NEXT: .LBB129_1: |
| 2257 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 2258 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 2259 | ; PPC64LE-NEXT: bne 0, .LBB129_1 |
| 2260 | ; PPC64LE-NEXT: # BB#2: |
| 2261 | ; PPC64LE-NEXT: mr 3, 5 |
| 2262 | ; PPC64LE-NEXT: lwsync |
| 2263 | ; PPC64LE-NEXT: blr |
| 2264 | %ret = atomicrmw xchg i16* %ptr, i16 %val seq_cst |
| 2265 | ret i16 %ret |
| 2266 | } |
| 2267 | |
| 2268 | define i32 @test130(i32* %ptr, i32 %val) { |
| 2269 | ; PPC64LE-LABEL: test130: |
| 2270 | ; PPC64LE: # BB#0: |
| 2271 | ; PPC64LE-NEXT: .LBB130_1: |
| 2272 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 2273 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 2274 | ; PPC64LE-NEXT: bne 0, .LBB130_1 |
| 2275 | ; PPC64LE-NEXT: # BB#2: |
| 2276 | ; PPC64LE-NEXT: mr 3, 5 |
| 2277 | ; PPC64LE-NEXT: blr |
| 2278 | %ret = atomicrmw xchg i32* %ptr, i32 %val monotonic |
| 2279 | ret i32 %ret |
| 2280 | } |
| 2281 | |
| 2282 | define i32 @test131(i32* %ptr, i32 %val) { |
| 2283 | ; PPC64LE-LABEL: test131: |
| 2284 | ; PPC64LE: # BB#0: |
| 2285 | ; PPC64LE-NEXT: mr 5, 3 |
| 2286 | ; PPC64LE-NEXT: .LBB131_1: |
| 2287 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 2288 | ; PPC64LE-NEXT: stwcx. 4, 0, 5 |
| 2289 | ; PPC64LE-NEXT: bne 0, .LBB131_1 |
| 2290 | ; PPC64LE-NEXT: # BB#2: |
| 2291 | ; PPC64LE-NEXT: lwsync |
| 2292 | ; PPC64LE-NEXT: blr |
| 2293 | %ret = atomicrmw xchg i32* %ptr, i32 %val acquire |
| 2294 | ret i32 %ret |
| 2295 | } |
| 2296 | |
| 2297 | define i32 @test132(i32* %ptr, i32 %val) { |
| 2298 | ; PPC64LE-LABEL: test132: |
| 2299 | ; PPC64LE: # BB#0: |
| 2300 | ; PPC64LE-NEXT: lwsync |
| 2301 | ; PPC64LE-NEXT: .LBB132_1: |
| 2302 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 2303 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 2304 | ; PPC64LE-NEXT: bne 0, .LBB132_1 |
| 2305 | ; PPC64LE-NEXT: # BB#2: |
| 2306 | ; PPC64LE-NEXT: mr 3, 5 |
| 2307 | ; PPC64LE-NEXT: blr |
| 2308 | %ret = atomicrmw xchg i32* %ptr, i32 %val release |
| 2309 | ret i32 %ret |
| 2310 | } |
| 2311 | |
| 2312 | define i32 @test133(i32* %ptr, i32 %val) { |
| 2313 | ; PPC64LE-LABEL: test133: |
| 2314 | ; PPC64LE: # BB#0: |
| 2315 | ; PPC64LE-NEXT: lwsync |
| 2316 | ; PPC64LE-NEXT: .LBB133_1: |
| 2317 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 2318 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 2319 | ; PPC64LE-NEXT: bne 0, .LBB133_1 |
| 2320 | ; PPC64LE-NEXT: # BB#2: |
| 2321 | ; PPC64LE-NEXT: mr 3, 5 |
| 2322 | ; PPC64LE-NEXT: lwsync |
| 2323 | ; PPC64LE-NEXT: blr |
| 2324 | %ret = atomicrmw xchg i32* %ptr, i32 %val acq_rel |
| 2325 | ret i32 %ret |
| 2326 | } |
| 2327 | |
| 2328 | define i32 @test134(i32* %ptr, i32 %val) { |
| 2329 | ; PPC64LE-LABEL: test134: |
| 2330 | ; PPC64LE: # BB#0: |
| 2331 | ; PPC64LE-NEXT: sync |
| 2332 | ; PPC64LE-NEXT: .LBB134_1: |
| 2333 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 2334 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 2335 | ; PPC64LE-NEXT: bne 0, .LBB134_1 |
| 2336 | ; PPC64LE-NEXT: # BB#2: |
| 2337 | ; PPC64LE-NEXT: mr 3, 5 |
| 2338 | ; PPC64LE-NEXT: lwsync |
| 2339 | ; PPC64LE-NEXT: blr |
| 2340 | %ret = atomicrmw xchg i32* %ptr, i32 %val seq_cst |
| 2341 | ret i32 %ret |
| 2342 | } |
| 2343 | |
| 2344 | define i64 @test135(i64* %ptr, i64 %val) { |
| 2345 | ; PPC64LE-LABEL: test135: |
| 2346 | ; PPC64LE: # BB#0: |
| 2347 | ; PPC64LE-NEXT: .LBB135_1: |
| 2348 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 2349 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 2350 | ; PPC64LE-NEXT: bne 0, .LBB135_1 |
| 2351 | ; PPC64LE-NEXT: # BB#2: |
| 2352 | ; PPC64LE-NEXT: mr 3, 5 |
| 2353 | ; PPC64LE-NEXT: blr |
| 2354 | %ret = atomicrmw xchg i64* %ptr, i64 %val monotonic |
| 2355 | ret i64 %ret |
| 2356 | } |
| 2357 | |
| 2358 | define i64 @test136(i64* %ptr, i64 %val) { |
| 2359 | ; PPC64LE-LABEL: test136: |
| 2360 | ; PPC64LE: # BB#0: |
| 2361 | ; PPC64LE-NEXT: mr 5, 3 |
| 2362 | ; PPC64LE-NEXT: .LBB136_1: |
| 2363 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 2364 | ; PPC64LE-NEXT: stdcx. 4, 0, 5 |
| 2365 | ; PPC64LE-NEXT: bne 0, .LBB136_1 |
| 2366 | ; PPC64LE-NEXT: # BB#2: |
| 2367 | ; PPC64LE-NEXT: lwsync |
| 2368 | ; PPC64LE-NEXT: blr |
| 2369 | %ret = atomicrmw xchg i64* %ptr, i64 %val acquire |
| 2370 | ret i64 %ret |
| 2371 | } |
| 2372 | |
| 2373 | define i64 @test137(i64* %ptr, i64 %val) { |
| 2374 | ; PPC64LE-LABEL: test137: |
| 2375 | ; PPC64LE: # BB#0: |
| 2376 | ; PPC64LE-NEXT: lwsync |
| 2377 | ; PPC64LE-NEXT: .LBB137_1: |
| 2378 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 2379 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 2380 | ; PPC64LE-NEXT: bne 0, .LBB137_1 |
| 2381 | ; PPC64LE-NEXT: # BB#2: |
| 2382 | ; PPC64LE-NEXT: mr 3, 5 |
| 2383 | ; PPC64LE-NEXT: blr |
| 2384 | %ret = atomicrmw xchg i64* %ptr, i64 %val release |
| 2385 | ret i64 %ret |
| 2386 | } |
| 2387 | |
| 2388 | define i64 @test138(i64* %ptr, i64 %val) { |
| 2389 | ; PPC64LE-LABEL: test138: |
| 2390 | ; PPC64LE: # BB#0: |
| 2391 | ; PPC64LE-NEXT: lwsync |
| 2392 | ; PPC64LE-NEXT: .LBB138_1: |
| 2393 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 2394 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 2395 | ; PPC64LE-NEXT: bne 0, .LBB138_1 |
| 2396 | ; PPC64LE-NEXT: # BB#2: |
| 2397 | ; PPC64LE-NEXT: mr 3, 5 |
| 2398 | ; PPC64LE-NEXT: lwsync |
| 2399 | ; PPC64LE-NEXT: blr |
| 2400 | %ret = atomicrmw xchg i64* %ptr, i64 %val acq_rel |
| 2401 | ret i64 %ret |
| 2402 | } |
| 2403 | |
| 2404 | define i64 @test139(i64* %ptr, i64 %val) { |
| 2405 | ; PPC64LE-LABEL: test139: |
| 2406 | ; PPC64LE: # BB#0: |
| 2407 | ; PPC64LE-NEXT: sync |
| 2408 | ; PPC64LE-NEXT: .LBB139_1: |
| 2409 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 2410 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 2411 | ; PPC64LE-NEXT: bne 0, .LBB139_1 |
| 2412 | ; PPC64LE-NEXT: # BB#2: |
| 2413 | ; PPC64LE-NEXT: mr 3, 5 |
| 2414 | ; PPC64LE-NEXT: lwsync |
| 2415 | ; PPC64LE-NEXT: blr |
| 2416 | %ret = atomicrmw xchg i64* %ptr, i64 %val seq_cst |
| 2417 | ret i64 %ret |
| 2418 | } |
| 2419 | |
| 2420 | define i8 @test140(i8* %ptr, i8 %val) { |
| 2421 | ; PPC64LE-LABEL: test140: |
| 2422 | ; PPC64LE: # BB#0: |
| 2423 | ; PPC64LE-NEXT: .LBB140_1: |
| 2424 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 2425 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2426 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 2427 | ; PPC64LE-NEXT: bne 0, .LBB140_1 |
| 2428 | ; PPC64LE-NEXT: # BB#2: |
| 2429 | ; PPC64LE-NEXT: mr 3, 5 |
| 2430 | ; PPC64LE-NEXT: blr |
| 2431 | %ret = atomicrmw add i8* %ptr, i8 %val monotonic |
| 2432 | ret i8 %ret |
| 2433 | } |
| 2434 | |
| 2435 | define i8 @test141(i8* %ptr, i8 %val) { |
| 2436 | ; PPC64LE-LABEL: test141: |
| 2437 | ; PPC64LE: # BB#0: |
| 2438 | ; PPC64LE-NEXT: mr 5, 3 |
| 2439 | ; PPC64LE-NEXT: .LBB141_1: |
| 2440 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 2441 | ; PPC64LE-NEXT: add 6, 4, 3 |
| 2442 | ; PPC64LE-NEXT: stbcx. 6, 0, 5 |
| 2443 | ; PPC64LE-NEXT: bne 0, .LBB141_1 |
| 2444 | ; PPC64LE-NEXT: # BB#2: |
| 2445 | ; PPC64LE-NEXT: lwsync |
| 2446 | ; PPC64LE-NEXT: blr |
| 2447 | %ret = atomicrmw add i8* %ptr, i8 %val acquire |
| 2448 | ret i8 %ret |
| 2449 | } |
| 2450 | |
| 2451 | define i8 @test142(i8* %ptr, i8 %val) { |
| 2452 | ; PPC64LE-LABEL: test142: |
| 2453 | ; PPC64LE: # BB#0: |
| 2454 | ; PPC64LE-NEXT: lwsync |
| 2455 | ; PPC64LE-NEXT: .LBB142_1: |
| 2456 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 2457 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2458 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 2459 | ; PPC64LE-NEXT: bne 0, .LBB142_1 |
| 2460 | ; PPC64LE-NEXT: # BB#2: |
| 2461 | ; PPC64LE-NEXT: mr 3, 5 |
| 2462 | ; PPC64LE-NEXT: blr |
| 2463 | %ret = atomicrmw add i8* %ptr, i8 %val release |
| 2464 | ret i8 %ret |
| 2465 | } |
| 2466 | |
| 2467 | define i8 @test143(i8* %ptr, i8 %val) { |
| 2468 | ; PPC64LE-LABEL: test143: |
| 2469 | ; PPC64LE: # BB#0: |
| 2470 | ; PPC64LE-NEXT: lwsync |
| 2471 | ; PPC64LE-NEXT: .LBB143_1: |
| 2472 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 2473 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2474 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 2475 | ; PPC64LE-NEXT: bne 0, .LBB143_1 |
| 2476 | ; PPC64LE-NEXT: # BB#2: |
| 2477 | ; PPC64LE-NEXT: mr 3, 5 |
| 2478 | ; PPC64LE-NEXT: lwsync |
| 2479 | ; PPC64LE-NEXT: blr |
| 2480 | %ret = atomicrmw add i8* %ptr, i8 %val acq_rel |
| 2481 | ret i8 %ret |
| 2482 | } |
| 2483 | |
| 2484 | define i8 @test144(i8* %ptr, i8 %val) { |
| 2485 | ; PPC64LE-LABEL: test144: |
| 2486 | ; PPC64LE: # BB#0: |
| 2487 | ; PPC64LE-NEXT: sync |
| 2488 | ; PPC64LE-NEXT: .LBB144_1: |
| 2489 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 2490 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2491 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 2492 | ; PPC64LE-NEXT: bne 0, .LBB144_1 |
| 2493 | ; PPC64LE-NEXT: # BB#2: |
| 2494 | ; PPC64LE-NEXT: mr 3, 5 |
| 2495 | ; PPC64LE-NEXT: lwsync |
| 2496 | ; PPC64LE-NEXT: blr |
| 2497 | %ret = atomicrmw add i8* %ptr, i8 %val seq_cst |
| 2498 | ret i8 %ret |
| 2499 | } |
| 2500 | |
| 2501 | define i16 @test145(i16* %ptr, i16 %val) { |
| 2502 | ; PPC64LE-LABEL: test145: |
| 2503 | ; PPC64LE: # BB#0: |
| 2504 | ; PPC64LE-NEXT: .LBB145_1: |
| 2505 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 2506 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2507 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 2508 | ; PPC64LE-NEXT: bne 0, .LBB145_1 |
| 2509 | ; PPC64LE-NEXT: # BB#2: |
| 2510 | ; PPC64LE-NEXT: mr 3, 5 |
| 2511 | ; PPC64LE-NEXT: blr |
| 2512 | %ret = atomicrmw add i16* %ptr, i16 %val monotonic |
| 2513 | ret i16 %ret |
| 2514 | } |
| 2515 | |
| 2516 | define i16 @test146(i16* %ptr, i16 %val) { |
| 2517 | ; PPC64LE-LABEL: test146: |
| 2518 | ; PPC64LE: # BB#0: |
| 2519 | ; PPC64LE-NEXT: mr 5, 3 |
| 2520 | ; PPC64LE-NEXT: .LBB146_1: |
| 2521 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 2522 | ; PPC64LE-NEXT: add 6, 4, 3 |
| 2523 | ; PPC64LE-NEXT: sthcx. 6, 0, 5 |
| 2524 | ; PPC64LE-NEXT: bne 0, .LBB146_1 |
| 2525 | ; PPC64LE-NEXT: # BB#2: |
| 2526 | ; PPC64LE-NEXT: lwsync |
| 2527 | ; PPC64LE-NEXT: blr |
| 2528 | %ret = atomicrmw add i16* %ptr, i16 %val acquire |
| 2529 | ret i16 %ret |
| 2530 | } |
| 2531 | |
| 2532 | define i16 @test147(i16* %ptr, i16 %val) { |
| 2533 | ; PPC64LE-LABEL: test147: |
| 2534 | ; PPC64LE: # BB#0: |
| 2535 | ; PPC64LE-NEXT: lwsync |
| 2536 | ; PPC64LE-NEXT: .LBB147_1: |
| 2537 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 2538 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2539 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 2540 | ; PPC64LE-NEXT: bne 0, .LBB147_1 |
| 2541 | ; PPC64LE-NEXT: # BB#2: |
| 2542 | ; PPC64LE-NEXT: mr 3, 5 |
| 2543 | ; PPC64LE-NEXT: blr |
| 2544 | %ret = atomicrmw add i16* %ptr, i16 %val release |
| 2545 | ret i16 %ret |
| 2546 | } |
| 2547 | |
| 2548 | define i16 @test148(i16* %ptr, i16 %val) { |
| 2549 | ; PPC64LE-LABEL: test148: |
| 2550 | ; PPC64LE: # BB#0: |
| 2551 | ; PPC64LE-NEXT: lwsync |
| 2552 | ; PPC64LE-NEXT: .LBB148_1: |
| 2553 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 2554 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2555 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 2556 | ; PPC64LE-NEXT: bne 0, .LBB148_1 |
| 2557 | ; PPC64LE-NEXT: # BB#2: |
| 2558 | ; PPC64LE-NEXT: mr 3, 5 |
| 2559 | ; PPC64LE-NEXT: lwsync |
| 2560 | ; PPC64LE-NEXT: blr |
| 2561 | %ret = atomicrmw add i16* %ptr, i16 %val acq_rel |
| 2562 | ret i16 %ret |
| 2563 | } |
| 2564 | |
| 2565 | define i16 @test149(i16* %ptr, i16 %val) { |
| 2566 | ; PPC64LE-LABEL: test149: |
| 2567 | ; PPC64LE: # BB#0: |
| 2568 | ; PPC64LE-NEXT: sync |
| 2569 | ; PPC64LE-NEXT: .LBB149_1: |
| 2570 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 2571 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2572 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 2573 | ; PPC64LE-NEXT: bne 0, .LBB149_1 |
| 2574 | ; PPC64LE-NEXT: # BB#2: |
| 2575 | ; PPC64LE-NEXT: mr 3, 5 |
| 2576 | ; PPC64LE-NEXT: lwsync |
| 2577 | ; PPC64LE-NEXT: blr |
| 2578 | %ret = atomicrmw add i16* %ptr, i16 %val seq_cst |
| 2579 | ret i16 %ret |
| 2580 | } |
| 2581 | |
| 2582 | define i32 @test150(i32* %ptr, i32 %val) { |
| 2583 | ; PPC64LE-LABEL: test150: |
| 2584 | ; PPC64LE: # BB#0: |
| 2585 | ; PPC64LE-NEXT: .LBB150_1: |
| 2586 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 2587 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2588 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 2589 | ; PPC64LE-NEXT: bne 0, .LBB150_1 |
| 2590 | ; PPC64LE-NEXT: # BB#2: |
| 2591 | ; PPC64LE-NEXT: mr 3, 5 |
| 2592 | ; PPC64LE-NEXT: blr |
| 2593 | %ret = atomicrmw add i32* %ptr, i32 %val monotonic |
| 2594 | ret i32 %ret |
| 2595 | } |
| 2596 | |
| 2597 | define i32 @test151(i32* %ptr, i32 %val) { |
| 2598 | ; PPC64LE-LABEL: test151: |
| 2599 | ; PPC64LE: # BB#0: |
| 2600 | ; PPC64LE-NEXT: mr 5, 3 |
| 2601 | ; PPC64LE-NEXT: .LBB151_1: |
| 2602 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 2603 | ; PPC64LE-NEXT: add 6, 4, 3 |
| 2604 | ; PPC64LE-NEXT: stwcx. 6, 0, 5 |
| 2605 | ; PPC64LE-NEXT: bne 0, .LBB151_1 |
| 2606 | ; PPC64LE-NEXT: # BB#2: |
| 2607 | ; PPC64LE-NEXT: lwsync |
| 2608 | ; PPC64LE-NEXT: blr |
| 2609 | %ret = atomicrmw add i32* %ptr, i32 %val acquire |
| 2610 | ret i32 %ret |
| 2611 | } |
| 2612 | |
| 2613 | define i32 @test152(i32* %ptr, i32 %val) { |
| 2614 | ; PPC64LE-LABEL: test152: |
| 2615 | ; PPC64LE: # BB#0: |
| 2616 | ; PPC64LE-NEXT: lwsync |
| 2617 | ; PPC64LE-NEXT: .LBB152_1: |
| 2618 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 2619 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2620 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 2621 | ; PPC64LE-NEXT: bne 0, .LBB152_1 |
| 2622 | ; PPC64LE-NEXT: # BB#2: |
| 2623 | ; PPC64LE-NEXT: mr 3, 5 |
| 2624 | ; PPC64LE-NEXT: blr |
| 2625 | %ret = atomicrmw add i32* %ptr, i32 %val release |
| 2626 | ret i32 %ret |
| 2627 | } |
| 2628 | |
| 2629 | define i32 @test153(i32* %ptr, i32 %val) { |
| 2630 | ; PPC64LE-LABEL: test153: |
| 2631 | ; PPC64LE: # BB#0: |
| 2632 | ; PPC64LE-NEXT: lwsync |
| 2633 | ; PPC64LE-NEXT: .LBB153_1: |
| 2634 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 2635 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2636 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 2637 | ; PPC64LE-NEXT: bne 0, .LBB153_1 |
| 2638 | ; PPC64LE-NEXT: # BB#2: |
| 2639 | ; PPC64LE-NEXT: mr 3, 5 |
| 2640 | ; PPC64LE-NEXT: lwsync |
| 2641 | ; PPC64LE-NEXT: blr |
| 2642 | %ret = atomicrmw add i32* %ptr, i32 %val acq_rel |
| 2643 | ret i32 %ret |
| 2644 | } |
| 2645 | |
| 2646 | define i32 @test154(i32* %ptr, i32 %val) { |
| 2647 | ; PPC64LE-LABEL: test154: |
| 2648 | ; PPC64LE: # BB#0: |
| 2649 | ; PPC64LE-NEXT: sync |
| 2650 | ; PPC64LE-NEXT: .LBB154_1: |
| 2651 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 2652 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2653 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 2654 | ; PPC64LE-NEXT: bne 0, .LBB154_1 |
| 2655 | ; PPC64LE-NEXT: # BB#2: |
| 2656 | ; PPC64LE-NEXT: mr 3, 5 |
| 2657 | ; PPC64LE-NEXT: lwsync |
| 2658 | ; PPC64LE-NEXT: blr |
| 2659 | %ret = atomicrmw add i32* %ptr, i32 %val seq_cst |
| 2660 | ret i32 %ret |
| 2661 | } |
| 2662 | |
| 2663 | define i64 @test155(i64* %ptr, i64 %val) { |
| 2664 | ; PPC64LE-LABEL: test155: |
| 2665 | ; PPC64LE: # BB#0: |
| 2666 | ; PPC64LE-NEXT: .LBB155_1: |
| 2667 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 2668 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2669 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 2670 | ; PPC64LE-NEXT: bne 0, .LBB155_1 |
| 2671 | ; PPC64LE-NEXT: # BB#2: |
| 2672 | ; PPC64LE-NEXT: mr 3, 5 |
| 2673 | ; PPC64LE-NEXT: blr |
| 2674 | %ret = atomicrmw add i64* %ptr, i64 %val monotonic |
| 2675 | ret i64 %ret |
| 2676 | } |
| 2677 | |
| 2678 | define i64 @test156(i64* %ptr, i64 %val) { |
| 2679 | ; PPC64LE-LABEL: test156: |
| 2680 | ; PPC64LE: # BB#0: |
| 2681 | ; PPC64LE-NEXT: mr 5, 3 |
| 2682 | ; PPC64LE-NEXT: .LBB156_1: |
| 2683 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 2684 | ; PPC64LE-NEXT: add 6, 4, 3 |
| 2685 | ; PPC64LE-NEXT: stdcx. 6, 0, 5 |
| 2686 | ; PPC64LE-NEXT: bne 0, .LBB156_1 |
| 2687 | ; PPC64LE-NEXT: # BB#2: |
| 2688 | ; PPC64LE-NEXT: lwsync |
| 2689 | ; PPC64LE-NEXT: blr |
| 2690 | %ret = atomicrmw add i64* %ptr, i64 %val acquire |
| 2691 | ret i64 %ret |
| 2692 | } |
| 2693 | |
| 2694 | define i64 @test157(i64* %ptr, i64 %val) { |
| 2695 | ; PPC64LE-LABEL: test157: |
| 2696 | ; PPC64LE: # BB#0: |
| 2697 | ; PPC64LE-NEXT: lwsync |
| 2698 | ; PPC64LE-NEXT: .LBB157_1: |
| 2699 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 2700 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2701 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 2702 | ; PPC64LE-NEXT: bne 0, .LBB157_1 |
| 2703 | ; PPC64LE-NEXT: # BB#2: |
| 2704 | ; PPC64LE-NEXT: mr 3, 5 |
| 2705 | ; PPC64LE-NEXT: blr |
| 2706 | %ret = atomicrmw add i64* %ptr, i64 %val release |
| 2707 | ret i64 %ret |
| 2708 | } |
| 2709 | |
| 2710 | define i64 @test158(i64* %ptr, i64 %val) { |
| 2711 | ; PPC64LE-LABEL: test158: |
| 2712 | ; PPC64LE: # BB#0: |
| 2713 | ; PPC64LE-NEXT: lwsync |
| 2714 | ; PPC64LE-NEXT: .LBB158_1: |
| 2715 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 2716 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2717 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 2718 | ; PPC64LE-NEXT: bne 0, .LBB158_1 |
| 2719 | ; PPC64LE-NEXT: # BB#2: |
| 2720 | ; PPC64LE-NEXT: mr 3, 5 |
| 2721 | ; PPC64LE-NEXT: lwsync |
| 2722 | ; PPC64LE-NEXT: blr |
| 2723 | %ret = atomicrmw add i64* %ptr, i64 %val acq_rel |
| 2724 | ret i64 %ret |
| 2725 | } |
| 2726 | |
| 2727 | define i64 @test159(i64* %ptr, i64 %val) { |
| 2728 | ; PPC64LE-LABEL: test159: |
| 2729 | ; PPC64LE: # BB#0: |
| 2730 | ; PPC64LE-NEXT: sync |
| 2731 | ; PPC64LE-NEXT: .LBB159_1: |
| 2732 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 2733 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 2734 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 2735 | ; PPC64LE-NEXT: bne 0, .LBB159_1 |
| 2736 | ; PPC64LE-NEXT: # BB#2: |
| 2737 | ; PPC64LE-NEXT: mr 3, 5 |
| 2738 | ; PPC64LE-NEXT: lwsync |
| 2739 | ; PPC64LE-NEXT: blr |
| 2740 | %ret = atomicrmw add i64* %ptr, i64 %val seq_cst |
| 2741 | ret i64 %ret |
| 2742 | } |
| 2743 | |
| 2744 | define i8 @test160(i8* %ptr, i8 %val) { |
| 2745 | ; PPC64LE-LABEL: test160: |
| 2746 | ; PPC64LE: # BB#0: |
| 2747 | ; PPC64LE-NEXT: .LBB160_1: |
| 2748 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 2749 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 2750 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 2751 | ; PPC64LE-NEXT: bne 0, .LBB160_1 |
| 2752 | ; PPC64LE-NEXT: # BB#2: |
| 2753 | ; PPC64LE-NEXT: mr 3, 5 |
| 2754 | ; PPC64LE-NEXT: blr |
| 2755 | %ret = atomicrmw sub i8* %ptr, i8 %val monotonic |
| 2756 | ret i8 %ret |
| 2757 | } |
| 2758 | |
| 2759 | define i8 @test161(i8* %ptr, i8 %val) { |
| 2760 | ; PPC64LE-LABEL: test161: |
| 2761 | ; PPC64LE: # BB#0: |
| 2762 | ; PPC64LE-NEXT: mr 5, 3 |
| 2763 | ; PPC64LE-NEXT: .LBB161_1: |
| 2764 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 2765 | ; PPC64LE-NEXT: subf 6, 4, 3 |
| 2766 | ; PPC64LE-NEXT: stbcx. 6, 0, 5 |
| 2767 | ; PPC64LE-NEXT: bne 0, .LBB161_1 |
| 2768 | ; PPC64LE-NEXT: # BB#2: |
| 2769 | ; PPC64LE-NEXT: lwsync |
| 2770 | ; PPC64LE-NEXT: blr |
| 2771 | %ret = atomicrmw sub i8* %ptr, i8 %val acquire |
| 2772 | ret i8 %ret |
| 2773 | } |
| 2774 | |
| 2775 | define i8 @test162(i8* %ptr, i8 %val) { |
| 2776 | ; PPC64LE-LABEL: test162: |
| 2777 | ; PPC64LE: # BB#0: |
| 2778 | ; PPC64LE-NEXT: lwsync |
| 2779 | ; PPC64LE-NEXT: .LBB162_1: |
| 2780 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 2781 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 2782 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 2783 | ; PPC64LE-NEXT: bne 0, .LBB162_1 |
| 2784 | ; PPC64LE-NEXT: # BB#2: |
| 2785 | ; PPC64LE-NEXT: mr 3, 5 |
| 2786 | ; PPC64LE-NEXT: blr |
| 2787 | %ret = atomicrmw sub i8* %ptr, i8 %val release |
| 2788 | ret i8 %ret |
| 2789 | } |
| 2790 | |
| 2791 | define i8 @test163(i8* %ptr, i8 %val) { |
| 2792 | ; PPC64LE-LABEL: test163: |
| 2793 | ; PPC64LE: # BB#0: |
| 2794 | ; PPC64LE-NEXT: lwsync |
| 2795 | ; PPC64LE-NEXT: .LBB163_1: |
| 2796 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 2797 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 2798 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 2799 | ; PPC64LE-NEXT: bne 0, .LBB163_1 |
| 2800 | ; PPC64LE-NEXT: # BB#2: |
| 2801 | ; PPC64LE-NEXT: mr 3, 5 |
| 2802 | ; PPC64LE-NEXT: lwsync |
| 2803 | ; PPC64LE-NEXT: blr |
| 2804 | %ret = atomicrmw sub i8* %ptr, i8 %val acq_rel |
| 2805 | ret i8 %ret |
| 2806 | } |
| 2807 | |
| 2808 | define i8 @test164(i8* %ptr, i8 %val) { |
| 2809 | ; PPC64LE-LABEL: test164: |
| 2810 | ; PPC64LE: # BB#0: |
| 2811 | ; PPC64LE-NEXT: sync |
| 2812 | ; PPC64LE-NEXT: .LBB164_1: |
| 2813 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 2814 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 2815 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 2816 | ; PPC64LE-NEXT: bne 0, .LBB164_1 |
| 2817 | ; PPC64LE-NEXT: # BB#2: |
| 2818 | ; PPC64LE-NEXT: mr 3, 5 |
| 2819 | ; PPC64LE-NEXT: lwsync |
| 2820 | ; PPC64LE-NEXT: blr |
| 2821 | %ret = atomicrmw sub i8* %ptr, i8 %val seq_cst |
| 2822 | ret i8 %ret |
| 2823 | } |
| 2824 | |
| 2825 | define i16 @test165(i16* %ptr, i16 %val) { |
| 2826 | ; PPC64LE-LABEL: test165: |
| 2827 | ; PPC64LE: # BB#0: |
| 2828 | ; PPC64LE-NEXT: .LBB165_1: |
| 2829 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 2830 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 2831 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 2832 | ; PPC64LE-NEXT: bne 0, .LBB165_1 |
| 2833 | ; PPC64LE-NEXT: # BB#2: |
| 2834 | ; PPC64LE-NEXT: mr 3, 5 |
| 2835 | ; PPC64LE-NEXT: blr |
| 2836 | %ret = atomicrmw sub i16* %ptr, i16 %val monotonic |
| 2837 | ret i16 %ret |
| 2838 | } |
| 2839 | |
| 2840 | define i16 @test166(i16* %ptr, i16 %val) { |
| 2841 | ; PPC64LE-LABEL: test166: |
| 2842 | ; PPC64LE: # BB#0: |
| 2843 | ; PPC64LE-NEXT: mr 5, 3 |
| 2844 | ; PPC64LE-NEXT: .LBB166_1: |
| 2845 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 2846 | ; PPC64LE-NEXT: subf 6, 4, 3 |
| 2847 | ; PPC64LE-NEXT: sthcx. 6, 0, 5 |
| 2848 | ; PPC64LE-NEXT: bne 0, .LBB166_1 |
| 2849 | ; PPC64LE-NEXT: # BB#2: |
| 2850 | ; PPC64LE-NEXT: lwsync |
| 2851 | ; PPC64LE-NEXT: blr |
| 2852 | %ret = atomicrmw sub i16* %ptr, i16 %val acquire |
| 2853 | ret i16 %ret |
| 2854 | } |
| 2855 | |
| 2856 | define i16 @test167(i16* %ptr, i16 %val) { |
| 2857 | ; PPC64LE-LABEL: test167: |
| 2858 | ; PPC64LE: # BB#0: |
| 2859 | ; PPC64LE-NEXT: lwsync |
| 2860 | ; PPC64LE-NEXT: .LBB167_1: |
| 2861 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 2862 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 2863 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 2864 | ; PPC64LE-NEXT: bne 0, .LBB167_1 |
| 2865 | ; PPC64LE-NEXT: # BB#2: |
| 2866 | ; PPC64LE-NEXT: mr 3, 5 |
| 2867 | ; PPC64LE-NEXT: blr |
| 2868 | %ret = atomicrmw sub i16* %ptr, i16 %val release |
| 2869 | ret i16 %ret |
| 2870 | } |
| 2871 | |
| 2872 | define i16 @test168(i16* %ptr, i16 %val) { |
| 2873 | ; PPC64LE-LABEL: test168: |
| 2874 | ; PPC64LE: # BB#0: |
| 2875 | ; PPC64LE-NEXT: lwsync |
| 2876 | ; PPC64LE-NEXT: .LBB168_1: |
| 2877 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 2878 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 2879 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 2880 | ; PPC64LE-NEXT: bne 0, .LBB168_1 |
| 2881 | ; PPC64LE-NEXT: # BB#2: |
| 2882 | ; PPC64LE-NEXT: mr 3, 5 |
| 2883 | ; PPC64LE-NEXT: lwsync |
| 2884 | ; PPC64LE-NEXT: blr |
| 2885 | %ret = atomicrmw sub i16* %ptr, i16 %val acq_rel |
| 2886 | ret i16 %ret |
| 2887 | } |
| 2888 | |
| 2889 | define i16 @test169(i16* %ptr, i16 %val) { |
| 2890 | ; PPC64LE-LABEL: test169: |
| 2891 | ; PPC64LE: # BB#0: |
| 2892 | ; PPC64LE-NEXT: sync |
| 2893 | ; PPC64LE-NEXT: .LBB169_1: |
| 2894 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 2895 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 2896 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 2897 | ; PPC64LE-NEXT: bne 0, .LBB169_1 |
| 2898 | ; PPC64LE-NEXT: # BB#2: |
| 2899 | ; PPC64LE-NEXT: mr 3, 5 |
| 2900 | ; PPC64LE-NEXT: lwsync |
| 2901 | ; PPC64LE-NEXT: blr |
| 2902 | %ret = atomicrmw sub i16* %ptr, i16 %val seq_cst |
| 2903 | ret i16 %ret |
| 2904 | } |
| 2905 | |
| 2906 | define i32 @test170(i32* %ptr, i32 %val) { |
| 2907 | ; PPC64LE-LABEL: test170: |
| 2908 | ; PPC64LE: # BB#0: |
| 2909 | ; PPC64LE-NEXT: .LBB170_1: |
| 2910 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 2911 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 2912 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 2913 | ; PPC64LE-NEXT: bne 0, .LBB170_1 |
| 2914 | ; PPC64LE-NEXT: # BB#2: |
| 2915 | ; PPC64LE-NEXT: mr 3, 5 |
| 2916 | ; PPC64LE-NEXT: blr |
| 2917 | %ret = atomicrmw sub i32* %ptr, i32 %val monotonic |
| 2918 | ret i32 %ret |
| 2919 | } |
| 2920 | |
| 2921 | define i32 @test171(i32* %ptr, i32 %val) { |
| 2922 | ; PPC64LE-LABEL: test171: |
| 2923 | ; PPC64LE: # BB#0: |
| 2924 | ; PPC64LE-NEXT: mr 5, 3 |
| 2925 | ; PPC64LE-NEXT: .LBB171_1: |
| 2926 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 2927 | ; PPC64LE-NEXT: subf 6, 4, 3 |
| 2928 | ; PPC64LE-NEXT: stwcx. 6, 0, 5 |
| 2929 | ; PPC64LE-NEXT: bne 0, .LBB171_1 |
| 2930 | ; PPC64LE-NEXT: # BB#2: |
| 2931 | ; PPC64LE-NEXT: lwsync |
| 2932 | ; PPC64LE-NEXT: blr |
| 2933 | %ret = atomicrmw sub i32* %ptr, i32 %val acquire |
| 2934 | ret i32 %ret |
| 2935 | } |
| 2936 | |
| 2937 | define i32 @test172(i32* %ptr, i32 %val) { |
| 2938 | ; PPC64LE-LABEL: test172: |
| 2939 | ; PPC64LE: # BB#0: |
| 2940 | ; PPC64LE-NEXT: lwsync |
| 2941 | ; PPC64LE-NEXT: .LBB172_1: |
| 2942 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 2943 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 2944 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 2945 | ; PPC64LE-NEXT: bne 0, .LBB172_1 |
| 2946 | ; PPC64LE-NEXT: # BB#2: |
| 2947 | ; PPC64LE-NEXT: mr 3, 5 |
| 2948 | ; PPC64LE-NEXT: blr |
| 2949 | %ret = atomicrmw sub i32* %ptr, i32 %val release |
| 2950 | ret i32 %ret |
| 2951 | } |
| 2952 | |
| 2953 | define i32 @test173(i32* %ptr, i32 %val) { |
| 2954 | ; PPC64LE-LABEL: test173: |
| 2955 | ; PPC64LE: # BB#0: |
| 2956 | ; PPC64LE-NEXT: lwsync |
| 2957 | ; PPC64LE-NEXT: .LBB173_1: |
| 2958 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 2959 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 2960 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 2961 | ; PPC64LE-NEXT: bne 0, .LBB173_1 |
| 2962 | ; PPC64LE-NEXT: # BB#2: |
| 2963 | ; PPC64LE-NEXT: mr 3, 5 |
| 2964 | ; PPC64LE-NEXT: lwsync |
| 2965 | ; PPC64LE-NEXT: blr |
| 2966 | %ret = atomicrmw sub i32* %ptr, i32 %val acq_rel |
| 2967 | ret i32 %ret |
| 2968 | } |
| 2969 | |
| 2970 | define i32 @test174(i32* %ptr, i32 %val) { |
| 2971 | ; PPC64LE-LABEL: test174: |
| 2972 | ; PPC64LE: # BB#0: |
| 2973 | ; PPC64LE-NEXT: sync |
| 2974 | ; PPC64LE-NEXT: .LBB174_1: |
| 2975 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 2976 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 2977 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 2978 | ; PPC64LE-NEXT: bne 0, .LBB174_1 |
| 2979 | ; PPC64LE-NEXT: # BB#2: |
| 2980 | ; PPC64LE-NEXT: mr 3, 5 |
| 2981 | ; PPC64LE-NEXT: lwsync |
| 2982 | ; PPC64LE-NEXT: blr |
| 2983 | %ret = atomicrmw sub i32* %ptr, i32 %val seq_cst |
| 2984 | ret i32 %ret |
| 2985 | } |
| 2986 | |
| 2987 | define i64 @test175(i64* %ptr, i64 %val) { |
| 2988 | ; PPC64LE-LABEL: test175: |
| 2989 | ; PPC64LE: # BB#0: |
| 2990 | ; PPC64LE-NEXT: .LBB175_1: |
| 2991 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 2992 | ; PPC64LE-NEXT: sub 6, 5, 4 |
| 2993 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 2994 | ; PPC64LE-NEXT: bne 0, .LBB175_1 |
| 2995 | ; PPC64LE-NEXT: # BB#2: |
| 2996 | ; PPC64LE-NEXT: mr 3, 5 |
| 2997 | ; PPC64LE-NEXT: blr |
| 2998 | %ret = atomicrmw sub i64* %ptr, i64 %val monotonic |
| 2999 | ret i64 %ret |
| 3000 | } |
| 3001 | |
| 3002 | define i64 @test176(i64* %ptr, i64 %val) { |
| 3003 | ; PPC64LE-LABEL: test176: |
| 3004 | ; PPC64LE: # BB#0: |
| 3005 | ; PPC64LE-NEXT: mr 5, 3 |
| 3006 | ; PPC64LE-NEXT: .LBB176_1: |
| 3007 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 3008 | ; PPC64LE-NEXT: sub 6, 3, 4 |
| 3009 | ; PPC64LE-NEXT: stdcx. 6, 0, 5 |
| 3010 | ; PPC64LE-NEXT: bne 0, .LBB176_1 |
| 3011 | ; PPC64LE-NEXT: # BB#2: |
| 3012 | ; PPC64LE-NEXT: lwsync |
| 3013 | ; PPC64LE-NEXT: blr |
| 3014 | %ret = atomicrmw sub i64* %ptr, i64 %val acquire |
| 3015 | ret i64 %ret |
| 3016 | } |
| 3017 | |
| 3018 | define i64 @test177(i64* %ptr, i64 %val) { |
| 3019 | ; PPC64LE-LABEL: test177: |
| 3020 | ; PPC64LE: # BB#0: |
| 3021 | ; PPC64LE-NEXT: lwsync |
| 3022 | ; PPC64LE-NEXT: .LBB177_1: |
| 3023 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3024 | ; PPC64LE-NEXT: sub 6, 5, 4 |
| 3025 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3026 | ; PPC64LE-NEXT: bne 0, .LBB177_1 |
| 3027 | ; PPC64LE-NEXT: # BB#2: |
| 3028 | ; PPC64LE-NEXT: mr 3, 5 |
| 3029 | ; PPC64LE-NEXT: blr |
| 3030 | %ret = atomicrmw sub i64* %ptr, i64 %val release |
| 3031 | ret i64 %ret |
| 3032 | } |
| 3033 | |
| 3034 | define i64 @test178(i64* %ptr, i64 %val) { |
| 3035 | ; PPC64LE-LABEL: test178: |
| 3036 | ; PPC64LE: # BB#0: |
| 3037 | ; PPC64LE-NEXT: lwsync |
| 3038 | ; PPC64LE-NEXT: .LBB178_1: |
| 3039 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3040 | ; PPC64LE-NEXT: sub 6, 5, 4 |
| 3041 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3042 | ; PPC64LE-NEXT: bne 0, .LBB178_1 |
| 3043 | ; PPC64LE-NEXT: # BB#2: |
| 3044 | ; PPC64LE-NEXT: mr 3, 5 |
| 3045 | ; PPC64LE-NEXT: lwsync |
| 3046 | ; PPC64LE-NEXT: blr |
| 3047 | %ret = atomicrmw sub i64* %ptr, i64 %val acq_rel |
| 3048 | ret i64 %ret |
| 3049 | } |
| 3050 | |
| 3051 | define i64 @test179(i64* %ptr, i64 %val) { |
| 3052 | ; PPC64LE-LABEL: test179: |
| 3053 | ; PPC64LE: # BB#0: |
| 3054 | ; PPC64LE-NEXT: sync |
| 3055 | ; PPC64LE-NEXT: .LBB179_1: |
| 3056 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3057 | ; PPC64LE-NEXT: sub 6, 5, 4 |
| 3058 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3059 | ; PPC64LE-NEXT: bne 0, .LBB179_1 |
| 3060 | ; PPC64LE-NEXT: # BB#2: |
| 3061 | ; PPC64LE-NEXT: mr 3, 5 |
| 3062 | ; PPC64LE-NEXT: lwsync |
| 3063 | ; PPC64LE-NEXT: blr |
| 3064 | %ret = atomicrmw sub i64* %ptr, i64 %val seq_cst |
| 3065 | ret i64 %ret |
| 3066 | } |
| 3067 | |
| 3068 | define i8 @test180(i8* %ptr, i8 %val) { |
| 3069 | ; PPC64LE-LABEL: test180: |
| 3070 | ; PPC64LE: # BB#0: |
| 3071 | ; PPC64LE-NEXT: .LBB180_1: |
| 3072 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 3073 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3074 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 3075 | ; PPC64LE-NEXT: bne 0, .LBB180_1 |
| 3076 | ; PPC64LE-NEXT: # BB#2: |
| 3077 | ; PPC64LE-NEXT: mr 3, 5 |
| 3078 | ; PPC64LE-NEXT: blr |
| 3079 | %ret = atomicrmw and i8* %ptr, i8 %val monotonic |
| 3080 | ret i8 %ret |
| 3081 | } |
| 3082 | |
| 3083 | define i8 @test181(i8* %ptr, i8 %val) { |
| 3084 | ; PPC64LE-LABEL: test181: |
| 3085 | ; PPC64LE: # BB#0: |
| 3086 | ; PPC64LE-NEXT: mr 5, 3 |
| 3087 | ; PPC64LE-NEXT: .LBB181_1: |
| 3088 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 3089 | ; PPC64LE-NEXT: and 6, 4, 3 |
| 3090 | ; PPC64LE-NEXT: stbcx. 6, 0, 5 |
| 3091 | ; PPC64LE-NEXT: bne 0, .LBB181_1 |
| 3092 | ; PPC64LE-NEXT: # BB#2: |
| 3093 | ; PPC64LE-NEXT: lwsync |
| 3094 | ; PPC64LE-NEXT: blr |
| 3095 | %ret = atomicrmw and i8* %ptr, i8 %val acquire |
| 3096 | ret i8 %ret |
| 3097 | } |
| 3098 | |
| 3099 | define i8 @test182(i8* %ptr, i8 %val) { |
| 3100 | ; PPC64LE-LABEL: test182: |
| 3101 | ; PPC64LE: # BB#0: |
| 3102 | ; PPC64LE-NEXT: lwsync |
| 3103 | ; PPC64LE-NEXT: .LBB182_1: |
| 3104 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 3105 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3106 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 3107 | ; PPC64LE-NEXT: bne 0, .LBB182_1 |
| 3108 | ; PPC64LE-NEXT: # BB#2: |
| 3109 | ; PPC64LE-NEXT: mr 3, 5 |
| 3110 | ; PPC64LE-NEXT: blr |
| 3111 | %ret = atomicrmw and i8* %ptr, i8 %val release |
| 3112 | ret i8 %ret |
| 3113 | } |
| 3114 | |
| 3115 | define i8 @test183(i8* %ptr, i8 %val) { |
| 3116 | ; PPC64LE-LABEL: test183: |
| 3117 | ; PPC64LE: # BB#0: |
| 3118 | ; PPC64LE-NEXT: lwsync |
| 3119 | ; PPC64LE-NEXT: .LBB183_1: |
| 3120 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 3121 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3122 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 3123 | ; PPC64LE-NEXT: bne 0, .LBB183_1 |
| 3124 | ; PPC64LE-NEXT: # BB#2: |
| 3125 | ; PPC64LE-NEXT: mr 3, 5 |
| 3126 | ; PPC64LE-NEXT: lwsync |
| 3127 | ; PPC64LE-NEXT: blr |
| 3128 | %ret = atomicrmw and i8* %ptr, i8 %val acq_rel |
| 3129 | ret i8 %ret |
| 3130 | } |
| 3131 | |
| 3132 | define i8 @test184(i8* %ptr, i8 %val) { |
| 3133 | ; PPC64LE-LABEL: test184: |
| 3134 | ; PPC64LE: # BB#0: |
| 3135 | ; PPC64LE-NEXT: sync |
| 3136 | ; PPC64LE-NEXT: .LBB184_1: |
| 3137 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 3138 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3139 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 3140 | ; PPC64LE-NEXT: bne 0, .LBB184_1 |
| 3141 | ; PPC64LE-NEXT: # BB#2: |
| 3142 | ; PPC64LE-NEXT: mr 3, 5 |
| 3143 | ; PPC64LE-NEXT: lwsync |
| 3144 | ; PPC64LE-NEXT: blr |
| 3145 | %ret = atomicrmw and i8* %ptr, i8 %val seq_cst |
| 3146 | ret i8 %ret |
| 3147 | } |
| 3148 | |
| 3149 | define i16 @test185(i16* %ptr, i16 %val) { |
| 3150 | ; PPC64LE-LABEL: test185: |
| 3151 | ; PPC64LE: # BB#0: |
| 3152 | ; PPC64LE-NEXT: .LBB185_1: |
| 3153 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 3154 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3155 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 3156 | ; PPC64LE-NEXT: bne 0, .LBB185_1 |
| 3157 | ; PPC64LE-NEXT: # BB#2: |
| 3158 | ; PPC64LE-NEXT: mr 3, 5 |
| 3159 | ; PPC64LE-NEXT: blr |
| 3160 | %ret = atomicrmw and i16* %ptr, i16 %val monotonic |
| 3161 | ret i16 %ret |
| 3162 | } |
| 3163 | |
| 3164 | define i16 @test186(i16* %ptr, i16 %val) { |
| 3165 | ; PPC64LE-LABEL: test186: |
| 3166 | ; PPC64LE: # BB#0: |
| 3167 | ; PPC64LE-NEXT: mr 5, 3 |
| 3168 | ; PPC64LE-NEXT: .LBB186_1: |
| 3169 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 3170 | ; PPC64LE-NEXT: and 6, 4, 3 |
| 3171 | ; PPC64LE-NEXT: sthcx. 6, 0, 5 |
| 3172 | ; PPC64LE-NEXT: bne 0, .LBB186_1 |
| 3173 | ; PPC64LE-NEXT: # BB#2: |
| 3174 | ; PPC64LE-NEXT: lwsync |
| 3175 | ; PPC64LE-NEXT: blr |
| 3176 | %ret = atomicrmw and i16* %ptr, i16 %val acquire |
| 3177 | ret i16 %ret |
| 3178 | } |
| 3179 | |
| 3180 | define i16 @test187(i16* %ptr, i16 %val) { |
| 3181 | ; PPC64LE-LABEL: test187: |
| 3182 | ; PPC64LE: # BB#0: |
| 3183 | ; PPC64LE-NEXT: lwsync |
| 3184 | ; PPC64LE-NEXT: .LBB187_1: |
| 3185 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 3186 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3187 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 3188 | ; PPC64LE-NEXT: bne 0, .LBB187_1 |
| 3189 | ; PPC64LE-NEXT: # BB#2: |
| 3190 | ; PPC64LE-NEXT: mr 3, 5 |
| 3191 | ; PPC64LE-NEXT: blr |
| 3192 | %ret = atomicrmw and i16* %ptr, i16 %val release |
| 3193 | ret i16 %ret |
| 3194 | } |
| 3195 | |
| 3196 | define i16 @test188(i16* %ptr, i16 %val) { |
| 3197 | ; PPC64LE-LABEL: test188: |
| 3198 | ; PPC64LE: # BB#0: |
| 3199 | ; PPC64LE-NEXT: lwsync |
| 3200 | ; PPC64LE-NEXT: .LBB188_1: |
| 3201 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 3202 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3203 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 3204 | ; PPC64LE-NEXT: bne 0, .LBB188_1 |
| 3205 | ; PPC64LE-NEXT: # BB#2: |
| 3206 | ; PPC64LE-NEXT: mr 3, 5 |
| 3207 | ; PPC64LE-NEXT: lwsync |
| 3208 | ; PPC64LE-NEXT: blr |
| 3209 | %ret = atomicrmw and i16* %ptr, i16 %val acq_rel |
| 3210 | ret i16 %ret |
| 3211 | } |
| 3212 | |
| 3213 | define i16 @test189(i16* %ptr, i16 %val) { |
| 3214 | ; PPC64LE-LABEL: test189: |
| 3215 | ; PPC64LE: # BB#0: |
| 3216 | ; PPC64LE-NEXT: sync |
| 3217 | ; PPC64LE-NEXT: .LBB189_1: |
| 3218 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 3219 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3220 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 3221 | ; PPC64LE-NEXT: bne 0, .LBB189_1 |
| 3222 | ; PPC64LE-NEXT: # BB#2: |
| 3223 | ; PPC64LE-NEXT: mr 3, 5 |
| 3224 | ; PPC64LE-NEXT: lwsync |
| 3225 | ; PPC64LE-NEXT: blr |
| 3226 | %ret = atomicrmw and i16* %ptr, i16 %val seq_cst |
| 3227 | ret i16 %ret |
| 3228 | } |
| 3229 | |
| 3230 | define i32 @test190(i32* %ptr, i32 %val) { |
| 3231 | ; PPC64LE-LABEL: test190: |
| 3232 | ; PPC64LE: # BB#0: |
| 3233 | ; PPC64LE-NEXT: .LBB190_1: |
| 3234 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 3235 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3236 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 3237 | ; PPC64LE-NEXT: bne 0, .LBB190_1 |
| 3238 | ; PPC64LE-NEXT: # BB#2: |
| 3239 | ; PPC64LE-NEXT: mr 3, 5 |
| 3240 | ; PPC64LE-NEXT: blr |
| 3241 | %ret = atomicrmw and i32* %ptr, i32 %val monotonic |
| 3242 | ret i32 %ret |
| 3243 | } |
| 3244 | |
| 3245 | define i32 @test191(i32* %ptr, i32 %val) { |
| 3246 | ; PPC64LE-LABEL: test191: |
| 3247 | ; PPC64LE: # BB#0: |
| 3248 | ; PPC64LE-NEXT: mr 5, 3 |
| 3249 | ; PPC64LE-NEXT: .LBB191_1: |
| 3250 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 3251 | ; PPC64LE-NEXT: and 6, 4, 3 |
| 3252 | ; PPC64LE-NEXT: stwcx. 6, 0, 5 |
| 3253 | ; PPC64LE-NEXT: bne 0, .LBB191_1 |
| 3254 | ; PPC64LE-NEXT: # BB#2: |
| 3255 | ; PPC64LE-NEXT: lwsync |
| 3256 | ; PPC64LE-NEXT: blr |
| 3257 | %ret = atomicrmw and i32* %ptr, i32 %val acquire |
| 3258 | ret i32 %ret |
| 3259 | } |
| 3260 | |
| 3261 | define i32 @test192(i32* %ptr, i32 %val) { |
| 3262 | ; PPC64LE-LABEL: test192: |
| 3263 | ; PPC64LE: # BB#0: |
| 3264 | ; PPC64LE-NEXT: lwsync |
| 3265 | ; PPC64LE-NEXT: .LBB192_1: |
| 3266 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 3267 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3268 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 3269 | ; PPC64LE-NEXT: bne 0, .LBB192_1 |
| 3270 | ; PPC64LE-NEXT: # BB#2: |
| 3271 | ; PPC64LE-NEXT: mr 3, 5 |
| 3272 | ; PPC64LE-NEXT: blr |
| 3273 | %ret = atomicrmw and i32* %ptr, i32 %val release |
| 3274 | ret i32 %ret |
| 3275 | } |
| 3276 | |
| 3277 | define i32 @test193(i32* %ptr, i32 %val) { |
| 3278 | ; PPC64LE-LABEL: test193: |
| 3279 | ; PPC64LE: # BB#0: |
| 3280 | ; PPC64LE-NEXT: lwsync |
| 3281 | ; PPC64LE-NEXT: .LBB193_1: |
| 3282 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 3283 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3284 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 3285 | ; PPC64LE-NEXT: bne 0, .LBB193_1 |
| 3286 | ; PPC64LE-NEXT: # BB#2: |
| 3287 | ; PPC64LE-NEXT: mr 3, 5 |
| 3288 | ; PPC64LE-NEXT: lwsync |
| 3289 | ; PPC64LE-NEXT: blr |
| 3290 | %ret = atomicrmw and i32* %ptr, i32 %val acq_rel |
| 3291 | ret i32 %ret |
| 3292 | } |
| 3293 | |
| 3294 | define i32 @test194(i32* %ptr, i32 %val) { |
| 3295 | ; PPC64LE-LABEL: test194: |
| 3296 | ; PPC64LE: # BB#0: |
| 3297 | ; PPC64LE-NEXT: sync |
| 3298 | ; PPC64LE-NEXT: .LBB194_1: |
| 3299 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 3300 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3301 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 3302 | ; PPC64LE-NEXT: bne 0, .LBB194_1 |
| 3303 | ; PPC64LE-NEXT: # BB#2: |
| 3304 | ; PPC64LE-NEXT: mr 3, 5 |
| 3305 | ; PPC64LE-NEXT: lwsync |
| 3306 | ; PPC64LE-NEXT: blr |
| 3307 | %ret = atomicrmw and i32* %ptr, i32 %val seq_cst |
| 3308 | ret i32 %ret |
| 3309 | } |
| 3310 | |
| 3311 | define i64 @test195(i64* %ptr, i64 %val) { |
| 3312 | ; PPC64LE-LABEL: test195: |
| 3313 | ; PPC64LE: # BB#0: |
| 3314 | ; PPC64LE-NEXT: .LBB195_1: |
| 3315 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3316 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3317 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3318 | ; PPC64LE-NEXT: bne 0, .LBB195_1 |
| 3319 | ; PPC64LE-NEXT: # BB#2: |
| 3320 | ; PPC64LE-NEXT: mr 3, 5 |
| 3321 | ; PPC64LE-NEXT: blr |
| 3322 | %ret = atomicrmw and i64* %ptr, i64 %val monotonic |
| 3323 | ret i64 %ret |
| 3324 | } |
| 3325 | |
| 3326 | define i64 @test196(i64* %ptr, i64 %val) { |
| 3327 | ; PPC64LE-LABEL: test196: |
| 3328 | ; PPC64LE: # BB#0: |
| 3329 | ; PPC64LE-NEXT: mr 5, 3 |
| 3330 | ; PPC64LE-NEXT: .LBB196_1: |
| 3331 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 3332 | ; PPC64LE-NEXT: and 6, 4, 3 |
| 3333 | ; PPC64LE-NEXT: stdcx. 6, 0, 5 |
| 3334 | ; PPC64LE-NEXT: bne 0, .LBB196_1 |
| 3335 | ; PPC64LE-NEXT: # BB#2: |
| 3336 | ; PPC64LE-NEXT: lwsync |
| 3337 | ; PPC64LE-NEXT: blr |
| 3338 | %ret = atomicrmw and i64* %ptr, i64 %val acquire |
| 3339 | ret i64 %ret |
| 3340 | } |
| 3341 | |
| 3342 | define i64 @test197(i64* %ptr, i64 %val) { |
| 3343 | ; PPC64LE-LABEL: test197: |
| 3344 | ; PPC64LE: # BB#0: |
| 3345 | ; PPC64LE-NEXT: lwsync |
| 3346 | ; PPC64LE-NEXT: .LBB197_1: |
| 3347 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3348 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3349 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3350 | ; PPC64LE-NEXT: bne 0, .LBB197_1 |
| 3351 | ; PPC64LE-NEXT: # BB#2: |
| 3352 | ; PPC64LE-NEXT: mr 3, 5 |
| 3353 | ; PPC64LE-NEXT: blr |
| 3354 | %ret = atomicrmw and i64* %ptr, i64 %val release |
| 3355 | ret i64 %ret |
| 3356 | } |
| 3357 | |
| 3358 | define i64 @test198(i64* %ptr, i64 %val) { |
| 3359 | ; PPC64LE-LABEL: test198: |
| 3360 | ; PPC64LE: # BB#0: |
| 3361 | ; PPC64LE-NEXT: lwsync |
| 3362 | ; PPC64LE-NEXT: .LBB198_1: |
| 3363 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3364 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3365 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3366 | ; PPC64LE-NEXT: bne 0, .LBB198_1 |
| 3367 | ; PPC64LE-NEXT: # BB#2: |
| 3368 | ; PPC64LE-NEXT: mr 3, 5 |
| 3369 | ; PPC64LE-NEXT: lwsync |
| 3370 | ; PPC64LE-NEXT: blr |
| 3371 | %ret = atomicrmw and i64* %ptr, i64 %val acq_rel |
| 3372 | ret i64 %ret |
| 3373 | } |
| 3374 | |
| 3375 | define i64 @test199(i64* %ptr, i64 %val) { |
| 3376 | ; PPC64LE-LABEL: test199: |
| 3377 | ; PPC64LE: # BB#0: |
| 3378 | ; PPC64LE-NEXT: sync |
| 3379 | ; PPC64LE-NEXT: .LBB199_1: |
| 3380 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3381 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 3382 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3383 | ; PPC64LE-NEXT: bne 0, .LBB199_1 |
| 3384 | ; PPC64LE-NEXT: # BB#2: |
| 3385 | ; PPC64LE-NEXT: mr 3, 5 |
| 3386 | ; PPC64LE-NEXT: lwsync |
| 3387 | ; PPC64LE-NEXT: blr |
| 3388 | %ret = atomicrmw and i64* %ptr, i64 %val seq_cst |
| 3389 | ret i64 %ret |
| 3390 | } |
| 3391 | |
| 3392 | define i8 @test200(i8* %ptr, i8 %val) { |
| 3393 | ; PPC64LE-LABEL: test200: |
| 3394 | ; PPC64LE: # BB#0: |
| 3395 | ; PPC64LE-NEXT: .LBB200_1: |
| 3396 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 3397 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3398 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 3399 | ; PPC64LE-NEXT: bne 0, .LBB200_1 |
| 3400 | ; PPC64LE-NEXT: # BB#2: |
| 3401 | ; PPC64LE-NEXT: mr 3, 5 |
| 3402 | ; PPC64LE-NEXT: blr |
| 3403 | %ret = atomicrmw nand i8* %ptr, i8 %val monotonic |
| 3404 | ret i8 %ret |
| 3405 | } |
| 3406 | |
| 3407 | define i8 @test201(i8* %ptr, i8 %val) { |
| 3408 | ; PPC64LE-LABEL: test201: |
| 3409 | ; PPC64LE: # BB#0: |
| 3410 | ; PPC64LE-NEXT: mr 5, 3 |
| 3411 | ; PPC64LE-NEXT: .LBB201_1: |
| 3412 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 3413 | ; PPC64LE-NEXT: nand 6, 4, 3 |
| 3414 | ; PPC64LE-NEXT: stbcx. 6, 0, 5 |
| 3415 | ; PPC64LE-NEXT: bne 0, .LBB201_1 |
| 3416 | ; PPC64LE-NEXT: # BB#2: |
| 3417 | ; PPC64LE-NEXT: lwsync |
| 3418 | ; PPC64LE-NEXT: blr |
| 3419 | %ret = atomicrmw nand i8* %ptr, i8 %val acquire |
| 3420 | ret i8 %ret |
| 3421 | } |
| 3422 | |
| 3423 | define i8 @test202(i8* %ptr, i8 %val) { |
| 3424 | ; PPC64LE-LABEL: test202: |
| 3425 | ; PPC64LE: # BB#0: |
| 3426 | ; PPC64LE-NEXT: lwsync |
| 3427 | ; PPC64LE-NEXT: .LBB202_1: |
| 3428 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 3429 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3430 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 3431 | ; PPC64LE-NEXT: bne 0, .LBB202_1 |
| 3432 | ; PPC64LE-NEXT: # BB#2: |
| 3433 | ; PPC64LE-NEXT: mr 3, 5 |
| 3434 | ; PPC64LE-NEXT: blr |
| 3435 | %ret = atomicrmw nand i8* %ptr, i8 %val release |
| 3436 | ret i8 %ret |
| 3437 | } |
| 3438 | |
| 3439 | define i8 @test203(i8* %ptr, i8 %val) { |
| 3440 | ; PPC64LE-LABEL: test203: |
| 3441 | ; PPC64LE: # BB#0: |
| 3442 | ; PPC64LE-NEXT: lwsync |
| 3443 | ; PPC64LE-NEXT: .LBB203_1: |
| 3444 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 3445 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3446 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 3447 | ; PPC64LE-NEXT: bne 0, .LBB203_1 |
| 3448 | ; PPC64LE-NEXT: # BB#2: |
| 3449 | ; PPC64LE-NEXT: mr 3, 5 |
| 3450 | ; PPC64LE-NEXT: lwsync |
| 3451 | ; PPC64LE-NEXT: blr |
| 3452 | %ret = atomicrmw nand i8* %ptr, i8 %val acq_rel |
| 3453 | ret i8 %ret |
| 3454 | } |
| 3455 | |
| 3456 | define i8 @test204(i8* %ptr, i8 %val) { |
| 3457 | ; PPC64LE-LABEL: test204: |
| 3458 | ; PPC64LE: # BB#0: |
| 3459 | ; PPC64LE-NEXT: sync |
| 3460 | ; PPC64LE-NEXT: .LBB204_1: |
| 3461 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 3462 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3463 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 3464 | ; PPC64LE-NEXT: bne 0, .LBB204_1 |
| 3465 | ; PPC64LE-NEXT: # BB#2: |
| 3466 | ; PPC64LE-NEXT: mr 3, 5 |
| 3467 | ; PPC64LE-NEXT: lwsync |
| 3468 | ; PPC64LE-NEXT: blr |
| 3469 | %ret = atomicrmw nand i8* %ptr, i8 %val seq_cst |
| 3470 | ret i8 %ret |
| 3471 | } |
| 3472 | |
| 3473 | define i16 @test205(i16* %ptr, i16 %val) { |
| 3474 | ; PPC64LE-LABEL: test205: |
| 3475 | ; PPC64LE: # BB#0: |
| 3476 | ; PPC64LE-NEXT: .LBB205_1: |
| 3477 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 3478 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3479 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 3480 | ; PPC64LE-NEXT: bne 0, .LBB205_1 |
| 3481 | ; PPC64LE-NEXT: # BB#2: |
| 3482 | ; PPC64LE-NEXT: mr 3, 5 |
| 3483 | ; PPC64LE-NEXT: blr |
| 3484 | %ret = atomicrmw nand i16* %ptr, i16 %val monotonic |
| 3485 | ret i16 %ret |
| 3486 | } |
| 3487 | |
| 3488 | define i16 @test206(i16* %ptr, i16 %val) { |
| 3489 | ; PPC64LE-LABEL: test206: |
| 3490 | ; PPC64LE: # BB#0: |
| 3491 | ; PPC64LE-NEXT: mr 5, 3 |
| 3492 | ; PPC64LE-NEXT: .LBB206_1: |
| 3493 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 3494 | ; PPC64LE-NEXT: nand 6, 4, 3 |
| 3495 | ; PPC64LE-NEXT: sthcx. 6, 0, 5 |
| 3496 | ; PPC64LE-NEXT: bne 0, .LBB206_1 |
| 3497 | ; PPC64LE-NEXT: # BB#2: |
| 3498 | ; PPC64LE-NEXT: lwsync |
| 3499 | ; PPC64LE-NEXT: blr |
| 3500 | %ret = atomicrmw nand i16* %ptr, i16 %val acquire |
| 3501 | ret i16 %ret |
| 3502 | } |
| 3503 | |
| 3504 | define i16 @test207(i16* %ptr, i16 %val) { |
| 3505 | ; PPC64LE-LABEL: test207: |
| 3506 | ; PPC64LE: # BB#0: |
| 3507 | ; PPC64LE-NEXT: lwsync |
| 3508 | ; PPC64LE-NEXT: .LBB207_1: |
| 3509 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 3510 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3511 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 3512 | ; PPC64LE-NEXT: bne 0, .LBB207_1 |
| 3513 | ; PPC64LE-NEXT: # BB#2: |
| 3514 | ; PPC64LE-NEXT: mr 3, 5 |
| 3515 | ; PPC64LE-NEXT: blr |
| 3516 | %ret = atomicrmw nand i16* %ptr, i16 %val release |
| 3517 | ret i16 %ret |
| 3518 | } |
| 3519 | |
| 3520 | define i16 @test208(i16* %ptr, i16 %val) { |
| 3521 | ; PPC64LE-LABEL: test208: |
| 3522 | ; PPC64LE: # BB#0: |
| 3523 | ; PPC64LE-NEXT: lwsync |
| 3524 | ; PPC64LE-NEXT: .LBB208_1: |
| 3525 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 3526 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3527 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 3528 | ; PPC64LE-NEXT: bne 0, .LBB208_1 |
| 3529 | ; PPC64LE-NEXT: # BB#2: |
| 3530 | ; PPC64LE-NEXT: mr 3, 5 |
| 3531 | ; PPC64LE-NEXT: lwsync |
| 3532 | ; PPC64LE-NEXT: blr |
| 3533 | %ret = atomicrmw nand i16* %ptr, i16 %val acq_rel |
| 3534 | ret i16 %ret |
| 3535 | } |
| 3536 | |
| 3537 | define i16 @test209(i16* %ptr, i16 %val) { |
| 3538 | ; PPC64LE-LABEL: test209: |
| 3539 | ; PPC64LE: # BB#0: |
| 3540 | ; PPC64LE-NEXT: sync |
| 3541 | ; PPC64LE-NEXT: .LBB209_1: |
| 3542 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 3543 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3544 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 3545 | ; PPC64LE-NEXT: bne 0, .LBB209_1 |
| 3546 | ; PPC64LE-NEXT: # BB#2: |
| 3547 | ; PPC64LE-NEXT: mr 3, 5 |
| 3548 | ; PPC64LE-NEXT: lwsync |
| 3549 | ; PPC64LE-NEXT: blr |
| 3550 | %ret = atomicrmw nand i16* %ptr, i16 %val seq_cst |
| 3551 | ret i16 %ret |
| 3552 | } |
| 3553 | |
| 3554 | define i32 @test210(i32* %ptr, i32 %val) { |
| 3555 | ; PPC64LE-LABEL: test210: |
| 3556 | ; PPC64LE: # BB#0: |
| 3557 | ; PPC64LE-NEXT: .LBB210_1: |
| 3558 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 3559 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3560 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 3561 | ; PPC64LE-NEXT: bne 0, .LBB210_1 |
| 3562 | ; PPC64LE-NEXT: # BB#2: |
| 3563 | ; PPC64LE-NEXT: mr 3, 5 |
| 3564 | ; PPC64LE-NEXT: blr |
| 3565 | %ret = atomicrmw nand i32* %ptr, i32 %val monotonic |
| 3566 | ret i32 %ret |
| 3567 | } |
| 3568 | |
| 3569 | define i32 @test211(i32* %ptr, i32 %val) { |
| 3570 | ; PPC64LE-LABEL: test211: |
| 3571 | ; PPC64LE: # BB#0: |
| 3572 | ; PPC64LE-NEXT: mr 5, 3 |
| 3573 | ; PPC64LE-NEXT: .LBB211_1: |
| 3574 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 3575 | ; PPC64LE-NEXT: nand 6, 4, 3 |
| 3576 | ; PPC64LE-NEXT: stwcx. 6, 0, 5 |
| 3577 | ; PPC64LE-NEXT: bne 0, .LBB211_1 |
| 3578 | ; PPC64LE-NEXT: # BB#2: |
| 3579 | ; PPC64LE-NEXT: lwsync |
| 3580 | ; PPC64LE-NEXT: blr |
| 3581 | %ret = atomicrmw nand i32* %ptr, i32 %val acquire |
| 3582 | ret i32 %ret |
| 3583 | } |
| 3584 | |
| 3585 | define i32 @test212(i32* %ptr, i32 %val) { |
| 3586 | ; PPC64LE-LABEL: test212: |
| 3587 | ; PPC64LE: # BB#0: |
| 3588 | ; PPC64LE-NEXT: lwsync |
| 3589 | ; PPC64LE-NEXT: .LBB212_1: |
| 3590 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 3591 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3592 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 3593 | ; PPC64LE-NEXT: bne 0, .LBB212_1 |
| 3594 | ; PPC64LE-NEXT: # BB#2: |
| 3595 | ; PPC64LE-NEXT: mr 3, 5 |
| 3596 | ; PPC64LE-NEXT: blr |
| 3597 | %ret = atomicrmw nand i32* %ptr, i32 %val release |
| 3598 | ret i32 %ret |
| 3599 | } |
| 3600 | |
| 3601 | define i32 @test213(i32* %ptr, i32 %val) { |
| 3602 | ; PPC64LE-LABEL: test213: |
| 3603 | ; PPC64LE: # BB#0: |
| 3604 | ; PPC64LE-NEXT: lwsync |
| 3605 | ; PPC64LE-NEXT: .LBB213_1: |
| 3606 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 3607 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3608 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 3609 | ; PPC64LE-NEXT: bne 0, .LBB213_1 |
| 3610 | ; PPC64LE-NEXT: # BB#2: |
| 3611 | ; PPC64LE-NEXT: mr 3, 5 |
| 3612 | ; PPC64LE-NEXT: lwsync |
| 3613 | ; PPC64LE-NEXT: blr |
| 3614 | %ret = atomicrmw nand i32* %ptr, i32 %val acq_rel |
| 3615 | ret i32 %ret |
| 3616 | } |
| 3617 | |
| 3618 | define i32 @test214(i32* %ptr, i32 %val) { |
| 3619 | ; PPC64LE-LABEL: test214: |
| 3620 | ; PPC64LE: # BB#0: |
| 3621 | ; PPC64LE-NEXT: sync |
| 3622 | ; PPC64LE-NEXT: .LBB214_1: |
| 3623 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 3624 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3625 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 3626 | ; PPC64LE-NEXT: bne 0, .LBB214_1 |
| 3627 | ; PPC64LE-NEXT: # BB#2: |
| 3628 | ; PPC64LE-NEXT: mr 3, 5 |
| 3629 | ; PPC64LE-NEXT: lwsync |
| 3630 | ; PPC64LE-NEXT: blr |
| 3631 | %ret = atomicrmw nand i32* %ptr, i32 %val seq_cst |
| 3632 | ret i32 %ret |
| 3633 | } |
| 3634 | |
| 3635 | define i64 @test215(i64* %ptr, i64 %val) { |
| 3636 | ; PPC64LE-LABEL: test215: |
| 3637 | ; PPC64LE: # BB#0: |
| 3638 | ; PPC64LE-NEXT: .LBB215_1: |
| 3639 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3640 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3641 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3642 | ; PPC64LE-NEXT: bne 0, .LBB215_1 |
| 3643 | ; PPC64LE-NEXT: # BB#2: |
| 3644 | ; PPC64LE-NEXT: mr 3, 5 |
| 3645 | ; PPC64LE-NEXT: blr |
| 3646 | %ret = atomicrmw nand i64* %ptr, i64 %val monotonic |
| 3647 | ret i64 %ret |
| 3648 | } |
| 3649 | |
| 3650 | define i64 @test216(i64* %ptr, i64 %val) { |
| 3651 | ; PPC64LE-LABEL: test216: |
| 3652 | ; PPC64LE: # BB#0: |
| 3653 | ; PPC64LE-NEXT: mr 5, 3 |
| 3654 | ; PPC64LE-NEXT: .LBB216_1: |
| 3655 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 3656 | ; PPC64LE-NEXT: nand 6, 4, 3 |
| 3657 | ; PPC64LE-NEXT: stdcx. 6, 0, 5 |
| 3658 | ; PPC64LE-NEXT: bne 0, .LBB216_1 |
| 3659 | ; PPC64LE-NEXT: # BB#2: |
| 3660 | ; PPC64LE-NEXT: lwsync |
| 3661 | ; PPC64LE-NEXT: blr |
| 3662 | %ret = atomicrmw nand i64* %ptr, i64 %val acquire |
| 3663 | ret i64 %ret |
| 3664 | } |
| 3665 | |
| 3666 | define i64 @test217(i64* %ptr, i64 %val) { |
| 3667 | ; PPC64LE-LABEL: test217: |
| 3668 | ; PPC64LE: # BB#0: |
| 3669 | ; PPC64LE-NEXT: lwsync |
| 3670 | ; PPC64LE-NEXT: .LBB217_1: |
| 3671 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3672 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3673 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3674 | ; PPC64LE-NEXT: bne 0, .LBB217_1 |
| 3675 | ; PPC64LE-NEXT: # BB#2: |
| 3676 | ; PPC64LE-NEXT: mr 3, 5 |
| 3677 | ; PPC64LE-NEXT: blr |
| 3678 | %ret = atomicrmw nand i64* %ptr, i64 %val release |
| 3679 | ret i64 %ret |
| 3680 | } |
| 3681 | |
| 3682 | define i64 @test218(i64* %ptr, i64 %val) { |
| 3683 | ; PPC64LE-LABEL: test218: |
| 3684 | ; PPC64LE: # BB#0: |
| 3685 | ; PPC64LE-NEXT: lwsync |
| 3686 | ; PPC64LE-NEXT: .LBB218_1: |
| 3687 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3688 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3689 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3690 | ; PPC64LE-NEXT: bne 0, .LBB218_1 |
| 3691 | ; PPC64LE-NEXT: # BB#2: |
| 3692 | ; PPC64LE-NEXT: mr 3, 5 |
| 3693 | ; PPC64LE-NEXT: lwsync |
| 3694 | ; PPC64LE-NEXT: blr |
| 3695 | %ret = atomicrmw nand i64* %ptr, i64 %val acq_rel |
| 3696 | ret i64 %ret |
| 3697 | } |
| 3698 | |
| 3699 | define i64 @test219(i64* %ptr, i64 %val) { |
| 3700 | ; PPC64LE-LABEL: test219: |
| 3701 | ; PPC64LE: # BB#0: |
| 3702 | ; PPC64LE-NEXT: sync |
| 3703 | ; PPC64LE-NEXT: .LBB219_1: |
| 3704 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3705 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 3706 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3707 | ; PPC64LE-NEXT: bne 0, .LBB219_1 |
| 3708 | ; PPC64LE-NEXT: # BB#2: |
| 3709 | ; PPC64LE-NEXT: mr 3, 5 |
| 3710 | ; PPC64LE-NEXT: lwsync |
| 3711 | ; PPC64LE-NEXT: blr |
| 3712 | %ret = atomicrmw nand i64* %ptr, i64 %val seq_cst |
| 3713 | ret i64 %ret |
| 3714 | } |
| 3715 | |
| 3716 | define i8 @test220(i8* %ptr, i8 %val) { |
| 3717 | ; PPC64LE-LABEL: test220: |
| 3718 | ; PPC64LE: # BB#0: |
| 3719 | ; PPC64LE-NEXT: .LBB220_1: |
| 3720 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 3721 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3722 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 3723 | ; PPC64LE-NEXT: bne 0, .LBB220_1 |
| 3724 | ; PPC64LE-NEXT: # BB#2: |
| 3725 | ; PPC64LE-NEXT: mr 3, 5 |
| 3726 | ; PPC64LE-NEXT: blr |
| 3727 | %ret = atomicrmw or i8* %ptr, i8 %val monotonic |
| 3728 | ret i8 %ret |
| 3729 | } |
| 3730 | |
| 3731 | define i8 @test221(i8* %ptr, i8 %val) { |
| 3732 | ; PPC64LE-LABEL: test221: |
| 3733 | ; PPC64LE: # BB#0: |
| 3734 | ; PPC64LE-NEXT: mr 5, 3 |
| 3735 | ; PPC64LE-NEXT: .LBB221_1: |
| 3736 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 3737 | ; PPC64LE-NEXT: or 6, 4, 3 |
| 3738 | ; PPC64LE-NEXT: stbcx. 6, 0, 5 |
| 3739 | ; PPC64LE-NEXT: bne 0, .LBB221_1 |
| 3740 | ; PPC64LE-NEXT: # BB#2: |
| 3741 | ; PPC64LE-NEXT: lwsync |
| 3742 | ; PPC64LE-NEXT: blr |
| 3743 | %ret = atomicrmw or i8* %ptr, i8 %val acquire |
| 3744 | ret i8 %ret |
| 3745 | } |
| 3746 | |
| 3747 | define i8 @test222(i8* %ptr, i8 %val) { |
| 3748 | ; PPC64LE-LABEL: test222: |
| 3749 | ; PPC64LE: # BB#0: |
| 3750 | ; PPC64LE-NEXT: lwsync |
| 3751 | ; PPC64LE-NEXT: .LBB222_1: |
| 3752 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 3753 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3754 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 3755 | ; PPC64LE-NEXT: bne 0, .LBB222_1 |
| 3756 | ; PPC64LE-NEXT: # BB#2: |
| 3757 | ; PPC64LE-NEXT: mr 3, 5 |
| 3758 | ; PPC64LE-NEXT: blr |
| 3759 | %ret = atomicrmw or i8* %ptr, i8 %val release |
| 3760 | ret i8 %ret |
| 3761 | } |
| 3762 | |
| 3763 | define i8 @test223(i8* %ptr, i8 %val) { |
| 3764 | ; PPC64LE-LABEL: test223: |
| 3765 | ; PPC64LE: # BB#0: |
| 3766 | ; PPC64LE-NEXT: lwsync |
| 3767 | ; PPC64LE-NEXT: .LBB223_1: |
| 3768 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 3769 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3770 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 3771 | ; PPC64LE-NEXT: bne 0, .LBB223_1 |
| 3772 | ; PPC64LE-NEXT: # BB#2: |
| 3773 | ; PPC64LE-NEXT: mr 3, 5 |
| 3774 | ; PPC64LE-NEXT: lwsync |
| 3775 | ; PPC64LE-NEXT: blr |
| 3776 | %ret = atomicrmw or i8* %ptr, i8 %val acq_rel |
| 3777 | ret i8 %ret |
| 3778 | } |
| 3779 | |
| 3780 | define i8 @test224(i8* %ptr, i8 %val) { |
| 3781 | ; PPC64LE-LABEL: test224: |
| 3782 | ; PPC64LE: # BB#0: |
| 3783 | ; PPC64LE-NEXT: sync |
| 3784 | ; PPC64LE-NEXT: .LBB224_1: |
| 3785 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 3786 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3787 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 3788 | ; PPC64LE-NEXT: bne 0, .LBB224_1 |
| 3789 | ; PPC64LE-NEXT: # BB#2: |
| 3790 | ; PPC64LE-NEXT: mr 3, 5 |
| 3791 | ; PPC64LE-NEXT: lwsync |
| 3792 | ; PPC64LE-NEXT: blr |
| 3793 | %ret = atomicrmw or i8* %ptr, i8 %val seq_cst |
| 3794 | ret i8 %ret |
| 3795 | } |
| 3796 | |
| 3797 | define i16 @test225(i16* %ptr, i16 %val) { |
| 3798 | ; PPC64LE-LABEL: test225: |
| 3799 | ; PPC64LE: # BB#0: |
| 3800 | ; PPC64LE-NEXT: .LBB225_1: |
| 3801 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 3802 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3803 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 3804 | ; PPC64LE-NEXT: bne 0, .LBB225_1 |
| 3805 | ; PPC64LE-NEXT: # BB#2: |
| 3806 | ; PPC64LE-NEXT: mr 3, 5 |
| 3807 | ; PPC64LE-NEXT: blr |
| 3808 | %ret = atomicrmw or i16* %ptr, i16 %val monotonic |
| 3809 | ret i16 %ret |
| 3810 | } |
| 3811 | |
| 3812 | define i16 @test226(i16* %ptr, i16 %val) { |
| 3813 | ; PPC64LE-LABEL: test226: |
| 3814 | ; PPC64LE: # BB#0: |
| 3815 | ; PPC64LE-NEXT: mr 5, 3 |
| 3816 | ; PPC64LE-NEXT: .LBB226_1: |
| 3817 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 3818 | ; PPC64LE-NEXT: or 6, 4, 3 |
| 3819 | ; PPC64LE-NEXT: sthcx. 6, 0, 5 |
| 3820 | ; PPC64LE-NEXT: bne 0, .LBB226_1 |
| 3821 | ; PPC64LE-NEXT: # BB#2: |
| 3822 | ; PPC64LE-NEXT: lwsync |
| 3823 | ; PPC64LE-NEXT: blr |
| 3824 | %ret = atomicrmw or i16* %ptr, i16 %val acquire |
| 3825 | ret i16 %ret |
| 3826 | } |
| 3827 | |
| 3828 | define i16 @test227(i16* %ptr, i16 %val) { |
| 3829 | ; PPC64LE-LABEL: test227: |
| 3830 | ; PPC64LE: # BB#0: |
| 3831 | ; PPC64LE-NEXT: lwsync |
| 3832 | ; PPC64LE-NEXT: .LBB227_1: |
| 3833 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 3834 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3835 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 3836 | ; PPC64LE-NEXT: bne 0, .LBB227_1 |
| 3837 | ; PPC64LE-NEXT: # BB#2: |
| 3838 | ; PPC64LE-NEXT: mr 3, 5 |
| 3839 | ; PPC64LE-NEXT: blr |
| 3840 | %ret = atomicrmw or i16* %ptr, i16 %val release |
| 3841 | ret i16 %ret |
| 3842 | } |
| 3843 | |
| 3844 | define i16 @test228(i16* %ptr, i16 %val) { |
| 3845 | ; PPC64LE-LABEL: test228: |
| 3846 | ; PPC64LE: # BB#0: |
| 3847 | ; PPC64LE-NEXT: lwsync |
| 3848 | ; PPC64LE-NEXT: .LBB228_1: |
| 3849 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 3850 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3851 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 3852 | ; PPC64LE-NEXT: bne 0, .LBB228_1 |
| 3853 | ; PPC64LE-NEXT: # BB#2: |
| 3854 | ; PPC64LE-NEXT: mr 3, 5 |
| 3855 | ; PPC64LE-NEXT: lwsync |
| 3856 | ; PPC64LE-NEXT: blr |
| 3857 | %ret = atomicrmw or i16* %ptr, i16 %val acq_rel |
| 3858 | ret i16 %ret |
| 3859 | } |
| 3860 | |
| 3861 | define i16 @test229(i16* %ptr, i16 %val) { |
| 3862 | ; PPC64LE-LABEL: test229: |
| 3863 | ; PPC64LE: # BB#0: |
| 3864 | ; PPC64LE-NEXT: sync |
| 3865 | ; PPC64LE-NEXT: .LBB229_1: |
| 3866 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 3867 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3868 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 3869 | ; PPC64LE-NEXT: bne 0, .LBB229_1 |
| 3870 | ; PPC64LE-NEXT: # BB#2: |
| 3871 | ; PPC64LE-NEXT: mr 3, 5 |
| 3872 | ; PPC64LE-NEXT: lwsync |
| 3873 | ; PPC64LE-NEXT: blr |
| 3874 | %ret = atomicrmw or i16* %ptr, i16 %val seq_cst |
| 3875 | ret i16 %ret |
| 3876 | } |
| 3877 | |
| 3878 | define i32 @test230(i32* %ptr, i32 %val) { |
| 3879 | ; PPC64LE-LABEL: test230: |
| 3880 | ; PPC64LE: # BB#0: |
| 3881 | ; PPC64LE-NEXT: .LBB230_1: |
| 3882 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 3883 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3884 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 3885 | ; PPC64LE-NEXT: bne 0, .LBB230_1 |
| 3886 | ; PPC64LE-NEXT: # BB#2: |
| 3887 | ; PPC64LE-NEXT: mr 3, 5 |
| 3888 | ; PPC64LE-NEXT: blr |
| 3889 | %ret = atomicrmw or i32* %ptr, i32 %val monotonic |
| 3890 | ret i32 %ret |
| 3891 | } |
| 3892 | |
| 3893 | define i32 @test231(i32* %ptr, i32 %val) { |
| 3894 | ; PPC64LE-LABEL: test231: |
| 3895 | ; PPC64LE: # BB#0: |
| 3896 | ; PPC64LE-NEXT: mr 5, 3 |
| 3897 | ; PPC64LE-NEXT: .LBB231_1: |
| 3898 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 3899 | ; PPC64LE-NEXT: or 6, 4, 3 |
| 3900 | ; PPC64LE-NEXT: stwcx. 6, 0, 5 |
| 3901 | ; PPC64LE-NEXT: bne 0, .LBB231_1 |
| 3902 | ; PPC64LE-NEXT: # BB#2: |
| 3903 | ; PPC64LE-NEXT: lwsync |
| 3904 | ; PPC64LE-NEXT: blr |
| 3905 | %ret = atomicrmw or i32* %ptr, i32 %val acquire |
| 3906 | ret i32 %ret |
| 3907 | } |
| 3908 | |
| 3909 | define i32 @test232(i32* %ptr, i32 %val) { |
| 3910 | ; PPC64LE-LABEL: test232: |
| 3911 | ; PPC64LE: # BB#0: |
| 3912 | ; PPC64LE-NEXT: lwsync |
| 3913 | ; PPC64LE-NEXT: .LBB232_1: |
| 3914 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 3915 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3916 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 3917 | ; PPC64LE-NEXT: bne 0, .LBB232_1 |
| 3918 | ; PPC64LE-NEXT: # BB#2: |
| 3919 | ; PPC64LE-NEXT: mr 3, 5 |
| 3920 | ; PPC64LE-NEXT: blr |
| 3921 | %ret = atomicrmw or i32* %ptr, i32 %val release |
| 3922 | ret i32 %ret |
| 3923 | } |
| 3924 | |
| 3925 | define i32 @test233(i32* %ptr, i32 %val) { |
| 3926 | ; PPC64LE-LABEL: test233: |
| 3927 | ; PPC64LE: # BB#0: |
| 3928 | ; PPC64LE-NEXT: lwsync |
| 3929 | ; PPC64LE-NEXT: .LBB233_1: |
| 3930 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 3931 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3932 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 3933 | ; PPC64LE-NEXT: bne 0, .LBB233_1 |
| 3934 | ; PPC64LE-NEXT: # BB#2: |
| 3935 | ; PPC64LE-NEXT: mr 3, 5 |
| 3936 | ; PPC64LE-NEXT: lwsync |
| 3937 | ; PPC64LE-NEXT: blr |
| 3938 | %ret = atomicrmw or i32* %ptr, i32 %val acq_rel |
| 3939 | ret i32 %ret |
| 3940 | } |
| 3941 | |
| 3942 | define i32 @test234(i32* %ptr, i32 %val) { |
| 3943 | ; PPC64LE-LABEL: test234: |
| 3944 | ; PPC64LE: # BB#0: |
| 3945 | ; PPC64LE-NEXT: sync |
| 3946 | ; PPC64LE-NEXT: .LBB234_1: |
| 3947 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 3948 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3949 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 3950 | ; PPC64LE-NEXT: bne 0, .LBB234_1 |
| 3951 | ; PPC64LE-NEXT: # BB#2: |
| 3952 | ; PPC64LE-NEXT: mr 3, 5 |
| 3953 | ; PPC64LE-NEXT: lwsync |
| 3954 | ; PPC64LE-NEXT: blr |
| 3955 | %ret = atomicrmw or i32* %ptr, i32 %val seq_cst |
| 3956 | ret i32 %ret |
| 3957 | } |
| 3958 | |
| 3959 | define i64 @test235(i64* %ptr, i64 %val) { |
| 3960 | ; PPC64LE-LABEL: test235: |
| 3961 | ; PPC64LE: # BB#0: |
| 3962 | ; PPC64LE-NEXT: .LBB235_1: |
| 3963 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3964 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3965 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3966 | ; PPC64LE-NEXT: bne 0, .LBB235_1 |
| 3967 | ; PPC64LE-NEXT: # BB#2: |
| 3968 | ; PPC64LE-NEXT: mr 3, 5 |
| 3969 | ; PPC64LE-NEXT: blr |
| 3970 | %ret = atomicrmw or i64* %ptr, i64 %val monotonic |
| 3971 | ret i64 %ret |
| 3972 | } |
| 3973 | |
| 3974 | define i64 @test236(i64* %ptr, i64 %val) { |
| 3975 | ; PPC64LE-LABEL: test236: |
| 3976 | ; PPC64LE: # BB#0: |
| 3977 | ; PPC64LE-NEXT: mr 5, 3 |
| 3978 | ; PPC64LE-NEXT: .LBB236_1: |
| 3979 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 3980 | ; PPC64LE-NEXT: or 6, 4, 3 |
| 3981 | ; PPC64LE-NEXT: stdcx. 6, 0, 5 |
| 3982 | ; PPC64LE-NEXT: bne 0, .LBB236_1 |
| 3983 | ; PPC64LE-NEXT: # BB#2: |
| 3984 | ; PPC64LE-NEXT: lwsync |
| 3985 | ; PPC64LE-NEXT: blr |
| 3986 | %ret = atomicrmw or i64* %ptr, i64 %val acquire |
| 3987 | ret i64 %ret |
| 3988 | } |
| 3989 | |
| 3990 | define i64 @test237(i64* %ptr, i64 %val) { |
| 3991 | ; PPC64LE-LABEL: test237: |
| 3992 | ; PPC64LE: # BB#0: |
| 3993 | ; PPC64LE-NEXT: lwsync |
| 3994 | ; PPC64LE-NEXT: .LBB237_1: |
| 3995 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 3996 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 3997 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 3998 | ; PPC64LE-NEXT: bne 0, .LBB237_1 |
| 3999 | ; PPC64LE-NEXT: # BB#2: |
| 4000 | ; PPC64LE-NEXT: mr 3, 5 |
| 4001 | ; PPC64LE-NEXT: blr |
| 4002 | %ret = atomicrmw or i64* %ptr, i64 %val release |
| 4003 | ret i64 %ret |
| 4004 | } |
| 4005 | |
| 4006 | define i64 @test238(i64* %ptr, i64 %val) { |
| 4007 | ; PPC64LE-LABEL: test238: |
| 4008 | ; PPC64LE: # BB#0: |
| 4009 | ; PPC64LE-NEXT: lwsync |
| 4010 | ; PPC64LE-NEXT: .LBB238_1: |
| 4011 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 4012 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 4013 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 4014 | ; PPC64LE-NEXT: bne 0, .LBB238_1 |
| 4015 | ; PPC64LE-NEXT: # BB#2: |
| 4016 | ; PPC64LE-NEXT: mr 3, 5 |
| 4017 | ; PPC64LE-NEXT: lwsync |
| 4018 | ; PPC64LE-NEXT: blr |
| 4019 | %ret = atomicrmw or i64* %ptr, i64 %val acq_rel |
| 4020 | ret i64 %ret |
| 4021 | } |
| 4022 | |
| 4023 | define i64 @test239(i64* %ptr, i64 %val) { |
| 4024 | ; PPC64LE-LABEL: test239: |
| 4025 | ; PPC64LE: # BB#0: |
| 4026 | ; PPC64LE-NEXT: sync |
| 4027 | ; PPC64LE-NEXT: .LBB239_1: |
| 4028 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 4029 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 4030 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 4031 | ; PPC64LE-NEXT: bne 0, .LBB239_1 |
| 4032 | ; PPC64LE-NEXT: # BB#2: |
| 4033 | ; PPC64LE-NEXT: mr 3, 5 |
| 4034 | ; PPC64LE-NEXT: lwsync |
| 4035 | ; PPC64LE-NEXT: blr |
| 4036 | %ret = atomicrmw or i64* %ptr, i64 %val seq_cst |
| 4037 | ret i64 %ret |
| 4038 | } |
| 4039 | |
| 4040 | define i8 @test240(i8* %ptr, i8 %val) { |
| 4041 | ; PPC64LE-LABEL: test240: |
| 4042 | ; PPC64LE: # BB#0: |
| 4043 | ; PPC64LE-NEXT: .LBB240_1: |
| 4044 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 4045 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4046 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 4047 | ; PPC64LE-NEXT: bne 0, .LBB240_1 |
| 4048 | ; PPC64LE-NEXT: # BB#2: |
| 4049 | ; PPC64LE-NEXT: mr 3, 5 |
| 4050 | ; PPC64LE-NEXT: blr |
| 4051 | %ret = atomicrmw xor i8* %ptr, i8 %val monotonic |
| 4052 | ret i8 %ret |
| 4053 | } |
| 4054 | |
| 4055 | define i8 @test241(i8* %ptr, i8 %val) { |
| 4056 | ; PPC64LE-LABEL: test241: |
| 4057 | ; PPC64LE: # BB#0: |
| 4058 | ; PPC64LE-NEXT: mr 5, 3 |
| 4059 | ; PPC64LE-NEXT: .LBB241_1: |
| 4060 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 4061 | ; PPC64LE-NEXT: xor 6, 4, 3 |
| 4062 | ; PPC64LE-NEXT: stbcx. 6, 0, 5 |
| 4063 | ; PPC64LE-NEXT: bne 0, .LBB241_1 |
| 4064 | ; PPC64LE-NEXT: # BB#2: |
| 4065 | ; PPC64LE-NEXT: lwsync |
| 4066 | ; PPC64LE-NEXT: blr |
| 4067 | %ret = atomicrmw xor i8* %ptr, i8 %val acquire |
| 4068 | ret i8 %ret |
| 4069 | } |
| 4070 | |
| 4071 | define i8 @test242(i8* %ptr, i8 %val) { |
| 4072 | ; PPC64LE-LABEL: test242: |
| 4073 | ; PPC64LE: # BB#0: |
| 4074 | ; PPC64LE-NEXT: lwsync |
| 4075 | ; PPC64LE-NEXT: .LBB242_1: |
| 4076 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 4077 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4078 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 4079 | ; PPC64LE-NEXT: bne 0, .LBB242_1 |
| 4080 | ; PPC64LE-NEXT: # BB#2: |
| 4081 | ; PPC64LE-NEXT: mr 3, 5 |
| 4082 | ; PPC64LE-NEXT: blr |
| 4083 | %ret = atomicrmw xor i8* %ptr, i8 %val release |
| 4084 | ret i8 %ret |
| 4085 | } |
| 4086 | |
| 4087 | define i8 @test243(i8* %ptr, i8 %val) { |
| 4088 | ; PPC64LE-LABEL: test243: |
| 4089 | ; PPC64LE: # BB#0: |
| 4090 | ; PPC64LE-NEXT: lwsync |
| 4091 | ; PPC64LE-NEXT: .LBB243_1: |
| 4092 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 4093 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4094 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 4095 | ; PPC64LE-NEXT: bne 0, .LBB243_1 |
| 4096 | ; PPC64LE-NEXT: # BB#2: |
| 4097 | ; PPC64LE-NEXT: mr 3, 5 |
| 4098 | ; PPC64LE-NEXT: lwsync |
| 4099 | ; PPC64LE-NEXT: blr |
| 4100 | %ret = atomicrmw xor i8* %ptr, i8 %val acq_rel |
| 4101 | ret i8 %ret |
| 4102 | } |
| 4103 | |
| 4104 | define i8 @test244(i8* %ptr, i8 %val) { |
| 4105 | ; PPC64LE-LABEL: test244: |
| 4106 | ; PPC64LE: # BB#0: |
| 4107 | ; PPC64LE-NEXT: sync |
| 4108 | ; PPC64LE-NEXT: .LBB244_1: |
| 4109 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 4110 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4111 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 4112 | ; PPC64LE-NEXT: bne 0, .LBB244_1 |
| 4113 | ; PPC64LE-NEXT: # BB#2: |
| 4114 | ; PPC64LE-NEXT: mr 3, 5 |
| 4115 | ; PPC64LE-NEXT: lwsync |
| 4116 | ; PPC64LE-NEXT: blr |
| 4117 | %ret = atomicrmw xor i8* %ptr, i8 %val seq_cst |
| 4118 | ret i8 %ret |
| 4119 | } |
| 4120 | |
| 4121 | define i16 @test245(i16* %ptr, i16 %val) { |
| 4122 | ; PPC64LE-LABEL: test245: |
| 4123 | ; PPC64LE: # BB#0: |
| 4124 | ; PPC64LE-NEXT: .LBB245_1: |
| 4125 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 4126 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4127 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 4128 | ; PPC64LE-NEXT: bne 0, .LBB245_1 |
| 4129 | ; PPC64LE-NEXT: # BB#2: |
| 4130 | ; PPC64LE-NEXT: mr 3, 5 |
| 4131 | ; PPC64LE-NEXT: blr |
| 4132 | %ret = atomicrmw xor i16* %ptr, i16 %val monotonic |
| 4133 | ret i16 %ret |
| 4134 | } |
| 4135 | |
| 4136 | define i16 @test246(i16* %ptr, i16 %val) { |
| 4137 | ; PPC64LE-LABEL: test246: |
| 4138 | ; PPC64LE: # BB#0: |
| 4139 | ; PPC64LE-NEXT: mr 5, 3 |
| 4140 | ; PPC64LE-NEXT: .LBB246_1: |
| 4141 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 4142 | ; PPC64LE-NEXT: xor 6, 4, 3 |
| 4143 | ; PPC64LE-NEXT: sthcx. 6, 0, 5 |
| 4144 | ; PPC64LE-NEXT: bne 0, .LBB246_1 |
| 4145 | ; PPC64LE-NEXT: # BB#2: |
| 4146 | ; PPC64LE-NEXT: lwsync |
| 4147 | ; PPC64LE-NEXT: blr |
| 4148 | %ret = atomicrmw xor i16* %ptr, i16 %val acquire |
| 4149 | ret i16 %ret |
| 4150 | } |
| 4151 | |
| 4152 | define i16 @test247(i16* %ptr, i16 %val) { |
| 4153 | ; PPC64LE-LABEL: test247: |
| 4154 | ; PPC64LE: # BB#0: |
| 4155 | ; PPC64LE-NEXT: lwsync |
| 4156 | ; PPC64LE-NEXT: .LBB247_1: |
| 4157 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 4158 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4159 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 4160 | ; PPC64LE-NEXT: bne 0, .LBB247_1 |
| 4161 | ; PPC64LE-NEXT: # BB#2: |
| 4162 | ; PPC64LE-NEXT: mr 3, 5 |
| 4163 | ; PPC64LE-NEXT: blr |
| 4164 | %ret = atomicrmw xor i16* %ptr, i16 %val release |
| 4165 | ret i16 %ret |
| 4166 | } |
| 4167 | |
| 4168 | define i16 @test248(i16* %ptr, i16 %val) { |
| 4169 | ; PPC64LE-LABEL: test248: |
| 4170 | ; PPC64LE: # BB#0: |
| 4171 | ; PPC64LE-NEXT: lwsync |
| 4172 | ; PPC64LE-NEXT: .LBB248_1: |
| 4173 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 4174 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4175 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 4176 | ; PPC64LE-NEXT: bne 0, .LBB248_1 |
| 4177 | ; PPC64LE-NEXT: # BB#2: |
| 4178 | ; PPC64LE-NEXT: mr 3, 5 |
| 4179 | ; PPC64LE-NEXT: lwsync |
| 4180 | ; PPC64LE-NEXT: blr |
| 4181 | %ret = atomicrmw xor i16* %ptr, i16 %val acq_rel |
| 4182 | ret i16 %ret |
| 4183 | } |
| 4184 | |
| 4185 | define i16 @test249(i16* %ptr, i16 %val) { |
| 4186 | ; PPC64LE-LABEL: test249: |
| 4187 | ; PPC64LE: # BB#0: |
| 4188 | ; PPC64LE-NEXT: sync |
| 4189 | ; PPC64LE-NEXT: .LBB249_1: |
| 4190 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 4191 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4192 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 4193 | ; PPC64LE-NEXT: bne 0, .LBB249_1 |
| 4194 | ; PPC64LE-NEXT: # BB#2: |
| 4195 | ; PPC64LE-NEXT: mr 3, 5 |
| 4196 | ; PPC64LE-NEXT: lwsync |
| 4197 | ; PPC64LE-NEXT: blr |
| 4198 | %ret = atomicrmw xor i16* %ptr, i16 %val seq_cst |
| 4199 | ret i16 %ret |
| 4200 | } |
| 4201 | |
| 4202 | define i32 @test250(i32* %ptr, i32 %val) { |
| 4203 | ; PPC64LE-LABEL: test250: |
| 4204 | ; PPC64LE: # BB#0: |
| 4205 | ; PPC64LE-NEXT: .LBB250_1: |
| 4206 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 4207 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4208 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 4209 | ; PPC64LE-NEXT: bne 0, .LBB250_1 |
| 4210 | ; PPC64LE-NEXT: # BB#2: |
| 4211 | ; PPC64LE-NEXT: mr 3, 5 |
| 4212 | ; PPC64LE-NEXT: blr |
| 4213 | %ret = atomicrmw xor i32* %ptr, i32 %val monotonic |
| 4214 | ret i32 %ret |
| 4215 | } |
| 4216 | |
| 4217 | define i32 @test251(i32* %ptr, i32 %val) { |
| 4218 | ; PPC64LE-LABEL: test251: |
| 4219 | ; PPC64LE: # BB#0: |
| 4220 | ; PPC64LE-NEXT: mr 5, 3 |
| 4221 | ; PPC64LE-NEXT: .LBB251_1: |
| 4222 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 4223 | ; PPC64LE-NEXT: xor 6, 4, 3 |
| 4224 | ; PPC64LE-NEXT: stwcx. 6, 0, 5 |
| 4225 | ; PPC64LE-NEXT: bne 0, .LBB251_1 |
| 4226 | ; PPC64LE-NEXT: # BB#2: |
| 4227 | ; PPC64LE-NEXT: lwsync |
| 4228 | ; PPC64LE-NEXT: blr |
| 4229 | %ret = atomicrmw xor i32* %ptr, i32 %val acquire |
| 4230 | ret i32 %ret |
| 4231 | } |
| 4232 | |
| 4233 | define i32 @test252(i32* %ptr, i32 %val) { |
| 4234 | ; PPC64LE-LABEL: test252: |
| 4235 | ; PPC64LE: # BB#0: |
| 4236 | ; PPC64LE-NEXT: lwsync |
| 4237 | ; PPC64LE-NEXT: .LBB252_1: |
| 4238 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 4239 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4240 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 4241 | ; PPC64LE-NEXT: bne 0, .LBB252_1 |
| 4242 | ; PPC64LE-NEXT: # BB#2: |
| 4243 | ; PPC64LE-NEXT: mr 3, 5 |
| 4244 | ; PPC64LE-NEXT: blr |
| 4245 | %ret = atomicrmw xor i32* %ptr, i32 %val release |
| 4246 | ret i32 %ret |
| 4247 | } |
| 4248 | |
| 4249 | define i32 @test253(i32* %ptr, i32 %val) { |
| 4250 | ; PPC64LE-LABEL: test253: |
| 4251 | ; PPC64LE: # BB#0: |
| 4252 | ; PPC64LE-NEXT: lwsync |
| 4253 | ; PPC64LE-NEXT: .LBB253_1: |
| 4254 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 4255 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4256 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 4257 | ; PPC64LE-NEXT: bne 0, .LBB253_1 |
| 4258 | ; PPC64LE-NEXT: # BB#2: |
| 4259 | ; PPC64LE-NEXT: mr 3, 5 |
| 4260 | ; PPC64LE-NEXT: lwsync |
| 4261 | ; PPC64LE-NEXT: blr |
| 4262 | %ret = atomicrmw xor i32* %ptr, i32 %val acq_rel |
| 4263 | ret i32 %ret |
| 4264 | } |
| 4265 | |
| 4266 | define i32 @test254(i32* %ptr, i32 %val) { |
| 4267 | ; PPC64LE-LABEL: test254: |
| 4268 | ; PPC64LE: # BB#0: |
| 4269 | ; PPC64LE-NEXT: sync |
| 4270 | ; PPC64LE-NEXT: .LBB254_1: |
| 4271 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 4272 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4273 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 4274 | ; PPC64LE-NEXT: bne 0, .LBB254_1 |
| 4275 | ; PPC64LE-NEXT: # BB#2: |
| 4276 | ; PPC64LE-NEXT: mr 3, 5 |
| 4277 | ; PPC64LE-NEXT: lwsync |
| 4278 | ; PPC64LE-NEXT: blr |
| 4279 | %ret = atomicrmw xor i32* %ptr, i32 %val seq_cst |
| 4280 | ret i32 %ret |
| 4281 | } |
| 4282 | |
| 4283 | define i64 @test255(i64* %ptr, i64 %val) { |
| 4284 | ; PPC64LE-LABEL: test255: |
| 4285 | ; PPC64LE: # BB#0: |
| 4286 | ; PPC64LE-NEXT: .LBB255_1: |
| 4287 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 4288 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4289 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 4290 | ; PPC64LE-NEXT: bne 0, .LBB255_1 |
| 4291 | ; PPC64LE-NEXT: # BB#2: |
| 4292 | ; PPC64LE-NEXT: mr 3, 5 |
| 4293 | ; PPC64LE-NEXT: blr |
| 4294 | %ret = atomicrmw xor i64* %ptr, i64 %val monotonic |
| 4295 | ret i64 %ret |
| 4296 | } |
| 4297 | |
| 4298 | define i64 @test256(i64* %ptr, i64 %val) { |
| 4299 | ; PPC64LE-LABEL: test256: |
| 4300 | ; PPC64LE: # BB#0: |
| 4301 | ; PPC64LE-NEXT: mr 5, 3 |
| 4302 | ; PPC64LE-NEXT: .LBB256_1: |
| 4303 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 4304 | ; PPC64LE-NEXT: xor 6, 4, 3 |
| 4305 | ; PPC64LE-NEXT: stdcx. 6, 0, 5 |
| 4306 | ; PPC64LE-NEXT: bne 0, .LBB256_1 |
| 4307 | ; PPC64LE-NEXT: # BB#2: |
| 4308 | ; PPC64LE-NEXT: lwsync |
| 4309 | ; PPC64LE-NEXT: blr |
| 4310 | %ret = atomicrmw xor i64* %ptr, i64 %val acquire |
| 4311 | ret i64 %ret |
| 4312 | } |
| 4313 | |
| 4314 | define i64 @test257(i64* %ptr, i64 %val) { |
| 4315 | ; PPC64LE-LABEL: test257: |
| 4316 | ; PPC64LE: # BB#0: |
| 4317 | ; PPC64LE-NEXT: lwsync |
| 4318 | ; PPC64LE-NEXT: .LBB257_1: |
| 4319 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 4320 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4321 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 4322 | ; PPC64LE-NEXT: bne 0, .LBB257_1 |
| 4323 | ; PPC64LE-NEXT: # BB#2: |
| 4324 | ; PPC64LE-NEXT: mr 3, 5 |
| 4325 | ; PPC64LE-NEXT: blr |
| 4326 | %ret = atomicrmw xor i64* %ptr, i64 %val release |
| 4327 | ret i64 %ret |
| 4328 | } |
| 4329 | |
| 4330 | define i64 @test258(i64* %ptr, i64 %val) { |
| 4331 | ; PPC64LE-LABEL: test258: |
| 4332 | ; PPC64LE: # BB#0: |
| 4333 | ; PPC64LE-NEXT: lwsync |
| 4334 | ; PPC64LE-NEXT: .LBB258_1: |
| 4335 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 4336 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4337 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 4338 | ; PPC64LE-NEXT: bne 0, .LBB258_1 |
| 4339 | ; PPC64LE-NEXT: # BB#2: |
| 4340 | ; PPC64LE-NEXT: mr 3, 5 |
| 4341 | ; PPC64LE-NEXT: lwsync |
| 4342 | ; PPC64LE-NEXT: blr |
| 4343 | %ret = atomicrmw xor i64* %ptr, i64 %val acq_rel |
| 4344 | ret i64 %ret |
| 4345 | } |
| 4346 | |
| 4347 | define i64 @test259(i64* %ptr, i64 %val) { |
| 4348 | ; PPC64LE-LABEL: test259: |
| 4349 | ; PPC64LE: # BB#0: |
| 4350 | ; PPC64LE-NEXT: sync |
| 4351 | ; PPC64LE-NEXT: .LBB259_1: |
| 4352 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 4353 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 4354 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 4355 | ; PPC64LE-NEXT: bne 0, .LBB259_1 |
| 4356 | ; PPC64LE-NEXT: # BB#2: |
| 4357 | ; PPC64LE-NEXT: mr 3, 5 |
| 4358 | ; PPC64LE-NEXT: lwsync |
| 4359 | ; PPC64LE-NEXT: blr |
| 4360 | %ret = atomicrmw xor i64* %ptr, i64 %val seq_cst |
| 4361 | ret i64 %ret |
| 4362 | } |
| 4363 | |
| 4364 | define i8 @test260(i8* %ptr, i8 %val) { |
| 4365 | ; PPC64LE-LABEL: test260: |
| 4366 | ; PPC64LE: # BB#0: |
| 4367 | ; PPC64LE-NEXT: .LBB260_1: |
| 4368 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 4369 | ; PPC64LE-NEXT: extsb 6, 5 |
| 4370 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4371 | ; PPC64LE-NEXT: ble 0, .LBB260_3 |
| 4372 | ; PPC64LE-NEXT: # BB#2: |
| 4373 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 4374 | ; PPC64LE-NEXT: bne 0, .LBB260_1 |
| 4375 | ; PPC64LE-NEXT: .LBB260_3: |
| 4376 | ; PPC64LE-NEXT: mr 3, 5 |
| 4377 | ; PPC64LE-NEXT: blr |
| 4378 | %ret = atomicrmw max i8* %ptr, i8 %val monotonic |
| 4379 | ret i8 %ret |
| 4380 | } |
| 4381 | |
| 4382 | define i8 @test261(i8* %ptr, i8 %val) { |
| 4383 | ; PPC64LE-LABEL: test261: |
| 4384 | ; PPC64LE: # BB#0: |
| 4385 | ; PPC64LE-NEXT: mr 5, 3 |
| 4386 | ; PPC64LE-NEXT: .LBB261_1: |
| 4387 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 4388 | ; PPC64LE-NEXT: extsb 6, 3 |
| 4389 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4390 | ; PPC64LE-NEXT: ble 0, .LBB261_3 |
| 4391 | ; PPC64LE-NEXT: # BB#2: |
| 4392 | ; PPC64LE-NEXT: stbcx. 4, 0, 5 |
| 4393 | ; PPC64LE-NEXT: bne 0, .LBB261_1 |
| 4394 | ; PPC64LE-NEXT: .LBB261_3: |
| 4395 | ; PPC64LE-NEXT: lwsync |
| 4396 | ; PPC64LE-NEXT: blr |
| 4397 | %ret = atomicrmw max i8* %ptr, i8 %val acquire |
| 4398 | ret i8 %ret |
| 4399 | } |
| 4400 | |
| 4401 | define i8 @test262(i8* %ptr, i8 %val) { |
| 4402 | ; PPC64LE-LABEL: test262: |
| 4403 | ; PPC64LE: # BB#0: |
| 4404 | ; PPC64LE-NEXT: lwsync |
| 4405 | ; PPC64LE-NEXT: .LBB262_1: |
| 4406 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 4407 | ; PPC64LE-NEXT: extsb 6, 5 |
| 4408 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4409 | ; PPC64LE-NEXT: ble 0, .LBB262_3 |
| 4410 | ; PPC64LE-NEXT: # BB#2: |
| 4411 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 4412 | ; PPC64LE-NEXT: bne 0, .LBB262_1 |
| 4413 | ; PPC64LE-NEXT: .LBB262_3: |
| 4414 | ; PPC64LE-NEXT: mr 3, 5 |
| 4415 | ; PPC64LE-NEXT: blr |
| 4416 | %ret = atomicrmw max i8* %ptr, i8 %val release |
| 4417 | ret i8 %ret |
| 4418 | } |
| 4419 | |
| 4420 | define i8 @test263(i8* %ptr, i8 %val) { |
| 4421 | ; PPC64LE-LABEL: test263: |
| 4422 | ; PPC64LE: # BB#0: |
| 4423 | ; PPC64LE-NEXT: lwsync |
| 4424 | ; PPC64LE-NEXT: .LBB263_1: |
| 4425 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 4426 | ; PPC64LE-NEXT: extsb 6, 5 |
| 4427 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4428 | ; PPC64LE-NEXT: ble 0, .LBB263_3 |
| 4429 | ; PPC64LE-NEXT: # BB#2: |
| 4430 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 4431 | ; PPC64LE-NEXT: bne 0, .LBB263_1 |
| 4432 | ; PPC64LE-NEXT: .LBB263_3: |
| 4433 | ; PPC64LE-NEXT: mr 3, 5 |
| 4434 | ; PPC64LE-NEXT: lwsync |
| 4435 | ; PPC64LE-NEXT: blr |
| 4436 | %ret = atomicrmw max i8* %ptr, i8 %val acq_rel |
| 4437 | ret i8 %ret |
| 4438 | } |
| 4439 | |
| 4440 | define i8 @test264(i8* %ptr, i8 %val) { |
| 4441 | ; PPC64LE-LABEL: test264: |
| 4442 | ; PPC64LE: # BB#0: |
| 4443 | ; PPC64LE-NEXT: sync |
| 4444 | ; PPC64LE-NEXT: .LBB264_1: |
| 4445 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 4446 | ; PPC64LE-NEXT: extsb 6, 5 |
| 4447 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4448 | ; PPC64LE-NEXT: ble 0, .LBB264_3 |
| 4449 | ; PPC64LE-NEXT: # BB#2: |
| 4450 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 4451 | ; PPC64LE-NEXT: bne 0, .LBB264_1 |
| 4452 | ; PPC64LE-NEXT: .LBB264_3: |
| 4453 | ; PPC64LE-NEXT: mr 3, 5 |
| 4454 | ; PPC64LE-NEXT: lwsync |
| 4455 | ; PPC64LE-NEXT: blr |
| 4456 | %ret = atomicrmw max i8* %ptr, i8 %val seq_cst |
| 4457 | ret i8 %ret |
| 4458 | } |
| 4459 | |
| 4460 | define i16 @test265(i16* %ptr, i16 %val) { |
| 4461 | ; PPC64LE-LABEL: test265: |
| 4462 | ; PPC64LE: # BB#0: |
| 4463 | ; PPC64LE-NEXT: .LBB265_1: |
| 4464 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 4465 | ; PPC64LE-NEXT: extsh 6, 5 |
| 4466 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4467 | ; PPC64LE-NEXT: ble 0, .LBB265_3 |
| 4468 | ; PPC64LE-NEXT: # BB#2: |
| 4469 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 4470 | ; PPC64LE-NEXT: bne 0, .LBB265_1 |
| 4471 | ; PPC64LE-NEXT: .LBB265_3: |
| 4472 | ; PPC64LE-NEXT: mr 3, 5 |
| 4473 | ; PPC64LE-NEXT: blr |
| 4474 | %ret = atomicrmw max i16* %ptr, i16 %val monotonic |
| 4475 | ret i16 %ret |
| 4476 | } |
| 4477 | |
| 4478 | define i16 @test266(i16* %ptr, i16 %val) { |
| 4479 | ; PPC64LE-LABEL: test266: |
| 4480 | ; PPC64LE: # BB#0: |
| 4481 | ; PPC64LE-NEXT: mr 5, 3 |
| 4482 | ; PPC64LE-NEXT: .LBB266_1: |
| 4483 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 4484 | ; PPC64LE-NEXT: extsh 6, 3 |
| 4485 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4486 | ; PPC64LE-NEXT: ble 0, .LBB266_3 |
| 4487 | ; PPC64LE-NEXT: # BB#2: |
| 4488 | ; PPC64LE-NEXT: sthcx. 4, 0, 5 |
| 4489 | ; PPC64LE-NEXT: bne 0, .LBB266_1 |
| 4490 | ; PPC64LE-NEXT: .LBB266_3: |
| 4491 | ; PPC64LE-NEXT: lwsync |
| 4492 | ; PPC64LE-NEXT: blr |
| 4493 | %ret = atomicrmw max i16* %ptr, i16 %val acquire |
| 4494 | ret i16 %ret |
| 4495 | } |
| 4496 | |
| 4497 | define i16 @test267(i16* %ptr, i16 %val) { |
| 4498 | ; PPC64LE-LABEL: test267: |
| 4499 | ; PPC64LE: # BB#0: |
| 4500 | ; PPC64LE-NEXT: lwsync |
| 4501 | ; PPC64LE-NEXT: .LBB267_1: |
| 4502 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 4503 | ; PPC64LE-NEXT: extsh 6, 5 |
| 4504 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4505 | ; PPC64LE-NEXT: ble 0, .LBB267_3 |
| 4506 | ; PPC64LE-NEXT: # BB#2: |
| 4507 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 4508 | ; PPC64LE-NEXT: bne 0, .LBB267_1 |
| 4509 | ; PPC64LE-NEXT: .LBB267_3: |
| 4510 | ; PPC64LE-NEXT: mr 3, 5 |
| 4511 | ; PPC64LE-NEXT: blr |
| 4512 | %ret = atomicrmw max i16* %ptr, i16 %val release |
| 4513 | ret i16 %ret |
| 4514 | } |
| 4515 | |
| 4516 | define i16 @test268(i16* %ptr, i16 %val) { |
| 4517 | ; PPC64LE-LABEL: test268: |
| 4518 | ; PPC64LE: # BB#0: |
| 4519 | ; PPC64LE-NEXT: lwsync |
| 4520 | ; PPC64LE-NEXT: .LBB268_1: |
| 4521 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 4522 | ; PPC64LE-NEXT: extsh 6, 5 |
| 4523 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4524 | ; PPC64LE-NEXT: ble 0, .LBB268_3 |
| 4525 | ; PPC64LE-NEXT: # BB#2: |
| 4526 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 4527 | ; PPC64LE-NEXT: bne 0, .LBB268_1 |
| 4528 | ; PPC64LE-NEXT: .LBB268_3: |
| 4529 | ; PPC64LE-NEXT: mr 3, 5 |
| 4530 | ; PPC64LE-NEXT: lwsync |
| 4531 | ; PPC64LE-NEXT: blr |
| 4532 | %ret = atomicrmw max i16* %ptr, i16 %val acq_rel |
| 4533 | ret i16 %ret |
| 4534 | } |
| 4535 | |
| 4536 | define i16 @test269(i16* %ptr, i16 %val) { |
| 4537 | ; PPC64LE-LABEL: test269: |
| 4538 | ; PPC64LE: # BB#0: |
| 4539 | ; PPC64LE-NEXT: sync |
| 4540 | ; PPC64LE-NEXT: .LBB269_1: |
| 4541 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 4542 | ; PPC64LE-NEXT: extsh 6, 5 |
| 4543 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4544 | ; PPC64LE-NEXT: ble 0, .LBB269_3 |
| 4545 | ; PPC64LE-NEXT: # BB#2: |
| 4546 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 4547 | ; PPC64LE-NEXT: bne 0, .LBB269_1 |
| 4548 | ; PPC64LE-NEXT: .LBB269_3: |
| 4549 | ; PPC64LE-NEXT: mr 3, 5 |
| 4550 | ; PPC64LE-NEXT: lwsync |
| 4551 | ; PPC64LE-NEXT: blr |
| 4552 | %ret = atomicrmw max i16* %ptr, i16 %val seq_cst |
| 4553 | ret i16 %ret |
| 4554 | } |
| 4555 | |
| 4556 | define i32 @test270(i32* %ptr, i32 %val) { |
| 4557 | ; PPC64LE-LABEL: test270: |
| 4558 | ; PPC64LE: # BB#0: |
| 4559 | ; PPC64LE-NEXT: .LBB270_1: |
| 4560 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 4561 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 4562 | ; PPC64LE-NEXT: ble 0, .LBB270_3 |
| 4563 | ; PPC64LE-NEXT: # BB#2: |
| 4564 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 4565 | ; PPC64LE-NEXT: bne 0, .LBB270_1 |
| 4566 | ; PPC64LE-NEXT: .LBB270_3: |
| 4567 | ; PPC64LE-NEXT: mr 3, 5 |
| 4568 | ; PPC64LE-NEXT: blr |
| 4569 | %ret = atomicrmw max i32* %ptr, i32 %val monotonic |
| 4570 | ret i32 %ret |
| 4571 | } |
| 4572 | |
| 4573 | define i32 @test271(i32* %ptr, i32 %val) { |
| 4574 | ; PPC64LE-LABEL: test271: |
| 4575 | ; PPC64LE: # BB#0: |
| 4576 | ; PPC64LE-NEXT: mr 5, 3 |
| 4577 | ; PPC64LE-NEXT: .LBB271_1: |
| 4578 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 4579 | ; PPC64LE-NEXT: cmpw 4, 3 |
| 4580 | ; PPC64LE-NEXT: ble 0, .LBB271_3 |
| 4581 | ; PPC64LE-NEXT: # BB#2: |
| 4582 | ; PPC64LE-NEXT: stwcx. 4, 0, 5 |
| 4583 | ; PPC64LE-NEXT: bne 0, .LBB271_1 |
| 4584 | ; PPC64LE-NEXT: .LBB271_3: |
| 4585 | ; PPC64LE-NEXT: lwsync |
| 4586 | ; PPC64LE-NEXT: blr |
| 4587 | %ret = atomicrmw max i32* %ptr, i32 %val acquire |
| 4588 | ret i32 %ret |
| 4589 | } |
| 4590 | |
| 4591 | define i32 @test272(i32* %ptr, i32 %val) { |
| 4592 | ; PPC64LE-LABEL: test272: |
| 4593 | ; PPC64LE: # BB#0: |
| 4594 | ; PPC64LE-NEXT: lwsync |
| 4595 | ; PPC64LE-NEXT: .LBB272_1: |
| 4596 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 4597 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 4598 | ; PPC64LE-NEXT: ble 0, .LBB272_3 |
| 4599 | ; PPC64LE-NEXT: # BB#2: |
| 4600 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 4601 | ; PPC64LE-NEXT: bne 0, .LBB272_1 |
| 4602 | ; PPC64LE-NEXT: .LBB272_3: |
| 4603 | ; PPC64LE-NEXT: mr 3, 5 |
| 4604 | ; PPC64LE-NEXT: blr |
| 4605 | %ret = atomicrmw max i32* %ptr, i32 %val release |
| 4606 | ret i32 %ret |
| 4607 | } |
| 4608 | |
| 4609 | define i32 @test273(i32* %ptr, i32 %val) { |
| 4610 | ; PPC64LE-LABEL: test273: |
| 4611 | ; PPC64LE: # BB#0: |
| 4612 | ; PPC64LE-NEXT: lwsync |
| 4613 | ; PPC64LE-NEXT: .LBB273_1: |
| 4614 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 4615 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 4616 | ; PPC64LE-NEXT: ble 0, .LBB273_3 |
| 4617 | ; PPC64LE-NEXT: # BB#2: |
| 4618 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 4619 | ; PPC64LE-NEXT: bne 0, .LBB273_1 |
| 4620 | ; PPC64LE-NEXT: .LBB273_3: |
| 4621 | ; PPC64LE-NEXT: mr 3, 5 |
| 4622 | ; PPC64LE-NEXT: lwsync |
| 4623 | ; PPC64LE-NEXT: blr |
| 4624 | %ret = atomicrmw max i32* %ptr, i32 %val acq_rel |
| 4625 | ret i32 %ret |
| 4626 | } |
| 4627 | |
| 4628 | define i32 @test274(i32* %ptr, i32 %val) { |
| 4629 | ; PPC64LE-LABEL: test274: |
| 4630 | ; PPC64LE: # BB#0: |
| 4631 | ; PPC64LE-NEXT: sync |
| 4632 | ; PPC64LE-NEXT: .LBB274_1: |
| 4633 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 4634 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 4635 | ; PPC64LE-NEXT: ble 0, .LBB274_3 |
| 4636 | ; PPC64LE-NEXT: # BB#2: |
| 4637 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 4638 | ; PPC64LE-NEXT: bne 0, .LBB274_1 |
| 4639 | ; PPC64LE-NEXT: .LBB274_3: |
| 4640 | ; PPC64LE-NEXT: mr 3, 5 |
| 4641 | ; PPC64LE-NEXT: lwsync |
| 4642 | ; PPC64LE-NEXT: blr |
| 4643 | %ret = atomicrmw max i32* %ptr, i32 %val seq_cst |
| 4644 | ret i32 %ret |
| 4645 | } |
| 4646 | |
| 4647 | define i64 @test275(i64* %ptr, i64 %val) { |
| 4648 | ; PPC64LE-LABEL: test275: |
| 4649 | ; PPC64LE: # BB#0: |
| 4650 | ; PPC64LE-NEXT: .LBB275_1: |
| 4651 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 4652 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 4653 | ; PPC64LE-NEXT: ble 0, .LBB275_3 |
| 4654 | ; PPC64LE-NEXT: # BB#2: |
| 4655 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 4656 | ; PPC64LE-NEXT: bne 0, .LBB275_1 |
| 4657 | ; PPC64LE-NEXT: .LBB275_3: |
| 4658 | ; PPC64LE-NEXT: mr 3, 5 |
| 4659 | ; PPC64LE-NEXT: blr |
| 4660 | %ret = atomicrmw max i64* %ptr, i64 %val monotonic |
| 4661 | ret i64 %ret |
| 4662 | } |
| 4663 | |
| 4664 | define i64 @test276(i64* %ptr, i64 %val) { |
| 4665 | ; PPC64LE-LABEL: test276: |
| 4666 | ; PPC64LE: # BB#0: |
| 4667 | ; PPC64LE-NEXT: mr 5, 3 |
| 4668 | ; PPC64LE-NEXT: .LBB276_1: |
| 4669 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 4670 | ; PPC64LE-NEXT: cmpd 4, 3 |
| 4671 | ; PPC64LE-NEXT: ble 0, .LBB276_3 |
| 4672 | ; PPC64LE-NEXT: # BB#2: |
| 4673 | ; PPC64LE-NEXT: stdcx. 4, 0, 5 |
| 4674 | ; PPC64LE-NEXT: bne 0, .LBB276_1 |
| 4675 | ; PPC64LE-NEXT: .LBB276_3: |
| 4676 | ; PPC64LE-NEXT: lwsync |
| 4677 | ; PPC64LE-NEXT: blr |
| 4678 | %ret = atomicrmw max i64* %ptr, i64 %val acquire |
| 4679 | ret i64 %ret |
| 4680 | } |
| 4681 | |
| 4682 | define i64 @test277(i64* %ptr, i64 %val) { |
| 4683 | ; PPC64LE-LABEL: test277: |
| 4684 | ; PPC64LE: # BB#0: |
| 4685 | ; PPC64LE-NEXT: lwsync |
| 4686 | ; PPC64LE-NEXT: .LBB277_1: |
| 4687 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 4688 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 4689 | ; PPC64LE-NEXT: ble 0, .LBB277_3 |
| 4690 | ; PPC64LE-NEXT: # BB#2: |
| 4691 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 4692 | ; PPC64LE-NEXT: bne 0, .LBB277_1 |
| 4693 | ; PPC64LE-NEXT: .LBB277_3: |
| 4694 | ; PPC64LE-NEXT: mr 3, 5 |
| 4695 | ; PPC64LE-NEXT: blr |
| 4696 | %ret = atomicrmw max i64* %ptr, i64 %val release |
| 4697 | ret i64 %ret |
| 4698 | } |
| 4699 | |
| 4700 | define i64 @test278(i64* %ptr, i64 %val) { |
| 4701 | ; PPC64LE-LABEL: test278: |
| 4702 | ; PPC64LE: # BB#0: |
| 4703 | ; PPC64LE-NEXT: lwsync |
| 4704 | ; PPC64LE-NEXT: .LBB278_1: |
| 4705 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 4706 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 4707 | ; PPC64LE-NEXT: ble 0, .LBB278_3 |
| 4708 | ; PPC64LE-NEXT: # BB#2: |
| 4709 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 4710 | ; PPC64LE-NEXT: bne 0, .LBB278_1 |
| 4711 | ; PPC64LE-NEXT: .LBB278_3: |
| 4712 | ; PPC64LE-NEXT: mr 3, 5 |
| 4713 | ; PPC64LE-NEXT: lwsync |
| 4714 | ; PPC64LE-NEXT: blr |
| 4715 | %ret = atomicrmw max i64* %ptr, i64 %val acq_rel |
| 4716 | ret i64 %ret |
| 4717 | } |
| 4718 | |
| 4719 | define i64 @test279(i64* %ptr, i64 %val) { |
| 4720 | ; PPC64LE-LABEL: test279: |
| 4721 | ; PPC64LE: # BB#0: |
| 4722 | ; PPC64LE-NEXT: sync |
| 4723 | ; PPC64LE-NEXT: .LBB279_1: |
| 4724 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 4725 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 4726 | ; PPC64LE-NEXT: ble 0, .LBB279_3 |
| 4727 | ; PPC64LE-NEXT: # BB#2: |
| 4728 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 4729 | ; PPC64LE-NEXT: bne 0, .LBB279_1 |
| 4730 | ; PPC64LE-NEXT: .LBB279_3: |
| 4731 | ; PPC64LE-NEXT: mr 3, 5 |
| 4732 | ; PPC64LE-NEXT: lwsync |
| 4733 | ; PPC64LE-NEXT: blr |
| 4734 | %ret = atomicrmw max i64* %ptr, i64 %val seq_cst |
| 4735 | ret i64 %ret |
| 4736 | } |
| 4737 | |
| 4738 | define i8 @test280(i8* %ptr, i8 %val) { |
| 4739 | ; PPC64LE-LABEL: test280: |
| 4740 | ; PPC64LE: # BB#0: |
| 4741 | ; PPC64LE-NEXT: .LBB280_1: |
| 4742 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 4743 | ; PPC64LE-NEXT: extsb 6, 5 |
| 4744 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4745 | ; PPC64LE-NEXT: bge 0, .LBB280_3 |
| 4746 | ; PPC64LE-NEXT: # BB#2: |
| 4747 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 4748 | ; PPC64LE-NEXT: bne 0, .LBB280_1 |
| 4749 | ; PPC64LE-NEXT: .LBB280_3: |
| 4750 | ; PPC64LE-NEXT: mr 3, 5 |
| 4751 | ; PPC64LE-NEXT: blr |
| 4752 | %ret = atomicrmw min i8* %ptr, i8 %val monotonic |
| 4753 | ret i8 %ret |
| 4754 | } |
| 4755 | |
| 4756 | define i8 @test281(i8* %ptr, i8 %val) { |
| 4757 | ; PPC64LE-LABEL: test281: |
| 4758 | ; PPC64LE: # BB#0: |
| 4759 | ; PPC64LE-NEXT: mr 5, 3 |
| 4760 | ; PPC64LE-NEXT: .LBB281_1: |
| 4761 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 4762 | ; PPC64LE-NEXT: extsb 6, 3 |
| 4763 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4764 | ; PPC64LE-NEXT: bge 0, .LBB281_3 |
| 4765 | ; PPC64LE-NEXT: # BB#2: |
| 4766 | ; PPC64LE-NEXT: stbcx. 4, 0, 5 |
| 4767 | ; PPC64LE-NEXT: bne 0, .LBB281_1 |
| 4768 | ; PPC64LE-NEXT: .LBB281_3: |
| 4769 | ; PPC64LE-NEXT: lwsync |
| 4770 | ; PPC64LE-NEXT: blr |
| 4771 | %ret = atomicrmw min i8* %ptr, i8 %val acquire |
| 4772 | ret i8 %ret |
| 4773 | } |
| 4774 | |
| 4775 | define i8 @test282(i8* %ptr, i8 %val) { |
| 4776 | ; PPC64LE-LABEL: test282: |
| 4777 | ; PPC64LE: # BB#0: |
| 4778 | ; PPC64LE-NEXT: lwsync |
| 4779 | ; PPC64LE-NEXT: .LBB282_1: |
| 4780 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 4781 | ; PPC64LE-NEXT: extsb 6, 5 |
| 4782 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4783 | ; PPC64LE-NEXT: bge 0, .LBB282_3 |
| 4784 | ; PPC64LE-NEXT: # BB#2: |
| 4785 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 4786 | ; PPC64LE-NEXT: bne 0, .LBB282_1 |
| 4787 | ; PPC64LE-NEXT: .LBB282_3: |
| 4788 | ; PPC64LE-NEXT: mr 3, 5 |
| 4789 | ; PPC64LE-NEXT: blr |
| 4790 | %ret = atomicrmw min i8* %ptr, i8 %val release |
| 4791 | ret i8 %ret |
| 4792 | } |
| 4793 | |
| 4794 | define i8 @test283(i8* %ptr, i8 %val) { |
| 4795 | ; PPC64LE-LABEL: test283: |
| 4796 | ; PPC64LE: # BB#0: |
| 4797 | ; PPC64LE-NEXT: lwsync |
| 4798 | ; PPC64LE-NEXT: .LBB283_1: |
| 4799 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 4800 | ; PPC64LE-NEXT: extsb 6, 5 |
| 4801 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4802 | ; PPC64LE-NEXT: bge 0, .LBB283_3 |
| 4803 | ; PPC64LE-NEXT: # BB#2: |
| 4804 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 4805 | ; PPC64LE-NEXT: bne 0, .LBB283_1 |
| 4806 | ; PPC64LE-NEXT: .LBB283_3: |
| 4807 | ; PPC64LE-NEXT: mr 3, 5 |
| 4808 | ; PPC64LE-NEXT: lwsync |
| 4809 | ; PPC64LE-NEXT: blr |
| 4810 | %ret = atomicrmw min i8* %ptr, i8 %val acq_rel |
| 4811 | ret i8 %ret |
| 4812 | } |
| 4813 | |
| 4814 | define i8 @test284(i8* %ptr, i8 %val) { |
| 4815 | ; PPC64LE-LABEL: test284: |
| 4816 | ; PPC64LE: # BB#0: |
| 4817 | ; PPC64LE-NEXT: sync |
| 4818 | ; PPC64LE-NEXT: .LBB284_1: |
| 4819 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 4820 | ; PPC64LE-NEXT: extsb 6, 5 |
| 4821 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4822 | ; PPC64LE-NEXT: bge 0, .LBB284_3 |
| 4823 | ; PPC64LE-NEXT: # BB#2: |
| 4824 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 4825 | ; PPC64LE-NEXT: bne 0, .LBB284_1 |
| 4826 | ; PPC64LE-NEXT: .LBB284_3: |
| 4827 | ; PPC64LE-NEXT: mr 3, 5 |
| 4828 | ; PPC64LE-NEXT: lwsync |
| 4829 | ; PPC64LE-NEXT: blr |
| 4830 | %ret = atomicrmw min i8* %ptr, i8 %val seq_cst |
| 4831 | ret i8 %ret |
| 4832 | } |
| 4833 | |
| 4834 | define i16 @test285(i16* %ptr, i16 %val) { |
| 4835 | ; PPC64LE-LABEL: test285: |
| 4836 | ; PPC64LE: # BB#0: |
| 4837 | ; PPC64LE-NEXT: .LBB285_1: |
| 4838 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 4839 | ; PPC64LE-NEXT: extsh 6, 5 |
| 4840 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4841 | ; PPC64LE-NEXT: bge 0, .LBB285_3 |
| 4842 | ; PPC64LE-NEXT: # BB#2: |
| 4843 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 4844 | ; PPC64LE-NEXT: bne 0, .LBB285_1 |
| 4845 | ; PPC64LE-NEXT: .LBB285_3: |
| 4846 | ; PPC64LE-NEXT: mr 3, 5 |
| 4847 | ; PPC64LE-NEXT: blr |
| 4848 | %ret = atomicrmw min i16* %ptr, i16 %val monotonic |
| 4849 | ret i16 %ret |
| 4850 | } |
| 4851 | |
| 4852 | define i16 @test286(i16* %ptr, i16 %val) { |
| 4853 | ; PPC64LE-LABEL: test286: |
| 4854 | ; PPC64LE: # BB#0: |
| 4855 | ; PPC64LE-NEXT: mr 5, 3 |
| 4856 | ; PPC64LE-NEXT: .LBB286_1: |
| 4857 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 4858 | ; PPC64LE-NEXT: extsh 6, 3 |
| 4859 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4860 | ; PPC64LE-NEXT: bge 0, .LBB286_3 |
| 4861 | ; PPC64LE-NEXT: # BB#2: |
| 4862 | ; PPC64LE-NEXT: sthcx. 4, 0, 5 |
| 4863 | ; PPC64LE-NEXT: bne 0, .LBB286_1 |
| 4864 | ; PPC64LE-NEXT: .LBB286_3: |
| 4865 | ; PPC64LE-NEXT: lwsync |
| 4866 | ; PPC64LE-NEXT: blr |
| 4867 | %ret = atomicrmw min i16* %ptr, i16 %val acquire |
| 4868 | ret i16 %ret |
| 4869 | } |
| 4870 | |
| 4871 | define i16 @test287(i16* %ptr, i16 %val) { |
| 4872 | ; PPC64LE-LABEL: test287: |
| 4873 | ; PPC64LE: # BB#0: |
| 4874 | ; PPC64LE-NEXT: lwsync |
| 4875 | ; PPC64LE-NEXT: .LBB287_1: |
| 4876 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 4877 | ; PPC64LE-NEXT: extsh 6, 5 |
| 4878 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4879 | ; PPC64LE-NEXT: bge 0, .LBB287_3 |
| 4880 | ; PPC64LE-NEXT: # BB#2: |
| 4881 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 4882 | ; PPC64LE-NEXT: bne 0, .LBB287_1 |
| 4883 | ; PPC64LE-NEXT: .LBB287_3: |
| 4884 | ; PPC64LE-NEXT: mr 3, 5 |
| 4885 | ; PPC64LE-NEXT: blr |
| 4886 | %ret = atomicrmw min i16* %ptr, i16 %val release |
| 4887 | ret i16 %ret |
| 4888 | } |
| 4889 | |
| 4890 | define i16 @test288(i16* %ptr, i16 %val) { |
| 4891 | ; PPC64LE-LABEL: test288: |
| 4892 | ; PPC64LE: # BB#0: |
| 4893 | ; PPC64LE-NEXT: lwsync |
| 4894 | ; PPC64LE-NEXT: .LBB288_1: |
| 4895 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 4896 | ; PPC64LE-NEXT: extsh 6, 5 |
| 4897 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4898 | ; PPC64LE-NEXT: bge 0, .LBB288_3 |
| 4899 | ; PPC64LE-NEXT: # BB#2: |
| 4900 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 4901 | ; PPC64LE-NEXT: bne 0, .LBB288_1 |
| 4902 | ; PPC64LE-NEXT: .LBB288_3: |
| 4903 | ; PPC64LE-NEXT: mr 3, 5 |
| 4904 | ; PPC64LE-NEXT: lwsync |
| 4905 | ; PPC64LE-NEXT: blr |
| 4906 | %ret = atomicrmw min i16* %ptr, i16 %val acq_rel |
| 4907 | ret i16 %ret |
| 4908 | } |
| 4909 | |
| 4910 | define i16 @test289(i16* %ptr, i16 %val) { |
| 4911 | ; PPC64LE-LABEL: test289: |
| 4912 | ; PPC64LE: # BB#0: |
| 4913 | ; PPC64LE-NEXT: sync |
| 4914 | ; PPC64LE-NEXT: .LBB289_1: |
| 4915 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 4916 | ; PPC64LE-NEXT: extsh 6, 5 |
| 4917 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 4918 | ; PPC64LE-NEXT: bge 0, .LBB289_3 |
| 4919 | ; PPC64LE-NEXT: # BB#2: |
| 4920 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 4921 | ; PPC64LE-NEXT: bne 0, .LBB289_1 |
| 4922 | ; PPC64LE-NEXT: .LBB289_3: |
| 4923 | ; PPC64LE-NEXT: mr 3, 5 |
| 4924 | ; PPC64LE-NEXT: lwsync |
| 4925 | ; PPC64LE-NEXT: blr |
| 4926 | %ret = atomicrmw min i16* %ptr, i16 %val seq_cst |
| 4927 | ret i16 %ret |
| 4928 | } |
| 4929 | |
| 4930 | define i32 @test290(i32* %ptr, i32 %val) { |
| 4931 | ; PPC64LE-LABEL: test290: |
| 4932 | ; PPC64LE: # BB#0: |
| 4933 | ; PPC64LE-NEXT: .LBB290_1: |
| 4934 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 4935 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 4936 | ; PPC64LE-NEXT: bge 0, .LBB290_3 |
| 4937 | ; PPC64LE-NEXT: # BB#2: |
| 4938 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 4939 | ; PPC64LE-NEXT: bne 0, .LBB290_1 |
| 4940 | ; PPC64LE-NEXT: .LBB290_3: |
| 4941 | ; PPC64LE-NEXT: mr 3, 5 |
| 4942 | ; PPC64LE-NEXT: blr |
| 4943 | %ret = atomicrmw min i32* %ptr, i32 %val monotonic |
| 4944 | ret i32 %ret |
| 4945 | } |
| 4946 | |
| 4947 | define i32 @test291(i32* %ptr, i32 %val) { |
| 4948 | ; PPC64LE-LABEL: test291: |
| 4949 | ; PPC64LE: # BB#0: |
| 4950 | ; PPC64LE-NEXT: mr 5, 3 |
| 4951 | ; PPC64LE-NEXT: .LBB291_1: |
| 4952 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 4953 | ; PPC64LE-NEXT: cmpw 4, 3 |
| 4954 | ; PPC64LE-NEXT: bge 0, .LBB291_3 |
| 4955 | ; PPC64LE-NEXT: # BB#2: |
| 4956 | ; PPC64LE-NEXT: stwcx. 4, 0, 5 |
| 4957 | ; PPC64LE-NEXT: bne 0, .LBB291_1 |
| 4958 | ; PPC64LE-NEXT: .LBB291_3: |
| 4959 | ; PPC64LE-NEXT: lwsync |
| 4960 | ; PPC64LE-NEXT: blr |
| 4961 | %ret = atomicrmw min i32* %ptr, i32 %val acquire |
| 4962 | ret i32 %ret |
| 4963 | } |
| 4964 | |
| 4965 | define i32 @test292(i32* %ptr, i32 %val) { |
| 4966 | ; PPC64LE-LABEL: test292: |
| 4967 | ; PPC64LE: # BB#0: |
| 4968 | ; PPC64LE-NEXT: lwsync |
| 4969 | ; PPC64LE-NEXT: .LBB292_1: |
| 4970 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 4971 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 4972 | ; PPC64LE-NEXT: bge 0, .LBB292_3 |
| 4973 | ; PPC64LE-NEXT: # BB#2: |
| 4974 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 4975 | ; PPC64LE-NEXT: bne 0, .LBB292_1 |
| 4976 | ; PPC64LE-NEXT: .LBB292_3: |
| 4977 | ; PPC64LE-NEXT: mr 3, 5 |
| 4978 | ; PPC64LE-NEXT: blr |
| 4979 | %ret = atomicrmw min i32* %ptr, i32 %val release |
| 4980 | ret i32 %ret |
| 4981 | } |
| 4982 | |
| 4983 | define i32 @test293(i32* %ptr, i32 %val) { |
| 4984 | ; PPC64LE-LABEL: test293: |
| 4985 | ; PPC64LE: # BB#0: |
| 4986 | ; PPC64LE-NEXT: lwsync |
| 4987 | ; PPC64LE-NEXT: .LBB293_1: |
| 4988 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 4989 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 4990 | ; PPC64LE-NEXT: bge 0, .LBB293_3 |
| 4991 | ; PPC64LE-NEXT: # BB#2: |
| 4992 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 4993 | ; PPC64LE-NEXT: bne 0, .LBB293_1 |
| 4994 | ; PPC64LE-NEXT: .LBB293_3: |
| 4995 | ; PPC64LE-NEXT: mr 3, 5 |
| 4996 | ; PPC64LE-NEXT: lwsync |
| 4997 | ; PPC64LE-NEXT: blr |
| 4998 | %ret = atomicrmw min i32* %ptr, i32 %val acq_rel |
| 4999 | ret i32 %ret |
| 5000 | } |
| 5001 | |
| 5002 | define i32 @test294(i32* %ptr, i32 %val) { |
| 5003 | ; PPC64LE-LABEL: test294: |
| 5004 | ; PPC64LE: # BB#0: |
| 5005 | ; PPC64LE-NEXT: sync |
| 5006 | ; PPC64LE-NEXT: .LBB294_1: |
| 5007 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 5008 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 5009 | ; PPC64LE-NEXT: bge 0, .LBB294_3 |
| 5010 | ; PPC64LE-NEXT: # BB#2: |
| 5011 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 5012 | ; PPC64LE-NEXT: bne 0, .LBB294_1 |
| 5013 | ; PPC64LE-NEXT: .LBB294_3: |
| 5014 | ; PPC64LE-NEXT: mr 3, 5 |
| 5015 | ; PPC64LE-NEXT: lwsync |
| 5016 | ; PPC64LE-NEXT: blr |
| 5017 | %ret = atomicrmw min i32* %ptr, i32 %val seq_cst |
| 5018 | ret i32 %ret |
| 5019 | } |
| 5020 | |
| 5021 | define i64 @test295(i64* %ptr, i64 %val) { |
| 5022 | ; PPC64LE-LABEL: test295: |
| 5023 | ; PPC64LE: # BB#0: |
| 5024 | ; PPC64LE-NEXT: .LBB295_1: |
| 5025 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 5026 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 5027 | ; PPC64LE-NEXT: bge 0, .LBB295_3 |
| 5028 | ; PPC64LE-NEXT: # BB#2: |
| 5029 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 5030 | ; PPC64LE-NEXT: bne 0, .LBB295_1 |
| 5031 | ; PPC64LE-NEXT: .LBB295_3: |
| 5032 | ; PPC64LE-NEXT: mr 3, 5 |
| 5033 | ; PPC64LE-NEXT: blr |
| 5034 | %ret = atomicrmw min i64* %ptr, i64 %val monotonic |
| 5035 | ret i64 %ret |
| 5036 | } |
| 5037 | |
| 5038 | define i64 @test296(i64* %ptr, i64 %val) { |
| 5039 | ; PPC64LE-LABEL: test296: |
| 5040 | ; PPC64LE: # BB#0: |
| 5041 | ; PPC64LE-NEXT: mr 5, 3 |
| 5042 | ; PPC64LE-NEXT: .LBB296_1: |
| 5043 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 5044 | ; PPC64LE-NEXT: cmpd 4, 3 |
| 5045 | ; PPC64LE-NEXT: bge 0, .LBB296_3 |
| 5046 | ; PPC64LE-NEXT: # BB#2: |
| 5047 | ; PPC64LE-NEXT: stdcx. 4, 0, 5 |
| 5048 | ; PPC64LE-NEXT: bne 0, .LBB296_1 |
| 5049 | ; PPC64LE-NEXT: .LBB296_3: |
| 5050 | ; PPC64LE-NEXT: lwsync |
| 5051 | ; PPC64LE-NEXT: blr |
| 5052 | %ret = atomicrmw min i64* %ptr, i64 %val acquire |
| 5053 | ret i64 %ret |
| 5054 | } |
| 5055 | |
| 5056 | define i64 @test297(i64* %ptr, i64 %val) { |
| 5057 | ; PPC64LE-LABEL: test297: |
| 5058 | ; PPC64LE: # BB#0: |
| 5059 | ; PPC64LE-NEXT: lwsync |
| 5060 | ; PPC64LE-NEXT: .LBB297_1: |
| 5061 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 5062 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 5063 | ; PPC64LE-NEXT: bge 0, .LBB297_3 |
| 5064 | ; PPC64LE-NEXT: # BB#2: |
| 5065 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 5066 | ; PPC64LE-NEXT: bne 0, .LBB297_1 |
| 5067 | ; PPC64LE-NEXT: .LBB297_3: |
| 5068 | ; PPC64LE-NEXT: mr 3, 5 |
| 5069 | ; PPC64LE-NEXT: blr |
| 5070 | %ret = atomicrmw min i64* %ptr, i64 %val release |
| 5071 | ret i64 %ret |
| 5072 | } |
| 5073 | |
| 5074 | define i64 @test298(i64* %ptr, i64 %val) { |
| 5075 | ; PPC64LE-LABEL: test298: |
| 5076 | ; PPC64LE: # BB#0: |
| 5077 | ; PPC64LE-NEXT: lwsync |
| 5078 | ; PPC64LE-NEXT: .LBB298_1: |
| 5079 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 5080 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 5081 | ; PPC64LE-NEXT: bge 0, .LBB298_3 |
| 5082 | ; PPC64LE-NEXT: # BB#2: |
| 5083 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 5084 | ; PPC64LE-NEXT: bne 0, .LBB298_1 |
| 5085 | ; PPC64LE-NEXT: .LBB298_3: |
| 5086 | ; PPC64LE-NEXT: mr 3, 5 |
| 5087 | ; PPC64LE-NEXT: lwsync |
| 5088 | ; PPC64LE-NEXT: blr |
| 5089 | %ret = atomicrmw min i64* %ptr, i64 %val acq_rel |
| 5090 | ret i64 %ret |
| 5091 | } |
| 5092 | |
| 5093 | define i64 @test299(i64* %ptr, i64 %val) { |
| 5094 | ; PPC64LE-LABEL: test299: |
| 5095 | ; PPC64LE: # BB#0: |
| 5096 | ; PPC64LE-NEXT: sync |
| 5097 | ; PPC64LE-NEXT: .LBB299_1: |
| 5098 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 5099 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 5100 | ; PPC64LE-NEXT: bge 0, .LBB299_3 |
| 5101 | ; PPC64LE-NEXT: # BB#2: |
| 5102 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 5103 | ; PPC64LE-NEXT: bne 0, .LBB299_1 |
| 5104 | ; PPC64LE-NEXT: .LBB299_3: |
| 5105 | ; PPC64LE-NEXT: mr 3, 5 |
| 5106 | ; PPC64LE-NEXT: lwsync |
| 5107 | ; PPC64LE-NEXT: blr |
| 5108 | %ret = atomicrmw min i64* %ptr, i64 %val seq_cst |
| 5109 | ret i64 %ret |
| 5110 | } |
| 5111 | |
| 5112 | define i8 @test300(i8* %ptr, i8 %val) { |
| 5113 | ; PPC64LE-LABEL: test300: |
| 5114 | ; PPC64LE: # BB#0: |
| 5115 | ; PPC64LE-NEXT: .LBB300_1: |
| 5116 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 5117 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5118 | ; PPC64LE-NEXT: ble 0, .LBB300_3 |
| 5119 | ; PPC64LE-NEXT: # BB#2: |
| 5120 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 5121 | ; PPC64LE-NEXT: bne 0, .LBB300_1 |
| 5122 | ; PPC64LE-NEXT: .LBB300_3: |
| 5123 | ; PPC64LE-NEXT: mr 3, 5 |
| 5124 | ; PPC64LE-NEXT: blr |
| 5125 | %ret = atomicrmw umax i8* %ptr, i8 %val monotonic |
| 5126 | ret i8 %ret |
| 5127 | } |
| 5128 | |
| 5129 | define i8 @test301(i8* %ptr, i8 %val) { |
| 5130 | ; PPC64LE-LABEL: test301: |
| 5131 | ; PPC64LE: # BB#0: |
| 5132 | ; PPC64LE-NEXT: mr 5, 3 |
| 5133 | ; PPC64LE-NEXT: .LBB301_1: |
| 5134 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 5135 | ; PPC64LE-NEXT: cmplw 4, 3 |
| 5136 | ; PPC64LE-NEXT: ble 0, .LBB301_3 |
| 5137 | ; PPC64LE-NEXT: # BB#2: |
| 5138 | ; PPC64LE-NEXT: stbcx. 4, 0, 5 |
| 5139 | ; PPC64LE-NEXT: bne 0, .LBB301_1 |
| 5140 | ; PPC64LE-NEXT: .LBB301_3: |
| 5141 | ; PPC64LE-NEXT: lwsync |
| 5142 | ; PPC64LE-NEXT: blr |
| 5143 | %ret = atomicrmw umax i8* %ptr, i8 %val acquire |
| 5144 | ret i8 %ret |
| 5145 | } |
| 5146 | |
| 5147 | define i8 @test302(i8* %ptr, i8 %val) { |
| 5148 | ; PPC64LE-LABEL: test302: |
| 5149 | ; PPC64LE: # BB#0: |
| 5150 | ; PPC64LE-NEXT: lwsync |
| 5151 | ; PPC64LE-NEXT: .LBB302_1: |
| 5152 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 5153 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5154 | ; PPC64LE-NEXT: ble 0, .LBB302_3 |
| 5155 | ; PPC64LE-NEXT: # BB#2: |
| 5156 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 5157 | ; PPC64LE-NEXT: bne 0, .LBB302_1 |
| 5158 | ; PPC64LE-NEXT: .LBB302_3: |
| 5159 | ; PPC64LE-NEXT: mr 3, 5 |
| 5160 | ; PPC64LE-NEXT: blr |
| 5161 | %ret = atomicrmw umax i8* %ptr, i8 %val release |
| 5162 | ret i8 %ret |
| 5163 | } |
| 5164 | |
| 5165 | define i8 @test303(i8* %ptr, i8 %val) { |
| 5166 | ; PPC64LE-LABEL: test303: |
| 5167 | ; PPC64LE: # BB#0: |
| 5168 | ; PPC64LE-NEXT: lwsync |
| 5169 | ; PPC64LE-NEXT: .LBB303_1: |
| 5170 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 5171 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5172 | ; PPC64LE-NEXT: ble 0, .LBB303_3 |
| 5173 | ; PPC64LE-NEXT: # BB#2: |
| 5174 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 5175 | ; PPC64LE-NEXT: bne 0, .LBB303_1 |
| 5176 | ; PPC64LE-NEXT: .LBB303_3: |
| 5177 | ; PPC64LE-NEXT: mr 3, 5 |
| 5178 | ; PPC64LE-NEXT: lwsync |
| 5179 | ; PPC64LE-NEXT: blr |
| 5180 | %ret = atomicrmw umax i8* %ptr, i8 %val acq_rel |
| 5181 | ret i8 %ret |
| 5182 | } |
| 5183 | |
| 5184 | define i8 @test304(i8* %ptr, i8 %val) { |
| 5185 | ; PPC64LE-LABEL: test304: |
| 5186 | ; PPC64LE: # BB#0: |
| 5187 | ; PPC64LE-NEXT: sync |
| 5188 | ; PPC64LE-NEXT: .LBB304_1: |
| 5189 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 5190 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5191 | ; PPC64LE-NEXT: ble 0, .LBB304_3 |
| 5192 | ; PPC64LE-NEXT: # BB#2: |
| 5193 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 5194 | ; PPC64LE-NEXT: bne 0, .LBB304_1 |
| 5195 | ; PPC64LE-NEXT: .LBB304_3: |
| 5196 | ; PPC64LE-NEXT: mr 3, 5 |
| 5197 | ; PPC64LE-NEXT: lwsync |
| 5198 | ; PPC64LE-NEXT: blr |
| 5199 | %ret = atomicrmw umax i8* %ptr, i8 %val seq_cst |
| 5200 | ret i8 %ret |
| 5201 | } |
| 5202 | |
| 5203 | define i16 @test305(i16* %ptr, i16 %val) { |
| 5204 | ; PPC64LE-LABEL: test305: |
| 5205 | ; PPC64LE: # BB#0: |
| 5206 | ; PPC64LE-NEXT: .LBB305_1: |
| 5207 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 5208 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5209 | ; PPC64LE-NEXT: ble 0, .LBB305_3 |
| 5210 | ; PPC64LE-NEXT: # BB#2: |
| 5211 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 5212 | ; PPC64LE-NEXT: bne 0, .LBB305_1 |
| 5213 | ; PPC64LE-NEXT: .LBB305_3: |
| 5214 | ; PPC64LE-NEXT: mr 3, 5 |
| 5215 | ; PPC64LE-NEXT: blr |
| 5216 | %ret = atomicrmw umax i16* %ptr, i16 %val monotonic |
| 5217 | ret i16 %ret |
| 5218 | } |
| 5219 | |
| 5220 | define i16 @test306(i16* %ptr, i16 %val) { |
| 5221 | ; PPC64LE-LABEL: test306: |
| 5222 | ; PPC64LE: # BB#0: |
| 5223 | ; PPC64LE-NEXT: mr 5, 3 |
| 5224 | ; PPC64LE-NEXT: .LBB306_1: |
| 5225 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 5226 | ; PPC64LE-NEXT: cmplw 4, 3 |
| 5227 | ; PPC64LE-NEXT: ble 0, .LBB306_3 |
| 5228 | ; PPC64LE-NEXT: # BB#2: |
| 5229 | ; PPC64LE-NEXT: sthcx. 4, 0, 5 |
| 5230 | ; PPC64LE-NEXT: bne 0, .LBB306_1 |
| 5231 | ; PPC64LE-NEXT: .LBB306_3: |
| 5232 | ; PPC64LE-NEXT: lwsync |
| 5233 | ; PPC64LE-NEXT: blr |
| 5234 | %ret = atomicrmw umax i16* %ptr, i16 %val acquire |
| 5235 | ret i16 %ret |
| 5236 | } |
| 5237 | |
| 5238 | define i16 @test307(i16* %ptr, i16 %val) { |
| 5239 | ; PPC64LE-LABEL: test307: |
| 5240 | ; PPC64LE: # BB#0: |
| 5241 | ; PPC64LE-NEXT: lwsync |
| 5242 | ; PPC64LE-NEXT: .LBB307_1: |
| 5243 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 5244 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5245 | ; PPC64LE-NEXT: ble 0, .LBB307_3 |
| 5246 | ; PPC64LE-NEXT: # BB#2: |
| 5247 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 5248 | ; PPC64LE-NEXT: bne 0, .LBB307_1 |
| 5249 | ; PPC64LE-NEXT: .LBB307_3: |
| 5250 | ; PPC64LE-NEXT: mr 3, 5 |
| 5251 | ; PPC64LE-NEXT: blr |
| 5252 | %ret = atomicrmw umax i16* %ptr, i16 %val release |
| 5253 | ret i16 %ret |
| 5254 | } |
| 5255 | |
| 5256 | define i16 @test308(i16* %ptr, i16 %val) { |
| 5257 | ; PPC64LE-LABEL: test308: |
| 5258 | ; PPC64LE: # BB#0: |
| 5259 | ; PPC64LE-NEXT: lwsync |
| 5260 | ; PPC64LE-NEXT: .LBB308_1: |
| 5261 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 5262 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5263 | ; PPC64LE-NEXT: ble 0, .LBB308_3 |
| 5264 | ; PPC64LE-NEXT: # BB#2: |
| 5265 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 5266 | ; PPC64LE-NEXT: bne 0, .LBB308_1 |
| 5267 | ; PPC64LE-NEXT: .LBB308_3: |
| 5268 | ; PPC64LE-NEXT: mr 3, 5 |
| 5269 | ; PPC64LE-NEXT: lwsync |
| 5270 | ; PPC64LE-NEXT: blr |
| 5271 | %ret = atomicrmw umax i16* %ptr, i16 %val acq_rel |
| 5272 | ret i16 %ret |
| 5273 | } |
| 5274 | |
| 5275 | define i16 @test309(i16* %ptr, i16 %val) { |
| 5276 | ; PPC64LE-LABEL: test309: |
| 5277 | ; PPC64LE: # BB#0: |
| 5278 | ; PPC64LE-NEXT: sync |
| 5279 | ; PPC64LE-NEXT: .LBB309_1: |
| 5280 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 5281 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5282 | ; PPC64LE-NEXT: ble 0, .LBB309_3 |
| 5283 | ; PPC64LE-NEXT: # BB#2: |
| 5284 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 5285 | ; PPC64LE-NEXT: bne 0, .LBB309_1 |
| 5286 | ; PPC64LE-NEXT: .LBB309_3: |
| 5287 | ; PPC64LE-NEXT: mr 3, 5 |
| 5288 | ; PPC64LE-NEXT: lwsync |
| 5289 | ; PPC64LE-NEXT: blr |
| 5290 | %ret = atomicrmw umax i16* %ptr, i16 %val seq_cst |
| 5291 | ret i16 %ret |
| 5292 | } |
| 5293 | |
| 5294 | define i32 @test310(i32* %ptr, i32 %val) { |
| 5295 | ; PPC64LE-LABEL: test310: |
| 5296 | ; PPC64LE: # BB#0: |
| 5297 | ; PPC64LE-NEXT: .LBB310_1: |
| 5298 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 5299 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5300 | ; PPC64LE-NEXT: ble 0, .LBB310_3 |
| 5301 | ; PPC64LE-NEXT: # BB#2: |
| 5302 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 5303 | ; PPC64LE-NEXT: bne 0, .LBB310_1 |
| 5304 | ; PPC64LE-NEXT: .LBB310_3: |
| 5305 | ; PPC64LE-NEXT: mr 3, 5 |
| 5306 | ; PPC64LE-NEXT: blr |
| 5307 | %ret = atomicrmw umax i32* %ptr, i32 %val monotonic |
| 5308 | ret i32 %ret |
| 5309 | } |
| 5310 | |
| 5311 | define i32 @test311(i32* %ptr, i32 %val) { |
| 5312 | ; PPC64LE-LABEL: test311: |
| 5313 | ; PPC64LE: # BB#0: |
| 5314 | ; PPC64LE-NEXT: mr 5, 3 |
| 5315 | ; PPC64LE-NEXT: .LBB311_1: |
| 5316 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 5317 | ; PPC64LE-NEXT: cmplw 4, 3 |
| 5318 | ; PPC64LE-NEXT: ble 0, .LBB311_3 |
| 5319 | ; PPC64LE-NEXT: # BB#2: |
| 5320 | ; PPC64LE-NEXT: stwcx. 4, 0, 5 |
| 5321 | ; PPC64LE-NEXT: bne 0, .LBB311_1 |
| 5322 | ; PPC64LE-NEXT: .LBB311_3: |
| 5323 | ; PPC64LE-NEXT: lwsync |
| 5324 | ; PPC64LE-NEXT: blr |
| 5325 | %ret = atomicrmw umax i32* %ptr, i32 %val acquire |
| 5326 | ret i32 %ret |
| 5327 | } |
| 5328 | |
| 5329 | define i32 @test312(i32* %ptr, i32 %val) { |
| 5330 | ; PPC64LE-LABEL: test312: |
| 5331 | ; PPC64LE: # BB#0: |
| 5332 | ; PPC64LE-NEXT: lwsync |
| 5333 | ; PPC64LE-NEXT: .LBB312_1: |
| 5334 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 5335 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5336 | ; PPC64LE-NEXT: ble 0, .LBB312_3 |
| 5337 | ; PPC64LE-NEXT: # BB#2: |
| 5338 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 5339 | ; PPC64LE-NEXT: bne 0, .LBB312_1 |
| 5340 | ; PPC64LE-NEXT: .LBB312_3: |
| 5341 | ; PPC64LE-NEXT: mr 3, 5 |
| 5342 | ; PPC64LE-NEXT: blr |
| 5343 | %ret = atomicrmw umax i32* %ptr, i32 %val release |
| 5344 | ret i32 %ret |
| 5345 | } |
| 5346 | |
| 5347 | define i32 @test313(i32* %ptr, i32 %val) { |
| 5348 | ; PPC64LE-LABEL: test313: |
| 5349 | ; PPC64LE: # BB#0: |
| 5350 | ; PPC64LE-NEXT: lwsync |
| 5351 | ; PPC64LE-NEXT: .LBB313_1: |
| 5352 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 5353 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5354 | ; PPC64LE-NEXT: ble 0, .LBB313_3 |
| 5355 | ; PPC64LE-NEXT: # BB#2: |
| 5356 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 5357 | ; PPC64LE-NEXT: bne 0, .LBB313_1 |
| 5358 | ; PPC64LE-NEXT: .LBB313_3: |
| 5359 | ; PPC64LE-NEXT: mr 3, 5 |
| 5360 | ; PPC64LE-NEXT: lwsync |
| 5361 | ; PPC64LE-NEXT: blr |
| 5362 | %ret = atomicrmw umax i32* %ptr, i32 %val acq_rel |
| 5363 | ret i32 %ret |
| 5364 | } |
| 5365 | |
| 5366 | define i32 @test314(i32* %ptr, i32 %val) { |
| 5367 | ; PPC64LE-LABEL: test314: |
| 5368 | ; PPC64LE: # BB#0: |
| 5369 | ; PPC64LE-NEXT: sync |
| 5370 | ; PPC64LE-NEXT: .LBB314_1: |
| 5371 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 5372 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5373 | ; PPC64LE-NEXT: ble 0, .LBB314_3 |
| 5374 | ; PPC64LE-NEXT: # BB#2: |
| 5375 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 5376 | ; PPC64LE-NEXT: bne 0, .LBB314_1 |
| 5377 | ; PPC64LE-NEXT: .LBB314_3: |
| 5378 | ; PPC64LE-NEXT: mr 3, 5 |
| 5379 | ; PPC64LE-NEXT: lwsync |
| 5380 | ; PPC64LE-NEXT: blr |
| 5381 | %ret = atomicrmw umax i32* %ptr, i32 %val seq_cst |
| 5382 | ret i32 %ret |
| 5383 | } |
| 5384 | |
| 5385 | define i64 @test315(i64* %ptr, i64 %val) { |
| 5386 | ; PPC64LE-LABEL: test315: |
| 5387 | ; PPC64LE: # BB#0: |
| 5388 | ; PPC64LE-NEXT: .LBB315_1: |
| 5389 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 5390 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 5391 | ; PPC64LE-NEXT: ble 0, .LBB315_3 |
| 5392 | ; PPC64LE-NEXT: # BB#2: |
| 5393 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 5394 | ; PPC64LE-NEXT: bne 0, .LBB315_1 |
| 5395 | ; PPC64LE-NEXT: .LBB315_3: |
| 5396 | ; PPC64LE-NEXT: mr 3, 5 |
| 5397 | ; PPC64LE-NEXT: blr |
| 5398 | %ret = atomicrmw umax i64* %ptr, i64 %val monotonic |
| 5399 | ret i64 %ret |
| 5400 | } |
| 5401 | |
| 5402 | define i64 @test316(i64* %ptr, i64 %val) { |
| 5403 | ; PPC64LE-LABEL: test316: |
| 5404 | ; PPC64LE: # BB#0: |
| 5405 | ; PPC64LE-NEXT: mr 5, 3 |
| 5406 | ; PPC64LE-NEXT: .LBB316_1: |
| 5407 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 5408 | ; PPC64LE-NEXT: cmpld 4, 3 |
| 5409 | ; PPC64LE-NEXT: ble 0, .LBB316_3 |
| 5410 | ; PPC64LE-NEXT: # BB#2: |
| 5411 | ; PPC64LE-NEXT: stdcx. 4, 0, 5 |
| 5412 | ; PPC64LE-NEXT: bne 0, .LBB316_1 |
| 5413 | ; PPC64LE-NEXT: .LBB316_3: |
| 5414 | ; PPC64LE-NEXT: lwsync |
| 5415 | ; PPC64LE-NEXT: blr |
| 5416 | %ret = atomicrmw umax i64* %ptr, i64 %val acquire |
| 5417 | ret i64 %ret |
| 5418 | } |
| 5419 | |
| 5420 | define i64 @test317(i64* %ptr, i64 %val) { |
| 5421 | ; PPC64LE-LABEL: test317: |
| 5422 | ; PPC64LE: # BB#0: |
| 5423 | ; PPC64LE-NEXT: lwsync |
| 5424 | ; PPC64LE-NEXT: .LBB317_1: |
| 5425 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 5426 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 5427 | ; PPC64LE-NEXT: ble 0, .LBB317_3 |
| 5428 | ; PPC64LE-NEXT: # BB#2: |
| 5429 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 5430 | ; PPC64LE-NEXT: bne 0, .LBB317_1 |
| 5431 | ; PPC64LE-NEXT: .LBB317_3: |
| 5432 | ; PPC64LE-NEXT: mr 3, 5 |
| 5433 | ; PPC64LE-NEXT: blr |
| 5434 | %ret = atomicrmw umax i64* %ptr, i64 %val release |
| 5435 | ret i64 %ret |
| 5436 | } |
| 5437 | |
| 5438 | define i64 @test318(i64* %ptr, i64 %val) { |
| 5439 | ; PPC64LE-LABEL: test318: |
| 5440 | ; PPC64LE: # BB#0: |
| 5441 | ; PPC64LE-NEXT: lwsync |
| 5442 | ; PPC64LE-NEXT: .LBB318_1: |
| 5443 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 5444 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 5445 | ; PPC64LE-NEXT: ble 0, .LBB318_3 |
| 5446 | ; PPC64LE-NEXT: # BB#2: |
| 5447 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 5448 | ; PPC64LE-NEXT: bne 0, .LBB318_1 |
| 5449 | ; PPC64LE-NEXT: .LBB318_3: |
| 5450 | ; PPC64LE-NEXT: mr 3, 5 |
| 5451 | ; PPC64LE-NEXT: lwsync |
| 5452 | ; PPC64LE-NEXT: blr |
| 5453 | %ret = atomicrmw umax i64* %ptr, i64 %val acq_rel |
| 5454 | ret i64 %ret |
| 5455 | } |
| 5456 | |
| 5457 | define i64 @test319(i64* %ptr, i64 %val) { |
| 5458 | ; PPC64LE-LABEL: test319: |
| 5459 | ; PPC64LE: # BB#0: |
| 5460 | ; PPC64LE-NEXT: sync |
| 5461 | ; PPC64LE-NEXT: .LBB319_1: |
| 5462 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 5463 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 5464 | ; PPC64LE-NEXT: ble 0, .LBB319_3 |
| 5465 | ; PPC64LE-NEXT: # BB#2: |
| 5466 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 5467 | ; PPC64LE-NEXT: bne 0, .LBB319_1 |
| 5468 | ; PPC64LE-NEXT: .LBB319_3: |
| 5469 | ; PPC64LE-NEXT: mr 3, 5 |
| 5470 | ; PPC64LE-NEXT: lwsync |
| 5471 | ; PPC64LE-NEXT: blr |
| 5472 | %ret = atomicrmw umax i64* %ptr, i64 %val seq_cst |
| 5473 | ret i64 %ret |
| 5474 | } |
| 5475 | |
| 5476 | define i8 @test320(i8* %ptr, i8 %val) { |
| 5477 | ; PPC64LE-LABEL: test320: |
| 5478 | ; PPC64LE: # BB#0: |
| 5479 | ; PPC64LE-NEXT: .LBB320_1: |
| 5480 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 5481 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5482 | ; PPC64LE-NEXT: bge 0, .LBB320_3 |
| 5483 | ; PPC64LE-NEXT: # BB#2: |
| 5484 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 5485 | ; PPC64LE-NEXT: bne 0, .LBB320_1 |
| 5486 | ; PPC64LE-NEXT: .LBB320_3: |
| 5487 | ; PPC64LE-NEXT: mr 3, 5 |
| 5488 | ; PPC64LE-NEXT: blr |
| 5489 | %ret = atomicrmw umin i8* %ptr, i8 %val monotonic |
| 5490 | ret i8 %ret |
| 5491 | } |
| 5492 | |
| 5493 | define i8 @test321(i8* %ptr, i8 %val) { |
| 5494 | ; PPC64LE-LABEL: test321: |
| 5495 | ; PPC64LE: # BB#0: |
| 5496 | ; PPC64LE-NEXT: mr 5, 3 |
| 5497 | ; PPC64LE-NEXT: .LBB321_1: |
| 5498 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 5499 | ; PPC64LE-NEXT: cmplw 4, 3 |
| 5500 | ; PPC64LE-NEXT: bge 0, .LBB321_3 |
| 5501 | ; PPC64LE-NEXT: # BB#2: |
| 5502 | ; PPC64LE-NEXT: stbcx. 4, 0, 5 |
| 5503 | ; PPC64LE-NEXT: bne 0, .LBB321_1 |
| 5504 | ; PPC64LE-NEXT: .LBB321_3: |
| 5505 | ; PPC64LE-NEXT: lwsync |
| 5506 | ; PPC64LE-NEXT: blr |
| 5507 | %ret = atomicrmw umin i8* %ptr, i8 %val acquire |
| 5508 | ret i8 %ret |
| 5509 | } |
| 5510 | |
| 5511 | define i8 @test322(i8* %ptr, i8 %val) { |
| 5512 | ; PPC64LE-LABEL: test322: |
| 5513 | ; PPC64LE: # BB#0: |
| 5514 | ; PPC64LE-NEXT: lwsync |
| 5515 | ; PPC64LE-NEXT: .LBB322_1: |
| 5516 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 5517 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5518 | ; PPC64LE-NEXT: bge 0, .LBB322_3 |
| 5519 | ; PPC64LE-NEXT: # BB#2: |
| 5520 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 5521 | ; PPC64LE-NEXT: bne 0, .LBB322_1 |
| 5522 | ; PPC64LE-NEXT: .LBB322_3: |
| 5523 | ; PPC64LE-NEXT: mr 3, 5 |
| 5524 | ; PPC64LE-NEXT: blr |
| 5525 | %ret = atomicrmw umin i8* %ptr, i8 %val release |
| 5526 | ret i8 %ret |
| 5527 | } |
| 5528 | |
| 5529 | define i8 @test323(i8* %ptr, i8 %val) { |
| 5530 | ; PPC64LE-LABEL: test323: |
| 5531 | ; PPC64LE: # BB#0: |
| 5532 | ; PPC64LE-NEXT: lwsync |
| 5533 | ; PPC64LE-NEXT: .LBB323_1: |
| 5534 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 5535 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5536 | ; PPC64LE-NEXT: bge 0, .LBB323_3 |
| 5537 | ; PPC64LE-NEXT: # BB#2: |
| 5538 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 5539 | ; PPC64LE-NEXT: bne 0, .LBB323_1 |
| 5540 | ; PPC64LE-NEXT: .LBB323_3: |
| 5541 | ; PPC64LE-NEXT: mr 3, 5 |
| 5542 | ; PPC64LE-NEXT: lwsync |
| 5543 | ; PPC64LE-NEXT: blr |
| 5544 | %ret = atomicrmw umin i8* %ptr, i8 %val acq_rel |
| 5545 | ret i8 %ret |
| 5546 | } |
| 5547 | |
| 5548 | define i8 @test324(i8* %ptr, i8 %val) { |
| 5549 | ; PPC64LE-LABEL: test324: |
| 5550 | ; PPC64LE: # BB#0: |
| 5551 | ; PPC64LE-NEXT: sync |
| 5552 | ; PPC64LE-NEXT: .LBB324_1: |
| 5553 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 5554 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5555 | ; PPC64LE-NEXT: bge 0, .LBB324_3 |
| 5556 | ; PPC64LE-NEXT: # BB#2: |
| 5557 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 5558 | ; PPC64LE-NEXT: bne 0, .LBB324_1 |
| 5559 | ; PPC64LE-NEXT: .LBB324_3: |
| 5560 | ; PPC64LE-NEXT: mr 3, 5 |
| 5561 | ; PPC64LE-NEXT: lwsync |
| 5562 | ; PPC64LE-NEXT: blr |
| 5563 | %ret = atomicrmw umin i8* %ptr, i8 %val seq_cst |
| 5564 | ret i8 %ret |
| 5565 | } |
| 5566 | |
| 5567 | define i16 @test325(i16* %ptr, i16 %val) { |
| 5568 | ; PPC64LE-LABEL: test325: |
| 5569 | ; PPC64LE: # BB#0: |
| 5570 | ; PPC64LE-NEXT: .LBB325_1: |
| 5571 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 5572 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5573 | ; PPC64LE-NEXT: bge 0, .LBB325_3 |
| 5574 | ; PPC64LE-NEXT: # BB#2: |
| 5575 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 5576 | ; PPC64LE-NEXT: bne 0, .LBB325_1 |
| 5577 | ; PPC64LE-NEXT: .LBB325_3: |
| 5578 | ; PPC64LE-NEXT: mr 3, 5 |
| 5579 | ; PPC64LE-NEXT: blr |
| 5580 | %ret = atomicrmw umin i16* %ptr, i16 %val monotonic |
| 5581 | ret i16 %ret |
| 5582 | } |
| 5583 | |
| 5584 | define i16 @test326(i16* %ptr, i16 %val) { |
| 5585 | ; PPC64LE-LABEL: test326: |
| 5586 | ; PPC64LE: # BB#0: |
| 5587 | ; PPC64LE-NEXT: mr 5, 3 |
| 5588 | ; PPC64LE-NEXT: .LBB326_1: |
| 5589 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 5590 | ; PPC64LE-NEXT: cmplw 4, 3 |
| 5591 | ; PPC64LE-NEXT: bge 0, .LBB326_3 |
| 5592 | ; PPC64LE-NEXT: # BB#2: |
| 5593 | ; PPC64LE-NEXT: sthcx. 4, 0, 5 |
| 5594 | ; PPC64LE-NEXT: bne 0, .LBB326_1 |
| 5595 | ; PPC64LE-NEXT: .LBB326_3: |
| 5596 | ; PPC64LE-NEXT: lwsync |
| 5597 | ; PPC64LE-NEXT: blr |
| 5598 | %ret = atomicrmw umin i16* %ptr, i16 %val acquire |
| 5599 | ret i16 %ret |
| 5600 | } |
| 5601 | |
| 5602 | define i16 @test327(i16* %ptr, i16 %val) { |
| 5603 | ; PPC64LE-LABEL: test327: |
| 5604 | ; PPC64LE: # BB#0: |
| 5605 | ; PPC64LE-NEXT: lwsync |
| 5606 | ; PPC64LE-NEXT: .LBB327_1: |
| 5607 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 5608 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5609 | ; PPC64LE-NEXT: bge 0, .LBB327_3 |
| 5610 | ; PPC64LE-NEXT: # BB#2: |
| 5611 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 5612 | ; PPC64LE-NEXT: bne 0, .LBB327_1 |
| 5613 | ; PPC64LE-NEXT: .LBB327_3: |
| 5614 | ; PPC64LE-NEXT: mr 3, 5 |
| 5615 | ; PPC64LE-NEXT: blr |
| 5616 | %ret = atomicrmw umin i16* %ptr, i16 %val release |
| 5617 | ret i16 %ret |
| 5618 | } |
| 5619 | |
| 5620 | define i16 @test328(i16* %ptr, i16 %val) { |
| 5621 | ; PPC64LE-LABEL: test328: |
| 5622 | ; PPC64LE: # BB#0: |
| 5623 | ; PPC64LE-NEXT: lwsync |
| 5624 | ; PPC64LE-NEXT: .LBB328_1: |
| 5625 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 5626 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5627 | ; PPC64LE-NEXT: bge 0, .LBB328_3 |
| 5628 | ; PPC64LE-NEXT: # BB#2: |
| 5629 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 5630 | ; PPC64LE-NEXT: bne 0, .LBB328_1 |
| 5631 | ; PPC64LE-NEXT: .LBB328_3: |
| 5632 | ; PPC64LE-NEXT: mr 3, 5 |
| 5633 | ; PPC64LE-NEXT: lwsync |
| 5634 | ; PPC64LE-NEXT: blr |
| 5635 | %ret = atomicrmw umin i16* %ptr, i16 %val acq_rel |
| 5636 | ret i16 %ret |
| 5637 | } |
| 5638 | |
| 5639 | define i16 @test329(i16* %ptr, i16 %val) { |
| 5640 | ; PPC64LE-LABEL: test329: |
| 5641 | ; PPC64LE: # BB#0: |
| 5642 | ; PPC64LE-NEXT: sync |
| 5643 | ; PPC64LE-NEXT: .LBB329_1: |
| 5644 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 5645 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5646 | ; PPC64LE-NEXT: bge 0, .LBB329_3 |
| 5647 | ; PPC64LE-NEXT: # BB#2: |
| 5648 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 5649 | ; PPC64LE-NEXT: bne 0, .LBB329_1 |
| 5650 | ; PPC64LE-NEXT: .LBB329_3: |
| 5651 | ; PPC64LE-NEXT: mr 3, 5 |
| 5652 | ; PPC64LE-NEXT: lwsync |
| 5653 | ; PPC64LE-NEXT: blr |
| 5654 | %ret = atomicrmw umin i16* %ptr, i16 %val seq_cst |
| 5655 | ret i16 %ret |
| 5656 | } |
| 5657 | |
| 5658 | define i32 @test330(i32* %ptr, i32 %val) { |
| 5659 | ; PPC64LE-LABEL: test330: |
| 5660 | ; PPC64LE: # BB#0: |
| 5661 | ; PPC64LE-NEXT: .LBB330_1: |
| 5662 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 5663 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5664 | ; PPC64LE-NEXT: bge 0, .LBB330_3 |
| 5665 | ; PPC64LE-NEXT: # BB#2: |
| 5666 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 5667 | ; PPC64LE-NEXT: bne 0, .LBB330_1 |
| 5668 | ; PPC64LE-NEXT: .LBB330_3: |
| 5669 | ; PPC64LE-NEXT: mr 3, 5 |
| 5670 | ; PPC64LE-NEXT: blr |
| 5671 | %ret = atomicrmw umin i32* %ptr, i32 %val monotonic |
| 5672 | ret i32 %ret |
| 5673 | } |
| 5674 | |
| 5675 | define i32 @test331(i32* %ptr, i32 %val) { |
| 5676 | ; PPC64LE-LABEL: test331: |
| 5677 | ; PPC64LE: # BB#0: |
| 5678 | ; PPC64LE-NEXT: mr 5, 3 |
| 5679 | ; PPC64LE-NEXT: .LBB331_1: |
| 5680 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 5681 | ; PPC64LE-NEXT: cmplw 4, 3 |
| 5682 | ; PPC64LE-NEXT: bge 0, .LBB331_3 |
| 5683 | ; PPC64LE-NEXT: # BB#2: |
| 5684 | ; PPC64LE-NEXT: stwcx. 4, 0, 5 |
| 5685 | ; PPC64LE-NEXT: bne 0, .LBB331_1 |
| 5686 | ; PPC64LE-NEXT: .LBB331_3: |
| 5687 | ; PPC64LE-NEXT: lwsync |
| 5688 | ; PPC64LE-NEXT: blr |
| 5689 | %ret = atomicrmw umin i32* %ptr, i32 %val acquire |
| 5690 | ret i32 %ret |
| 5691 | } |
| 5692 | |
| 5693 | define i32 @test332(i32* %ptr, i32 %val) { |
| 5694 | ; PPC64LE-LABEL: test332: |
| 5695 | ; PPC64LE: # BB#0: |
| 5696 | ; PPC64LE-NEXT: lwsync |
| 5697 | ; PPC64LE-NEXT: .LBB332_1: |
| 5698 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 5699 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5700 | ; PPC64LE-NEXT: bge 0, .LBB332_3 |
| 5701 | ; PPC64LE-NEXT: # BB#2: |
| 5702 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 5703 | ; PPC64LE-NEXT: bne 0, .LBB332_1 |
| 5704 | ; PPC64LE-NEXT: .LBB332_3: |
| 5705 | ; PPC64LE-NEXT: mr 3, 5 |
| 5706 | ; PPC64LE-NEXT: blr |
| 5707 | %ret = atomicrmw umin i32* %ptr, i32 %val release |
| 5708 | ret i32 %ret |
| 5709 | } |
| 5710 | |
| 5711 | define i32 @test333(i32* %ptr, i32 %val) { |
| 5712 | ; PPC64LE-LABEL: test333: |
| 5713 | ; PPC64LE: # BB#0: |
| 5714 | ; PPC64LE-NEXT: lwsync |
| 5715 | ; PPC64LE-NEXT: .LBB333_1: |
| 5716 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 5717 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5718 | ; PPC64LE-NEXT: bge 0, .LBB333_3 |
| 5719 | ; PPC64LE-NEXT: # BB#2: |
| 5720 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 5721 | ; PPC64LE-NEXT: bne 0, .LBB333_1 |
| 5722 | ; PPC64LE-NEXT: .LBB333_3: |
| 5723 | ; PPC64LE-NEXT: mr 3, 5 |
| 5724 | ; PPC64LE-NEXT: lwsync |
| 5725 | ; PPC64LE-NEXT: blr |
| 5726 | %ret = atomicrmw umin i32* %ptr, i32 %val acq_rel |
| 5727 | ret i32 %ret |
| 5728 | } |
| 5729 | |
| 5730 | define i32 @test334(i32* %ptr, i32 %val) { |
| 5731 | ; PPC64LE-LABEL: test334: |
| 5732 | ; PPC64LE: # BB#0: |
| 5733 | ; PPC64LE-NEXT: sync |
| 5734 | ; PPC64LE-NEXT: .LBB334_1: |
| 5735 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 5736 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 5737 | ; PPC64LE-NEXT: bge 0, .LBB334_3 |
| 5738 | ; PPC64LE-NEXT: # BB#2: |
| 5739 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 5740 | ; PPC64LE-NEXT: bne 0, .LBB334_1 |
| 5741 | ; PPC64LE-NEXT: .LBB334_3: |
| 5742 | ; PPC64LE-NEXT: mr 3, 5 |
| 5743 | ; PPC64LE-NEXT: lwsync |
| 5744 | ; PPC64LE-NEXT: blr |
| 5745 | %ret = atomicrmw umin i32* %ptr, i32 %val seq_cst |
| 5746 | ret i32 %ret |
| 5747 | } |
| 5748 | |
| 5749 | define i64 @test335(i64* %ptr, i64 %val) { |
| 5750 | ; PPC64LE-LABEL: test335: |
| 5751 | ; PPC64LE: # BB#0: |
| 5752 | ; PPC64LE-NEXT: .LBB335_1: |
| 5753 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 5754 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 5755 | ; PPC64LE-NEXT: bge 0, .LBB335_3 |
| 5756 | ; PPC64LE-NEXT: # BB#2: |
| 5757 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 5758 | ; PPC64LE-NEXT: bne 0, .LBB335_1 |
| 5759 | ; PPC64LE-NEXT: .LBB335_3: |
| 5760 | ; PPC64LE-NEXT: mr 3, 5 |
| 5761 | ; PPC64LE-NEXT: blr |
| 5762 | %ret = atomicrmw umin i64* %ptr, i64 %val monotonic |
| 5763 | ret i64 %ret |
| 5764 | } |
| 5765 | |
| 5766 | define i64 @test336(i64* %ptr, i64 %val) { |
| 5767 | ; PPC64LE-LABEL: test336: |
| 5768 | ; PPC64LE: # BB#0: |
| 5769 | ; PPC64LE-NEXT: mr 5, 3 |
| 5770 | ; PPC64LE-NEXT: .LBB336_1: |
| 5771 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 5772 | ; PPC64LE-NEXT: cmpld 4, 3 |
| 5773 | ; PPC64LE-NEXT: bge 0, .LBB336_3 |
| 5774 | ; PPC64LE-NEXT: # BB#2: |
| 5775 | ; PPC64LE-NEXT: stdcx. 4, 0, 5 |
| 5776 | ; PPC64LE-NEXT: bne 0, .LBB336_1 |
| 5777 | ; PPC64LE-NEXT: .LBB336_3: |
| 5778 | ; PPC64LE-NEXT: lwsync |
| 5779 | ; PPC64LE-NEXT: blr |
| 5780 | %ret = atomicrmw umin i64* %ptr, i64 %val acquire |
| 5781 | ret i64 %ret |
| 5782 | } |
| 5783 | |
| 5784 | define i64 @test337(i64* %ptr, i64 %val) { |
| 5785 | ; PPC64LE-LABEL: test337: |
| 5786 | ; PPC64LE: # BB#0: |
| 5787 | ; PPC64LE-NEXT: lwsync |
| 5788 | ; PPC64LE-NEXT: .LBB337_1: |
| 5789 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 5790 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 5791 | ; PPC64LE-NEXT: bge 0, .LBB337_3 |
| 5792 | ; PPC64LE-NEXT: # BB#2: |
| 5793 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 5794 | ; PPC64LE-NEXT: bne 0, .LBB337_1 |
| 5795 | ; PPC64LE-NEXT: .LBB337_3: |
| 5796 | ; PPC64LE-NEXT: mr 3, 5 |
| 5797 | ; PPC64LE-NEXT: blr |
| 5798 | %ret = atomicrmw umin i64* %ptr, i64 %val release |
| 5799 | ret i64 %ret |
| 5800 | } |
| 5801 | |
| 5802 | define i64 @test338(i64* %ptr, i64 %val) { |
| 5803 | ; PPC64LE-LABEL: test338: |
| 5804 | ; PPC64LE: # BB#0: |
| 5805 | ; PPC64LE-NEXT: lwsync |
| 5806 | ; PPC64LE-NEXT: .LBB338_1: |
| 5807 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 5808 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 5809 | ; PPC64LE-NEXT: bge 0, .LBB338_3 |
| 5810 | ; PPC64LE-NEXT: # BB#2: |
| 5811 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 5812 | ; PPC64LE-NEXT: bne 0, .LBB338_1 |
| 5813 | ; PPC64LE-NEXT: .LBB338_3: |
| 5814 | ; PPC64LE-NEXT: mr 3, 5 |
| 5815 | ; PPC64LE-NEXT: lwsync |
| 5816 | ; PPC64LE-NEXT: blr |
| 5817 | %ret = atomicrmw umin i64* %ptr, i64 %val acq_rel |
| 5818 | ret i64 %ret |
| 5819 | } |
| 5820 | |
| 5821 | define i64 @test339(i64* %ptr, i64 %val) { |
| 5822 | ; PPC64LE-LABEL: test339: |
| 5823 | ; PPC64LE: # BB#0: |
| 5824 | ; PPC64LE-NEXT: sync |
| 5825 | ; PPC64LE-NEXT: .LBB339_1: |
| 5826 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 5827 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 5828 | ; PPC64LE-NEXT: bge 0, .LBB339_3 |
| 5829 | ; PPC64LE-NEXT: # BB#2: |
| 5830 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 5831 | ; PPC64LE-NEXT: bne 0, .LBB339_1 |
| 5832 | ; PPC64LE-NEXT: .LBB339_3: |
| 5833 | ; PPC64LE-NEXT: mr 3, 5 |
| 5834 | ; PPC64LE-NEXT: lwsync |
| 5835 | ; PPC64LE-NEXT: blr |
| 5836 | %ret = atomicrmw umin i64* %ptr, i64 %val seq_cst |
| 5837 | ret i64 %ret |
| 5838 | } |
| 5839 | |
| 5840 | define i8 @test340(i8* %ptr, i8 %val) { |
| 5841 | ; PPC64LE-LABEL: test340: |
| 5842 | ; PPC64LE: # BB#0: |
| 5843 | ; PPC64LE-NEXT: .LBB340_1: |
| 5844 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 5845 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 5846 | ; PPC64LE-NEXT: bne 0, .LBB340_1 |
| 5847 | ; PPC64LE-NEXT: # BB#2: |
| 5848 | ; PPC64LE-NEXT: mr 3, 5 |
| 5849 | ; PPC64LE-NEXT: blr |
| 5850 | %ret = atomicrmw xchg i8* %ptr, i8 %val singlethread monotonic |
| 5851 | ret i8 %ret |
| 5852 | } |
| 5853 | |
| 5854 | define i8 @test341(i8* %ptr, i8 %val) { |
| 5855 | ; PPC64LE-LABEL: test341: |
| 5856 | ; PPC64LE: # BB#0: |
| 5857 | ; PPC64LE-NEXT: mr 5, 3 |
| 5858 | ; PPC64LE-NEXT: .LBB341_1: |
| 5859 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 5860 | ; PPC64LE-NEXT: stbcx. 4, 0, 5 |
| 5861 | ; PPC64LE-NEXT: bne 0, .LBB341_1 |
| 5862 | ; PPC64LE-NEXT: # BB#2: |
| 5863 | ; PPC64LE-NEXT: lwsync |
| 5864 | ; PPC64LE-NEXT: blr |
| 5865 | %ret = atomicrmw xchg i8* %ptr, i8 %val singlethread acquire |
| 5866 | ret i8 %ret |
| 5867 | } |
| 5868 | |
| 5869 | define i8 @test342(i8* %ptr, i8 %val) { |
| 5870 | ; PPC64LE-LABEL: test342: |
| 5871 | ; PPC64LE: # BB#0: |
| 5872 | ; PPC64LE-NEXT: lwsync |
| 5873 | ; PPC64LE-NEXT: .LBB342_1: |
| 5874 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 5875 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 5876 | ; PPC64LE-NEXT: bne 0, .LBB342_1 |
| 5877 | ; PPC64LE-NEXT: # BB#2: |
| 5878 | ; PPC64LE-NEXT: mr 3, 5 |
| 5879 | ; PPC64LE-NEXT: blr |
| 5880 | %ret = atomicrmw xchg i8* %ptr, i8 %val singlethread release |
| 5881 | ret i8 %ret |
| 5882 | } |
| 5883 | |
| 5884 | define i8 @test343(i8* %ptr, i8 %val) { |
| 5885 | ; PPC64LE-LABEL: test343: |
| 5886 | ; PPC64LE: # BB#0: |
| 5887 | ; PPC64LE-NEXT: lwsync |
| 5888 | ; PPC64LE-NEXT: .LBB343_1: |
| 5889 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 5890 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 5891 | ; PPC64LE-NEXT: bne 0, .LBB343_1 |
| 5892 | ; PPC64LE-NEXT: # BB#2: |
| 5893 | ; PPC64LE-NEXT: mr 3, 5 |
| 5894 | ; PPC64LE-NEXT: lwsync |
| 5895 | ; PPC64LE-NEXT: blr |
| 5896 | %ret = atomicrmw xchg i8* %ptr, i8 %val singlethread acq_rel |
| 5897 | ret i8 %ret |
| 5898 | } |
| 5899 | |
| 5900 | define i8 @test344(i8* %ptr, i8 %val) { |
| 5901 | ; PPC64LE-LABEL: test344: |
| 5902 | ; PPC64LE: # BB#0: |
| 5903 | ; PPC64LE-NEXT: sync |
| 5904 | ; PPC64LE-NEXT: .LBB344_1: |
| 5905 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 5906 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 5907 | ; PPC64LE-NEXT: bne 0, .LBB344_1 |
| 5908 | ; PPC64LE-NEXT: # BB#2: |
| 5909 | ; PPC64LE-NEXT: mr 3, 5 |
| 5910 | ; PPC64LE-NEXT: lwsync |
| 5911 | ; PPC64LE-NEXT: blr |
| 5912 | %ret = atomicrmw xchg i8* %ptr, i8 %val singlethread seq_cst |
| 5913 | ret i8 %ret |
| 5914 | } |
| 5915 | |
| 5916 | define i16 @test345(i16* %ptr, i16 %val) { |
| 5917 | ; PPC64LE-LABEL: test345: |
| 5918 | ; PPC64LE: # BB#0: |
| 5919 | ; PPC64LE-NEXT: .LBB345_1: |
| 5920 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 5921 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 5922 | ; PPC64LE-NEXT: bne 0, .LBB345_1 |
| 5923 | ; PPC64LE-NEXT: # BB#2: |
| 5924 | ; PPC64LE-NEXT: mr 3, 5 |
| 5925 | ; PPC64LE-NEXT: blr |
| 5926 | %ret = atomicrmw xchg i16* %ptr, i16 %val singlethread monotonic |
| 5927 | ret i16 %ret |
| 5928 | } |
| 5929 | |
| 5930 | define i16 @test346(i16* %ptr, i16 %val) { |
| 5931 | ; PPC64LE-LABEL: test346: |
| 5932 | ; PPC64LE: # BB#0: |
| 5933 | ; PPC64LE-NEXT: mr 5, 3 |
| 5934 | ; PPC64LE-NEXT: .LBB346_1: |
| 5935 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 5936 | ; PPC64LE-NEXT: sthcx. 4, 0, 5 |
| 5937 | ; PPC64LE-NEXT: bne 0, .LBB346_1 |
| 5938 | ; PPC64LE-NEXT: # BB#2: |
| 5939 | ; PPC64LE-NEXT: lwsync |
| 5940 | ; PPC64LE-NEXT: blr |
| 5941 | %ret = atomicrmw xchg i16* %ptr, i16 %val singlethread acquire |
| 5942 | ret i16 %ret |
| 5943 | } |
| 5944 | |
| 5945 | define i16 @test347(i16* %ptr, i16 %val) { |
| 5946 | ; PPC64LE-LABEL: test347: |
| 5947 | ; PPC64LE: # BB#0: |
| 5948 | ; PPC64LE-NEXT: lwsync |
| 5949 | ; PPC64LE-NEXT: .LBB347_1: |
| 5950 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 5951 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 5952 | ; PPC64LE-NEXT: bne 0, .LBB347_1 |
| 5953 | ; PPC64LE-NEXT: # BB#2: |
| 5954 | ; PPC64LE-NEXT: mr 3, 5 |
| 5955 | ; PPC64LE-NEXT: blr |
| 5956 | %ret = atomicrmw xchg i16* %ptr, i16 %val singlethread release |
| 5957 | ret i16 %ret |
| 5958 | } |
| 5959 | |
| 5960 | define i16 @test348(i16* %ptr, i16 %val) { |
| 5961 | ; PPC64LE-LABEL: test348: |
| 5962 | ; PPC64LE: # BB#0: |
| 5963 | ; PPC64LE-NEXT: lwsync |
| 5964 | ; PPC64LE-NEXT: .LBB348_1: |
| 5965 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 5966 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 5967 | ; PPC64LE-NEXT: bne 0, .LBB348_1 |
| 5968 | ; PPC64LE-NEXT: # BB#2: |
| 5969 | ; PPC64LE-NEXT: mr 3, 5 |
| 5970 | ; PPC64LE-NEXT: lwsync |
| 5971 | ; PPC64LE-NEXT: blr |
| 5972 | %ret = atomicrmw xchg i16* %ptr, i16 %val singlethread acq_rel |
| 5973 | ret i16 %ret |
| 5974 | } |
| 5975 | |
| 5976 | define i16 @test349(i16* %ptr, i16 %val) { |
| 5977 | ; PPC64LE-LABEL: test349: |
| 5978 | ; PPC64LE: # BB#0: |
| 5979 | ; PPC64LE-NEXT: sync |
| 5980 | ; PPC64LE-NEXT: .LBB349_1: |
| 5981 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 5982 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 5983 | ; PPC64LE-NEXT: bne 0, .LBB349_1 |
| 5984 | ; PPC64LE-NEXT: # BB#2: |
| 5985 | ; PPC64LE-NEXT: mr 3, 5 |
| 5986 | ; PPC64LE-NEXT: lwsync |
| 5987 | ; PPC64LE-NEXT: blr |
| 5988 | %ret = atomicrmw xchg i16* %ptr, i16 %val singlethread seq_cst |
| 5989 | ret i16 %ret |
| 5990 | } |
| 5991 | |
| 5992 | define i32 @test350(i32* %ptr, i32 %val) { |
| 5993 | ; PPC64LE-LABEL: test350: |
| 5994 | ; PPC64LE: # BB#0: |
| 5995 | ; PPC64LE-NEXT: .LBB350_1: |
| 5996 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 5997 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 5998 | ; PPC64LE-NEXT: bne 0, .LBB350_1 |
| 5999 | ; PPC64LE-NEXT: # BB#2: |
| 6000 | ; PPC64LE-NEXT: mr 3, 5 |
| 6001 | ; PPC64LE-NEXT: blr |
| 6002 | %ret = atomicrmw xchg i32* %ptr, i32 %val singlethread monotonic |
| 6003 | ret i32 %ret |
| 6004 | } |
| 6005 | |
| 6006 | define i32 @test351(i32* %ptr, i32 %val) { |
| 6007 | ; PPC64LE-LABEL: test351: |
| 6008 | ; PPC64LE: # BB#0: |
| 6009 | ; PPC64LE-NEXT: mr 5, 3 |
| 6010 | ; PPC64LE-NEXT: .LBB351_1: |
| 6011 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 6012 | ; PPC64LE-NEXT: stwcx. 4, 0, 5 |
| 6013 | ; PPC64LE-NEXT: bne 0, .LBB351_1 |
| 6014 | ; PPC64LE-NEXT: # BB#2: |
| 6015 | ; PPC64LE-NEXT: lwsync |
| 6016 | ; PPC64LE-NEXT: blr |
| 6017 | %ret = atomicrmw xchg i32* %ptr, i32 %val singlethread acquire |
| 6018 | ret i32 %ret |
| 6019 | } |
| 6020 | |
| 6021 | define i32 @test352(i32* %ptr, i32 %val) { |
| 6022 | ; PPC64LE-LABEL: test352: |
| 6023 | ; PPC64LE: # BB#0: |
| 6024 | ; PPC64LE-NEXT: lwsync |
| 6025 | ; PPC64LE-NEXT: .LBB352_1: |
| 6026 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6027 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 6028 | ; PPC64LE-NEXT: bne 0, .LBB352_1 |
| 6029 | ; PPC64LE-NEXT: # BB#2: |
| 6030 | ; PPC64LE-NEXT: mr 3, 5 |
| 6031 | ; PPC64LE-NEXT: blr |
| 6032 | %ret = atomicrmw xchg i32* %ptr, i32 %val singlethread release |
| 6033 | ret i32 %ret |
| 6034 | } |
| 6035 | |
| 6036 | define i32 @test353(i32* %ptr, i32 %val) { |
| 6037 | ; PPC64LE-LABEL: test353: |
| 6038 | ; PPC64LE: # BB#0: |
| 6039 | ; PPC64LE-NEXT: lwsync |
| 6040 | ; PPC64LE-NEXT: .LBB353_1: |
| 6041 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6042 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 6043 | ; PPC64LE-NEXT: bne 0, .LBB353_1 |
| 6044 | ; PPC64LE-NEXT: # BB#2: |
| 6045 | ; PPC64LE-NEXT: mr 3, 5 |
| 6046 | ; PPC64LE-NEXT: lwsync |
| 6047 | ; PPC64LE-NEXT: blr |
| 6048 | %ret = atomicrmw xchg i32* %ptr, i32 %val singlethread acq_rel |
| 6049 | ret i32 %ret |
| 6050 | } |
| 6051 | |
| 6052 | define i32 @test354(i32* %ptr, i32 %val) { |
| 6053 | ; PPC64LE-LABEL: test354: |
| 6054 | ; PPC64LE: # BB#0: |
| 6055 | ; PPC64LE-NEXT: sync |
| 6056 | ; PPC64LE-NEXT: .LBB354_1: |
| 6057 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6058 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 6059 | ; PPC64LE-NEXT: bne 0, .LBB354_1 |
| 6060 | ; PPC64LE-NEXT: # BB#2: |
| 6061 | ; PPC64LE-NEXT: mr 3, 5 |
| 6062 | ; PPC64LE-NEXT: lwsync |
| 6063 | ; PPC64LE-NEXT: blr |
| 6064 | %ret = atomicrmw xchg i32* %ptr, i32 %val singlethread seq_cst |
| 6065 | ret i32 %ret |
| 6066 | } |
| 6067 | |
| 6068 | define i64 @test355(i64* %ptr, i64 %val) { |
| 6069 | ; PPC64LE-LABEL: test355: |
| 6070 | ; PPC64LE: # BB#0: |
| 6071 | ; PPC64LE-NEXT: .LBB355_1: |
| 6072 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 6073 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 6074 | ; PPC64LE-NEXT: bne 0, .LBB355_1 |
| 6075 | ; PPC64LE-NEXT: # BB#2: |
| 6076 | ; PPC64LE-NEXT: mr 3, 5 |
| 6077 | ; PPC64LE-NEXT: blr |
| 6078 | %ret = atomicrmw xchg i64* %ptr, i64 %val singlethread monotonic |
| 6079 | ret i64 %ret |
| 6080 | } |
| 6081 | |
| 6082 | define i64 @test356(i64* %ptr, i64 %val) { |
| 6083 | ; PPC64LE-LABEL: test356: |
| 6084 | ; PPC64LE: # BB#0: |
| 6085 | ; PPC64LE-NEXT: mr 5, 3 |
| 6086 | ; PPC64LE-NEXT: .LBB356_1: |
| 6087 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 6088 | ; PPC64LE-NEXT: stdcx. 4, 0, 5 |
| 6089 | ; PPC64LE-NEXT: bne 0, .LBB356_1 |
| 6090 | ; PPC64LE-NEXT: # BB#2: |
| 6091 | ; PPC64LE-NEXT: lwsync |
| 6092 | ; PPC64LE-NEXT: blr |
| 6093 | %ret = atomicrmw xchg i64* %ptr, i64 %val singlethread acquire |
| 6094 | ret i64 %ret |
| 6095 | } |
| 6096 | |
| 6097 | define i64 @test357(i64* %ptr, i64 %val) { |
| 6098 | ; PPC64LE-LABEL: test357: |
| 6099 | ; PPC64LE: # BB#0: |
| 6100 | ; PPC64LE-NEXT: lwsync |
| 6101 | ; PPC64LE-NEXT: .LBB357_1: |
| 6102 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 6103 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 6104 | ; PPC64LE-NEXT: bne 0, .LBB357_1 |
| 6105 | ; PPC64LE-NEXT: # BB#2: |
| 6106 | ; PPC64LE-NEXT: mr 3, 5 |
| 6107 | ; PPC64LE-NEXT: blr |
| 6108 | %ret = atomicrmw xchg i64* %ptr, i64 %val singlethread release |
| 6109 | ret i64 %ret |
| 6110 | } |
| 6111 | |
| 6112 | define i64 @test358(i64* %ptr, i64 %val) { |
| 6113 | ; PPC64LE-LABEL: test358: |
| 6114 | ; PPC64LE: # BB#0: |
| 6115 | ; PPC64LE-NEXT: lwsync |
| 6116 | ; PPC64LE-NEXT: .LBB358_1: |
| 6117 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 6118 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 6119 | ; PPC64LE-NEXT: bne 0, .LBB358_1 |
| 6120 | ; PPC64LE-NEXT: # BB#2: |
| 6121 | ; PPC64LE-NEXT: mr 3, 5 |
| 6122 | ; PPC64LE-NEXT: lwsync |
| 6123 | ; PPC64LE-NEXT: blr |
| 6124 | %ret = atomicrmw xchg i64* %ptr, i64 %val singlethread acq_rel |
| 6125 | ret i64 %ret |
| 6126 | } |
| 6127 | |
| 6128 | define i64 @test359(i64* %ptr, i64 %val) { |
| 6129 | ; PPC64LE-LABEL: test359: |
| 6130 | ; PPC64LE: # BB#0: |
| 6131 | ; PPC64LE-NEXT: sync |
| 6132 | ; PPC64LE-NEXT: .LBB359_1: |
| 6133 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 6134 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 6135 | ; PPC64LE-NEXT: bne 0, .LBB359_1 |
| 6136 | ; PPC64LE-NEXT: # BB#2: |
| 6137 | ; PPC64LE-NEXT: mr 3, 5 |
| 6138 | ; PPC64LE-NEXT: lwsync |
| 6139 | ; PPC64LE-NEXT: blr |
| 6140 | %ret = atomicrmw xchg i64* %ptr, i64 %val singlethread seq_cst |
| 6141 | ret i64 %ret |
| 6142 | } |
| 6143 | |
| 6144 | define i8 @test360(i8* %ptr, i8 %val) { |
| 6145 | ; PPC64LE-LABEL: test360: |
| 6146 | ; PPC64LE: # BB#0: |
| 6147 | ; PPC64LE-NEXT: .LBB360_1: |
| 6148 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 6149 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6150 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 6151 | ; PPC64LE-NEXT: bne 0, .LBB360_1 |
| 6152 | ; PPC64LE-NEXT: # BB#2: |
| 6153 | ; PPC64LE-NEXT: mr 3, 5 |
| 6154 | ; PPC64LE-NEXT: blr |
| 6155 | %ret = atomicrmw add i8* %ptr, i8 %val singlethread monotonic |
| 6156 | ret i8 %ret |
| 6157 | } |
| 6158 | |
| 6159 | define i8 @test361(i8* %ptr, i8 %val) { |
| 6160 | ; PPC64LE-LABEL: test361: |
| 6161 | ; PPC64LE: # BB#0: |
| 6162 | ; PPC64LE-NEXT: mr 5, 3 |
| 6163 | ; PPC64LE-NEXT: .LBB361_1: |
| 6164 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 6165 | ; PPC64LE-NEXT: add 6, 4, 3 |
| 6166 | ; PPC64LE-NEXT: stbcx. 6, 0, 5 |
| 6167 | ; PPC64LE-NEXT: bne 0, .LBB361_1 |
| 6168 | ; PPC64LE-NEXT: # BB#2: |
| 6169 | ; PPC64LE-NEXT: lwsync |
| 6170 | ; PPC64LE-NEXT: blr |
| 6171 | %ret = atomicrmw add i8* %ptr, i8 %val singlethread acquire |
| 6172 | ret i8 %ret |
| 6173 | } |
| 6174 | |
| 6175 | define i8 @test362(i8* %ptr, i8 %val) { |
| 6176 | ; PPC64LE-LABEL: test362: |
| 6177 | ; PPC64LE: # BB#0: |
| 6178 | ; PPC64LE-NEXT: lwsync |
| 6179 | ; PPC64LE-NEXT: .LBB362_1: |
| 6180 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 6181 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6182 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 6183 | ; PPC64LE-NEXT: bne 0, .LBB362_1 |
| 6184 | ; PPC64LE-NEXT: # BB#2: |
| 6185 | ; PPC64LE-NEXT: mr 3, 5 |
| 6186 | ; PPC64LE-NEXT: blr |
| 6187 | %ret = atomicrmw add i8* %ptr, i8 %val singlethread release |
| 6188 | ret i8 %ret |
| 6189 | } |
| 6190 | |
| 6191 | define i8 @test363(i8* %ptr, i8 %val) { |
| 6192 | ; PPC64LE-LABEL: test363: |
| 6193 | ; PPC64LE: # BB#0: |
| 6194 | ; PPC64LE-NEXT: lwsync |
| 6195 | ; PPC64LE-NEXT: .LBB363_1: |
| 6196 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 6197 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6198 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 6199 | ; PPC64LE-NEXT: bne 0, .LBB363_1 |
| 6200 | ; PPC64LE-NEXT: # BB#2: |
| 6201 | ; PPC64LE-NEXT: mr 3, 5 |
| 6202 | ; PPC64LE-NEXT: lwsync |
| 6203 | ; PPC64LE-NEXT: blr |
| 6204 | %ret = atomicrmw add i8* %ptr, i8 %val singlethread acq_rel |
| 6205 | ret i8 %ret |
| 6206 | } |
| 6207 | |
| 6208 | define i8 @test364(i8* %ptr, i8 %val) { |
| 6209 | ; PPC64LE-LABEL: test364: |
| 6210 | ; PPC64LE: # BB#0: |
| 6211 | ; PPC64LE-NEXT: sync |
| 6212 | ; PPC64LE-NEXT: .LBB364_1: |
| 6213 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 6214 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6215 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 6216 | ; PPC64LE-NEXT: bne 0, .LBB364_1 |
| 6217 | ; PPC64LE-NEXT: # BB#2: |
| 6218 | ; PPC64LE-NEXT: mr 3, 5 |
| 6219 | ; PPC64LE-NEXT: lwsync |
| 6220 | ; PPC64LE-NEXT: blr |
| 6221 | %ret = atomicrmw add i8* %ptr, i8 %val singlethread seq_cst |
| 6222 | ret i8 %ret |
| 6223 | } |
| 6224 | |
| 6225 | define i16 @test365(i16* %ptr, i16 %val) { |
| 6226 | ; PPC64LE-LABEL: test365: |
| 6227 | ; PPC64LE: # BB#0: |
| 6228 | ; PPC64LE-NEXT: .LBB365_1: |
| 6229 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 6230 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6231 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 6232 | ; PPC64LE-NEXT: bne 0, .LBB365_1 |
| 6233 | ; PPC64LE-NEXT: # BB#2: |
| 6234 | ; PPC64LE-NEXT: mr 3, 5 |
| 6235 | ; PPC64LE-NEXT: blr |
| 6236 | %ret = atomicrmw add i16* %ptr, i16 %val singlethread monotonic |
| 6237 | ret i16 %ret |
| 6238 | } |
| 6239 | |
| 6240 | define i16 @test366(i16* %ptr, i16 %val) { |
| 6241 | ; PPC64LE-LABEL: test366: |
| 6242 | ; PPC64LE: # BB#0: |
| 6243 | ; PPC64LE-NEXT: mr 5, 3 |
| 6244 | ; PPC64LE-NEXT: .LBB366_1: |
| 6245 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 6246 | ; PPC64LE-NEXT: add 6, 4, 3 |
| 6247 | ; PPC64LE-NEXT: sthcx. 6, 0, 5 |
| 6248 | ; PPC64LE-NEXT: bne 0, .LBB366_1 |
| 6249 | ; PPC64LE-NEXT: # BB#2: |
| 6250 | ; PPC64LE-NEXT: lwsync |
| 6251 | ; PPC64LE-NEXT: blr |
| 6252 | %ret = atomicrmw add i16* %ptr, i16 %val singlethread acquire |
| 6253 | ret i16 %ret |
| 6254 | } |
| 6255 | |
| 6256 | define i16 @test367(i16* %ptr, i16 %val) { |
| 6257 | ; PPC64LE-LABEL: test367: |
| 6258 | ; PPC64LE: # BB#0: |
| 6259 | ; PPC64LE-NEXT: lwsync |
| 6260 | ; PPC64LE-NEXT: .LBB367_1: |
| 6261 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 6262 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6263 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 6264 | ; PPC64LE-NEXT: bne 0, .LBB367_1 |
| 6265 | ; PPC64LE-NEXT: # BB#2: |
| 6266 | ; PPC64LE-NEXT: mr 3, 5 |
| 6267 | ; PPC64LE-NEXT: blr |
| 6268 | %ret = atomicrmw add i16* %ptr, i16 %val singlethread release |
| 6269 | ret i16 %ret |
| 6270 | } |
| 6271 | |
| 6272 | define i16 @test368(i16* %ptr, i16 %val) { |
| 6273 | ; PPC64LE-LABEL: test368: |
| 6274 | ; PPC64LE: # BB#0: |
| 6275 | ; PPC64LE-NEXT: lwsync |
| 6276 | ; PPC64LE-NEXT: .LBB368_1: |
| 6277 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 6278 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6279 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 6280 | ; PPC64LE-NEXT: bne 0, .LBB368_1 |
| 6281 | ; PPC64LE-NEXT: # BB#2: |
| 6282 | ; PPC64LE-NEXT: mr 3, 5 |
| 6283 | ; PPC64LE-NEXT: lwsync |
| 6284 | ; PPC64LE-NEXT: blr |
| 6285 | %ret = atomicrmw add i16* %ptr, i16 %val singlethread acq_rel |
| 6286 | ret i16 %ret |
| 6287 | } |
| 6288 | |
| 6289 | define i16 @test369(i16* %ptr, i16 %val) { |
| 6290 | ; PPC64LE-LABEL: test369: |
| 6291 | ; PPC64LE: # BB#0: |
| 6292 | ; PPC64LE-NEXT: sync |
| 6293 | ; PPC64LE-NEXT: .LBB369_1: |
| 6294 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 6295 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6296 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 6297 | ; PPC64LE-NEXT: bne 0, .LBB369_1 |
| 6298 | ; PPC64LE-NEXT: # BB#2: |
| 6299 | ; PPC64LE-NEXT: mr 3, 5 |
| 6300 | ; PPC64LE-NEXT: lwsync |
| 6301 | ; PPC64LE-NEXT: blr |
| 6302 | %ret = atomicrmw add i16* %ptr, i16 %val singlethread seq_cst |
| 6303 | ret i16 %ret |
| 6304 | } |
| 6305 | |
| 6306 | define i32 @test370(i32* %ptr, i32 %val) { |
| 6307 | ; PPC64LE-LABEL: test370: |
| 6308 | ; PPC64LE: # BB#0: |
| 6309 | ; PPC64LE-NEXT: .LBB370_1: |
| 6310 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6311 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6312 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 6313 | ; PPC64LE-NEXT: bne 0, .LBB370_1 |
| 6314 | ; PPC64LE-NEXT: # BB#2: |
| 6315 | ; PPC64LE-NEXT: mr 3, 5 |
| 6316 | ; PPC64LE-NEXT: blr |
| 6317 | %ret = atomicrmw add i32* %ptr, i32 %val singlethread monotonic |
| 6318 | ret i32 %ret |
| 6319 | } |
| 6320 | |
| 6321 | define i32 @test371(i32* %ptr, i32 %val) { |
| 6322 | ; PPC64LE-LABEL: test371: |
| 6323 | ; PPC64LE: # BB#0: |
| 6324 | ; PPC64LE-NEXT: mr 5, 3 |
| 6325 | ; PPC64LE-NEXT: .LBB371_1: |
| 6326 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 6327 | ; PPC64LE-NEXT: add 6, 4, 3 |
| 6328 | ; PPC64LE-NEXT: stwcx. 6, 0, 5 |
| 6329 | ; PPC64LE-NEXT: bne 0, .LBB371_1 |
| 6330 | ; PPC64LE-NEXT: # BB#2: |
| 6331 | ; PPC64LE-NEXT: lwsync |
| 6332 | ; PPC64LE-NEXT: blr |
| 6333 | %ret = atomicrmw add i32* %ptr, i32 %val singlethread acquire |
| 6334 | ret i32 %ret |
| 6335 | } |
| 6336 | |
| 6337 | define i32 @test372(i32* %ptr, i32 %val) { |
| 6338 | ; PPC64LE-LABEL: test372: |
| 6339 | ; PPC64LE: # BB#0: |
| 6340 | ; PPC64LE-NEXT: lwsync |
| 6341 | ; PPC64LE-NEXT: .LBB372_1: |
| 6342 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6343 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6344 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 6345 | ; PPC64LE-NEXT: bne 0, .LBB372_1 |
| 6346 | ; PPC64LE-NEXT: # BB#2: |
| 6347 | ; PPC64LE-NEXT: mr 3, 5 |
| 6348 | ; PPC64LE-NEXT: blr |
| 6349 | %ret = atomicrmw add i32* %ptr, i32 %val singlethread release |
| 6350 | ret i32 %ret |
| 6351 | } |
| 6352 | |
| 6353 | define i32 @test373(i32* %ptr, i32 %val) { |
| 6354 | ; PPC64LE-LABEL: test373: |
| 6355 | ; PPC64LE: # BB#0: |
| 6356 | ; PPC64LE-NEXT: lwsync |
| 6357 | ; PPC64LE-NEXT: .LBB373_1: |
| 6358 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6359 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6360 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 6361 | ; PPC64LE-NEXT: bne 0, .LBB373_1 |
| 6362 | ; PPC64LE-NEXT: # BB#2: |
| 6363 | ; PPC64LE-NEXT: mr 3, 5 |
| 6364 | ; PPC64LE-NEXT: lwsync |
| 6365 | ; PPC64LE-NEXT: blr |
| 6366 | %ret = atomicrmw add i32* %ptr, i32 %val singlethread acq_rel |
| 6367 | ret i32 %ret |
| 6368 | } |
| 6369 | |
| 6370 | define i32 @test374(i32* %ptr, i32 %val) { |
| 6371 | ; PPC64LE-LABEL: test374: |
| 6372 | ; PPC64LE: # BB#0: |
| 6373 | ; PPC64LE-NEXT: sync |
| 6374 | ; PPC64LE-NEXT: .LBB374_1: |
| 6375 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6376 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6377 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 6378 | ; PPC64LE-NEXT: bne 0, .LBB374_1 |
| 6379 | ; PPC64LE-NEXT: # BB#2: |
| 6380 | ; PPC64LE-NEXT: mr 3, 5 |
| 6381 | ; PPC64LE-NEXT: lwsync |
| 6382 | ; PPC64LE-NEXT: blr |
| 6383 | %ret = atomicrmw add i32* %ptr, i32 %val singlethread seq_cst |
| 6384 | ret i32 %ret |
| 6385 | } |
| 6386 | |
| 6387 | define i64 @test375(i64* %ptr, i64 %val) { |
| 6388 | ; PPC64LE-LABEL: test375: |
| 6389 | ; PPC64LE: # BB#0: |
| 6390 | ; PPC64LE-NEXT: .LBB375_1: |
| 6391 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 6392 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6393 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 6394 | ; PPC64LE-NEXT: bne 0, .LBB375_1 |
| 6395 | ; PPC64LE-NEXT: # BB#2: |
| 6396 | ; PPC64LE-NEXT: mr 3, 5 |
| 6397 | ; PPC64LE-NEXT: blr |
| 6398 | %ret = atomicrmw add i64* %ptr, i64 %val singlethread monotonic |
| 6399 | ret i64 %ret |
| 6400 | } |
| 6401 | |
| 6402 | define i64 @test376(i64* %ptr, i64 %val) { |
| 6403 | ; PPC64LE-LABEL: test376: |
| 6404 | ; PPC64LE: # BB#0: |
| 6405 | ; PPC64LE-NEXT: mr 5, 3 |
| 6406 | ; PPC64LE-NEXT: .LBB376_1: |
| 6407 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 6408 | ; PPC64LE-NEXT: add 6, 4, 3 |
| 6409 | ; PPC64LE-NEXT: stdcx. 6, 0, 5 |
| 6410 | ; PPC64LE-NEXT: bne 0, .LBB376_1 |
| 6411 | ; PPC64LE-NEXT: # BB#2: |
| 6412 | ; PPC64LE-NEXT: lwsync |
| 6413 | ; PPC64LE-NEXT: blr |
| 6414 | %ret = atomicrmw add i64* %ptr, i64 %val singlethread acquire |
| 6415 | ret i64 %ret |
| 6416 | } |
| 6417 | |
| 6418 | define i64 @test377(i64* %ptr, i64 %val) { |
| 6419 | ; PPC64LE-LABEL: test377: |
| 6420 | ; PPC64LE: # BB#0: |
| 6421 | ; PPC64LE-NEXT: lwsync |
| 6422 | ; PPC64LE-NEXT: .LBB377_1: |
| 6423 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 6424 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6425 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 6426 | ; PPC64LE-NEXT: bne 0, .LBB377_1 |
| 6427 | ; PPC64LE-NEXT: # BB#2: |
| 6428 | ; PPC64LE-NEXT: mr 3, 5 |
| 6429 | ; PPC64LE-NEXT: blr |
| 6430 | %ret = atomicrmw add i64* %ptr, i64 %val singlethread release |
| 6431 | ret i64 %ret |
| 6432 | } |
| 6433 | |
| 6434 | define i64 @test378(i64* %ptr, i64 %val) { |
| 6435 | ; PPC64LE-LABEL: test378: |
| 6436 | ; PPC64LE: # BB#0: |
| 6437 | ; PPC64LE-NEXT: lwsync |
| 6438 | ; PPC64LE-NEXT: .LBB378_1: |
| 6439 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 6440 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6441 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 6442 | ; PPC64LE-NEXT: bne 0, .LBB378_1 |
| 6443 | ; PPC64LE-NEXT: # BB#2: |
| 6444 | ; PPC64LE-NEXT: mr 3, 5 |
| 6445 | ; PPC64LE-NEXT: lwsync |
| 6446 | ; PPC64LE-NEXT: blr |
| 6447 | %ret = atomicrmw add i64* %ptr, i64 %val singlethread acq_rel |
| 6448 | ret i64 %ret |
| 6449 | } |
| 6450 | |
| 6451 | define i64 @test379(i64* %ptr, i64 %val) { |
| 6452 | ; PPC64LE-LABEL: test379: |
| 6453 | ; PPC64LE: # BB#0: |
| 6454 | ; PPC64LE-NEXT: sync |
| 6455 | ; PPC64LE-NEXT: .LBB379_1: |
| 6456 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 6457 | ; PPC64LE-NEXT: add 6, 4, 5 |
| 6458 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 6459 | ; PPC64LE-NEXT: bne 0, .LBB379_1 |
| 6460 | ; PPC64LE-NEXT: # BB#2: |
| 6461 | ; PPC64LE-NEXT: mr 3, 5 |
| 6462 | ; PPC64LE-NEXT: lwsync |
| 6463 | ; PPC64LE-NEXT: blr |
| 6464 | %ret = atomicrmw add i64* %ptr, i64 %val singlethread seq_cst |
| 6465 | ret i64 %ret |
| 6466 | } |
| 6467 | |
| 6468 | define i8 @test380(i8* %ptr, i8 %val) { |
| 6469 | ; PPC64LE-LABEL: test380: |
| 6470 | ; PPC64LE: # BB#0: |
| 6471 | ; PPC64LE-NEXT: .LBB380_1: |
| 6472 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 6473 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 6474 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 6475 | ; PPC64LE-NEXT: bne 0, .LBB380_1 |
| 6476 | ; PPC64LE-NEXT: # BB#2: |
| 6477 | ; PPC64LE-NEXT: mr 3, 5 |
| 6478 | ; PPC64LE-NEXT: blr |
| 6479 | %ret = atomicrmw sub i8* %ptr, i8 %val singlethread monotonic |
| 6480 | ret i8 %ret |
| 6481 | } |
| 6482 | |
| 6483 | define i8 @test381(i8* %ptr, i8 %val) { |
| 6484 | ; PPC64LE-LABEL: test381: |
| 6485 | ; PPC64LE: # BB#0: |
| 6486 | ; PPC64LE-NEXT: mr 5, 3 |
| 6487 | ; PPC64LE-NEXT: .LBB381_1: |
| 6488 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 6489 | ; PPC64LE-NEXT: subf 6, 4, 3 |
| 6490 | ; PPC64LE-NEXT: stbcx. 6, 0, 5 |
| 6491 | ; PPC64LE-NEXT: bne 0, .LBB381_1 |
| 6492 | ; PPC64LE-NEXT: # BB#2: |
| 6493 | ; PPC64LE-NEXT: lwsync |
| 6494 | ; PPC64LE-NEXT: blr |
| 6495 | %ret = atomicrmw sub i8* %ptr, i8 %val singlethread acquire |
| 6496 | ret i8 %ret |
| 6497 | } |
| 6498 | |
| 6499 | define i8 @test382(i8* %ptr, i8 %val) { |
| 6500 | ; PPC64LE-LABEL: test382: |
| 6501 | ; PPC64LE: # BB#0: |
| 6502 | ; PPC64LE-NEXT: lwsync |
| 6503 | ; PPC64LE-NEXT: .LBB382_1: |
| 6504 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 6505 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 6506 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 6507 | ; PPC64LE-NEXT: bne 0, .LBB382_1 |
| 6508 | ; PPC64LE-NEXT: # BB#2: |
| 6509 | ; PPC64LE-NEXT: mr 3, 5 |
| 6510 | ; PPC64LE-NEXT: blr |
| 6511 | %ret = atomicrmw sub i8* %ptr, i8 %val singlethread release |
| 6512 | ret i8 %ret |
| 6513 | } |
| 6514 | |
| 6515 | define i8 @test383(i8* %ptr, i8 %val) { |
| 6516 | ; PPC64LE-LABEL: test383: |
| 6517 | ; PPC64LE: # BB#0: |
| 6518 | ; PPC64LE-NEXT: lwsync |
| 6519 | ; PPC64LE-NEXT: .LBB383_1: |
| 6520 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 6521 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 6522 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 6523 | ; PPC64LE-NEXT: bne 0, .LBB383_1 |
| 6524 | ; PPC64LE-NEXT: # BB#2: |
| 6525 | ; PPC64LE-NEXT: mr 3, 5 |
| 6526 | ; PPC64LE-NEXT: lwsync |
| 6527 | ; PPC64LE-NEXT: blr |
| 6528 | %ret = atomicrmw sub i8* %ptr, i8 %val singlethread acq_rel |
| 6529 | ret i8 %ret |
| 6530 | } |
| 6531 | |
| 6532 | define i8 @test384(i8* %ptr, i8 %val) { |
| 6533 | ; PPC64LE-LABEL: test384: |
| 6534 | ; PPC64LE: # BB#0: |
| 6535 | ; PPC64LE-NEXT: sync |
| 6536 | ; PPC64LE-NEXT: .LBB384_1: |
| 6537 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 6538 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 6539 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 6540 | ; PPC64LE-NEXT: bne 0, .LBB384_1 |
| 6541 | ; PPC64LE-NEXT: # BB#2: |
| 6542 | ; PPC64LE-NEXT: mr 3, 5 |
| 6543 | ; PPC64LE-NEXT: lwsync |
| 6544 | ; PPC64LE-NEXT: blr |
| 6545 | %ret = atomicrmw sub i8* %ptr, i8 %val singlethread seq_cst |
| 6546 | ret i8 %ret |
| 6547 | } |
| 6548 | |
| 6549 | define i16 @test385(i16* %ptr, i16 %val) { |
| 6550 | ; PPC64LE-LABEL: test385: |
| 6551 | ; PPC64LE: # BB#0: |
| 6552 | ; PPC64LE-NEXT: .LBB385_1: |
| 6553 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 6554 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 6555 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 6556 | ; PPC64LE-NEXT: bne 0, .LBB385_1 |
| 6557 | ; PPC64LE-NEXT: # BB#2: |
| 6558 | ; PPC64LE-NEXT: mr 3, 5 |
| 6559 | ; PPC64LE-NEXT: blr |
| 6560 | %ret = atomicrmw sub i16* %ptr, i16 %val singlethread monotonic |
| 6561 | ret i16 %ret |
| 6562 | } |
| 6563 | |
| 6564 | define i16 @test386(i16* %ptr, i16 %val) { |
| 6565 | ; PPC64LE-LABEL: test386: |
| 6566 | ; PPC64LE: # BB#0: |
| 6567 | ; PPC64LE-NEXT: mr 5, 3 |
| 6568 | ; PPC64LE-NEXT: .LBB386_1: |
| 6569 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 6570 | ; PPC64LE-NEXT: subf 6, 4, 3 |
| 6571 | ; PPC64LE-NEXT: sthcx. 6, 0, 5 |
| 6572 | ; PPC64LE-NEXT: bne 0, .LBB386_1 |
| 6573 | ; PPC64LE-NEXT: # BB#2: |
| 6574 | ; PPC64LE-NEXT: lwsync |
| 6575 | ; PPC64LE-NEXT: blr |
| 6576 | %ret = atomicrmw sub i16* %ptr, i16 %val singlethread acquire |
| 6577 | ret i16 %ret |
| 6578 | } |
| 6579 | |
| 6580 | define i16 @test387(i16* %ptr, i16 %val) { |
| 6581 | ; PPC64LE-LABEL: test387: |
| 6582 | ; PPC64LE: # BB#0: |
| 6583 | ; PPC64LE-NEXT: lwsync |
| 6584 | ; PPC64LE-NEXT: .LBB387_1: |
| 6585 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 6586 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 6587 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 6588 | ; PPC64LE-NEXT: bne 0, .LBB387_1 |
| 6589 | ; PPC64LE-NEXT: # BB#2: |
| 6590 | ; PPC64LE-NEXT: mr 3, 5 |
| 6591 | ; PPC64LE-NEXT: blr |
| 6592 | %ret = atomicrmw sub i16* %ptr, i16 %val singlethread release |
| 6593 | ret i16 %ret |
| 6594 | } |
| 6595 | |
| 6596 | define i16 @test388(i16* %ptr, i16 %val) { |
| 6597 | ; PPC64LE-LABEL: test388: |
| 6598 | ; PPC64LE: # BB#0: |
| 6599 | ; PPC64LE-NEXT: lwsync |
| 6600 | ; PPC64LE-NEXT: .LBB388_1: |
| 6601 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 6602 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 6603 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 6604 | ; PPC64LE-NEXT: bne 0, .LBB388_1 |
| 6605 | ; PPC64LE-NEXT: # BB#2: |
| 6606 | ; PPC64LE-NEXT: mr 3, 5 |
| 6607 | ; PPC64LE-NEXT: lwsync |
| 6608 | ; PPC64LE-NEXT: blr |
| 6609 | %ret = atomicrmw sub i16* %ptr, i16 %val singlethread acq_rel |
| 6610 | ret i16 %ret |
| 6611 | } |
| 6612 | |
| 6613 | define i16 @test389(i16* %ptr, i16 %val) { |
| 6614 | ; PPC64LE-LABEL: test389: |
| 6615 | ; PPC64LE: # BB#0: |
| 6616 | ; PPC64LE-NEXT: sync |
| 6617 | ; PPC64LE-NEXT: .LBB389_1: |
| 6618 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 6619 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 6620 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 6621 | ; PPC64LE-NEXT: bne 0, .LBB389_1 |
| 6622 | ; PPC64LE-NEXT: # BB#2: |
| 6623 | ; PPC64LE-NEXT: mr 3, 5 |
| 6624 | ; PPC64LE-NEXT: lwsync |
| 6625 | ; PPC64LE-NEXT: blr |
| 6626 | %ret = atomicrmw sub i16* %ptr, i16 %val singlethread seq_cst |
| 6627 | ret i16 %ret |
| 6628 | } |
| 6629 | |
| 6630 | define i32 @test390(i32* %ptr, i32 %val) { |
| 6631 | ; PPC64LE-LABEL: test390: |
| 6632 | ; PPC64LE: # BB#0: |
| 6633 | ; PPC64LE-NEXT: .LBB390_1: |
| 6634 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6635 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 6636 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 6637 | ; PPC64LE-NEXT: bne 0, .LBB390_1 |
| 6638 | ; PPC64LE-NEXT: # BB#2: |
| 6639 | ; PPC64LE-NEXT: mr 3, 5 |
| 6640 | ; PPC64LE-NEXT: blr |
| 6641 | %ret = atomicrmw sub i32* %ptr, i32 %val singlethread monotonic |
| 6642 | ret i32 %ret |
| 6643 | } |
| 6644 | |
| 6645 | define i32 @test391(i32* %ptr, i32 %val) { |
| 6646 | ; PPC64LE-LABEL: test391: |
| 6647 | ; PPC64LE: # BB#0: |
| 6648 | ; PPC64LE-NEXT: mr 5, 3 |
| 6649 | ; PPC64LE-NEXT: .LBB391_1: |
| 6650 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 6651 | ; PPC64LE-NEXT: subf 6, 4, 3 |
| 6652 | ; PPC64LE-NEXT: stwcx. 6, 0, 5 |
| 6653 | ; PPC64LE-NEXT: bne 0, .LBB391_1 |
| 6654 | ; PPC64LE-NEXT: # BB#2: |
| 6655 | ; PPC64LE-NEXT: lwsync |
| 6656 | ; PPC64LE-NEXT: blr |
| 6657 | %ret = atomicrmw sub i32* %ptr, i32 %val singlethread acquire |
| 6658 | ret i32 %ret |
| 6659 | } |
| 6660 | |
| 6661 | define i32 @test392(i32* %ptr, i32 %val) { |
| 6662 | ; PPC64LE-LABEL: test392: |
| 6663 | ; PPC64LE: # BB#0: |
| 6664 | ; PPC64LE-NEXT: lwsync |
| 6665 | ; PPC64LE-NEXT: .LBB392_1: |
| 6666 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6667 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 6668 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 6669 | ; PPC64LE-NEXT: bne 0, .LBB392_1 |
| 6670 | ; PPC64LE-NEXT: # BB#2: |
| 6671 | ; PPC64LE-NEXT: mr 3, 5 |
| 6672 | ; PPC64LE-NEXT: blr |
| 6673 | %ret = atomicrmw sub i32* %ptr, i32 %val singlethread release |
| 6674 | ret i32 %ret |
| 6675 | } |
| 6676 | |
| 6677 | define i32 @test393(i32* %ptr, i32 %val) { |
| 6678 | ; PPC64LE-LABEL: test393: |
| 6679 | ; PPC64LE: # BB#0: |
| 6680 | ; PPC64LE-NEXT: lwsync |
| 6681 | ; PPC64LE-NEXT: .LBB393_1: |
| 6682 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6683 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 6684 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 6685 | ; PPC64LE-NEXT: bne 0, .LBB393_1 |
| 6686 | ; PPC64LE-NEXT: # BB#2: |
| 6687 | ; PPC64LE-NEXT: mr 3, 5 |
| 6688 | ; PPC64LE-NEXT: lwsync |
| 6689 | ; PPC64LE-NEXT: blr |
| 6690 | %ret = atomicrmw sub i32* %ptr, i32 %val singlethread acq_rel |
| 6691 | ret i32 %ret |
| 6692 | } |
| 6693 | |
| 6694 | define i32 @test394(i32* %ptr, i32 %val) { |
| 6695 | ; PPC64LE-LABEL: test394: |
| 6696 | ; PPC64LE: # BB#0: |
| 6697 | ; PPC64LE-NEXT: sync |
| 6698 | ; PPC64LE-NEXT: .LBB394_1: |
| 6699 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6700 | ; PPC64LE-NEXT: subf 6, 4, 5 |
| 6701 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 6702 | ; PPC64LE-NEXT: bne 0, .LBB394_1 |
| 6703 | ; PPC64LE-NEXT: # BB#2: |
| 6704 | ; PPC64LE-NEXT: mr 3, 5 |
| 6705 | ; PPC64LE-NEXT: lwsync |
| 6706 | ; PPC64LE-NEXT: blr |
| 6707 | %ret = atomicrmw sub i32* %ptr, i32 %val singlethread seq_cst |
| 6708 | ret i32 %ret |
| 6709 | } |
| 6710 | |
| 6711 | define i64 @test395(i64* %ptr, i64 %val) { |
| 6712 | ; PPC64LE-LABEL: test395: |
| 6713 | ; PPC64LE: # BB#0: |
| 6714 | ; PPC64LE-NEXT: .LBB395_1: |
| 6715 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 6716 | ; PPC64LE-NEXT: sub 6, 5, 4 |
| 6717 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 6718 | ; PPC64LE-NEXT: bne 0, .LBB395_1 |
| 6719 | ; PPC64LE-NEXT: # BB#2: |
| 6720 | ; PPC64LE-NEXT: mr 3, 5 |
| 6721 | ; PPC64LE-NEXT: blr |
| 6722 | %ret = atomicrmw sub i64* %ptr, i64 %val singlethread monotonic |
| 6723 | ret i64 %ret |
| 6724 | } |
| 6725 | |
| 6726 | define i64 @test396(i64* %ptr, i64 %val) { |
| 6727 | ; PPC64LE-LABEL: test396: |
| 6728 | ; PPC64LE: # BB#0: |
| 6729 | ; PPC64LE-NEXT: mr 5, 3 |
| 6730 | ; PPC64LE-NEXT: .LBB396_1: |
| 6731 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 6732 | ; PPC64LE-NEXT: sub 6, 3, 4 |
| 6733 | ; PPC64LE-NEXT: stdcx. 6, 0, 5 |
| 6734 | ; PPC64LE-NEXT: bne 0, .LBB396_1 |
| 6735 | ; PPC64LE-NEXT: # BB#2: |
| 6736 | ; PPC64LE-NEXT: lwsync |
| 6737 | ; PPC64LE-NEXT: blr |
| 6738 | %ret = atomicrmw sub i64* %ptr, i64 %val singlethread acquire |
| 6739 | ret i64 %ret |
| 6740 | } |
| 6741 | |
| 6742 | define i64 @test397(i64* %ptr, i64 %val) { |
| 6743 | ; PPC64LE-LABEL: test397: |
| 6744 | ; PPC64LE: # BB#0: |
| 6745 | ; PPC64LE-NEXT: lwsync |
| 6746 | ; PPC64LE-NEXT: .LBB397_1: |
| 6747 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 6748 | ; PPC64LE-NEXT: sub 6, 5, 4 |
| 6749 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 6750 | ; PPC64LE-NEXT: bne 0, .LBB397_1 |
| 6751 | ; PPC64LE-NEXT: # BB#2: |
| 6752 | ; PPC64LE-NEXT: mr 3, 5 |
| 6753 | ; PPC64LE-NEXT: blr |
| 6754 | %ret = atomicrmw sub i64* %ptr, i64 %val singlethread release |
| 6755 | ret i64 %ret |
| 6756 | } |
| 6757 | |
| 6758 | define i64 @test398(i64* %ptr, i64 %val) { |
| 6759 | ; PPC64LE-LABEL: test398: |
| 6760 | ; PPC64LE: # BB#0: |
| 6761 | ; PPC64LE-NEXT: lwsync |
| 6762 | ; PPC64LE-NEXT: .LBB398_1: |
| 6763 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 6764 | ; PPC64LE-NEXT: sub 6, 5, 4 |
| 6765 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 6766 | ; PPC64LE-NEXT: bne 0, .LBB398_1 |
| 6767 | ; PPC64LE-NEXT: # BB#2: |
| 6768 | ; PPC64LE-NEXT: mr 3, 5 |
| 6769 | ; PPC64LE-NEXT: lwsync |
| 6770 | ; PPC64LE-NEXT: blr |
| 6771 | %ret = atomicrmw sub i64* %ptr, i64 %val singlethread acq_rel |
| 6772 | ret i64 %ret |
| 6773 | } |
| 6774 | |
| 6775 | define i64 @test399(i64* %ptr, i64 %val) { |
| 6776 | ; PPC64LE-LABEL: test399: |
| 6777 | ; PPC64LE: # BB#0: |
| 6778 | ; PPC64LE-NEXT: sync |
| 6779 | ; PPC64LE-NEXT: .LBB399_1: |
| 6780 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 6781 | ; PPC64LE-NEXT: sub 6, 5, 4 |
| 6782 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 6783 | ; PPC64LE-NEXT: bne 0, .LBB399_1 |
| 6784 | ; PPC64LE-NEXT: # BB#2: |
| 6785 | ; PPC64LE-NEXT: mr 3, 5 |
| 6786 | ; PPC64LE-NEXT: lwsync |
| 6787 | ; PPC64LE-NEXT: blr |
| 6788 | %ret = atomicrmw sub i64* %ptr, i64 %val singlethread seq_cst |
| 6789 | ret i64 %ret |
| 6790 | } |
| 6791 | |
| 6792 | define i8 @test400(i8* %ptr, i8 %val) { |
| 6793 | ; PPC64LE-LABEL: test400: |
| 6794 | ; PPC64LE: # BB#0: |
| 6795 | ; PPC64LE-NEXT: .LBB400_1: |
| 6796 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 6797 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 6798 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 6799 | ; PPC64LE-NEXT: bne 0, .LBB400_1 |
| 6800 | ; PPC64LE-NEXT: # BB#2: |
| 6801 | ; PPC64LE-NEXT: mr 3, 5 |
| 6802 | ; PPC64LE-NEXT: blr |
| 6803 | %ret = atomicrmw and i8* %ptr, i8 %val singlethread monotonic |
| 6804 | ret i8 %ret |
| 6805 | } |
| 6806 | |
| 6807 | define i8 @test401(i8* %ptr, i8 %val) { |
| 6808 | ; PPC64LE-LABEL: test401: |
| 6809 | ; PPC64LE: # BB#0: |
| 6810 | ; PPC64LE-NEXT: mr 5, 3 |
| 6811 | ; PPC64LE-NEXT: .LBB401_1: |
| 6812 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 6813 | ; PPC64LE-NEXT: and 6, 4, 3 |
| 6814 | ; PPC64LE-NEXT: stbcx. 6, 0, 5 |
| 6815 | ; PPC64LE-NEXT: bne 0, .LBB401_1 |
| 6816 | ; PPC64LE-NEXT: # BB#2: |
| 6817 | ; PPC64LE-NEXT: lwsync |
| 6818 | ; PPC64LE-NEXT: blr |
| 6819 | %ret = atomicrmw and i8* %ptr, i8 %val singlethread acquire |
| 6820 | ret i8 %ret |
| 6821 | } |
| 6822 | |
| 6823 | define i8 @test402(i8* %ptr, i8 %val) { |
| 6824 | ; PPC64LE-LABEL: test402: |
| 6825 | ; PPC64LE: # BB#0: |
| 6826 | ; PPC64LE-NEXT: lwsync |
| 6827 | ; PPC64LE-NEXT: .LBB402_1: |
| 6828 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 6829 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 6830 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 6831 | ; PPC64LE-NEXT: bne 0, .LBB402_1 |
| 6832 | ; PPC64LE-NEXT: # BB#2: |
| 6833 | ; PPC64LE-NEXT: mr 3, 5 |
| 6834 | ; PPC64LE-NEXT: blr |
| 6835 | %ret = atomicrmw and i8* %ptr, i8 %val singlethread release |
| 6836 | ret i8 %ret |
| 6837 | } |
| 6838 | |
| 6839 | define i8 @test403(i8* %ptr, i8 %val) { |
| 6840 | ; PPC64LE-LABEL: test403: |
| 6841 | ; PPC64LE: # BB#0: |
| 6842 | ; PPC64LE-NEXT: lwsync |
| 6843 | ; PPC64LE-NEXT: .LBB403_1: |
| 6844 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 6845 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 6846 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 6847 | ; PPC64LE-NEXT: bne 0, .LBB403_1 |
| 6848 | ; PPC64LE-NEXT: # BB#2: |
| 6849 | ; PPC64LE-NEXT: mr 3, 5 |
| 6850 | ; PPC64LE-NEXT: lwsync |
| 6851 | ; PPC64LE-NEXT: blr |
| 6852 | %ret = atomicrmw and i8* %ptr, i8 %val singlethread acq_rel |
| 6853 | ret i8 %ret |
| 6854 | } |
| 6855 | |
| 6856 | define i8 @test404(i8* %ptr, i8 %val) { |
| 6857 | ; PPC64LE-LABEL: test404: |
| 6858 | ; PPC64LE: # BB#0: |
| 6859 | ; PPC64LE-NEXT: sync |
| 6860 | ; PPC64LE-NEXT: .LBB404_1: |
| 6861 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 6862 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 6863 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 6864 | ; PPC64LE-NEXT: bne 0, .LBB404_1 |
| 6865 | ; PPC64LE-NEXT: # BB#2: |
| 6866 | ; PPC64LE-NEXT: mr 3, 5 |
| 6867 | ; PPC64LE-NEXT: lwsync |
| 6868 | ; PPC64LE-NEXT: blr |
| 6869 | %ret = atomicrmw and i8* %ptr, i8 %val singlethread seq_cst |
| 6870 | ret i8 %ret |
| 6871 | } |
| 6872 | |
| 6873 | define i16 @test405(i16* %ptr, i16 %val) { |
| 6874 | ; PPC64LE-LABEL: test405: |
| 6875 | ; PPC64LE: # BB#0: |
| 6876 | ; PPC64LE-NEXT: .LBB405_1: |
| 6877 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 6878 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 6879 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 6880 | ; PPC64LE-NEXT: bne 0, .LBB405_1 |
| 6881 | ; PPC64LE-NEXT: # BB#2: |
| 6882 | ; PPC64LE-NEXT: mr 3, 5 |
| 6883 | ; PPC64LE-NEXT: blr |
| 6884 | %ret = atomicrmw and i16* %ptr, i16 %val singlethread monotonic |
| 6885 | ret i16 %ret |
| 6886 | } |
| 6887 | |
| 6888 | define i16 @test406(i16* %ptr, i16 %val) { |
| 6889 | ; PPC64LE-LABEL: test406: |
| 6890 | ; PPC64LE: # BB#0: |
| 6891 | ; PPC64LE-NEXT: mr 5, 3 |
| 6892 | ; PPC64LE-NEXT: .LBB406_1: |
| 6893 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 6894 | ; PPC64LE-NEXT: and 6, 4, 3 |
| 6895 | ; PPC64LE-NEXT: sthcx. 6, 0, 5 |
| 6896 | ; PPC64LE-NEXT: bne 0, .LBB406_1 |
| 6897 | ; PPC64LE-NEXT: # BB#2: |
| 6898 | ; PPC64LE-NEXT: lwsync |
| 6899 | ; PPC64LE-NEXT: blr |
| 6900 | %ret = atomicrmw and i16* %ptr, i16 %val singlethread acquire |
| 6901 | ret i16 %ret |
| 6902 | } |
| 6903 | |
| 6904 | define i16 @test407(i16* %ptr, i16 %val) { |
| 6905 | ; PPC64LE-LABEL: test407: |
| 6906 | ; PPC64LE: # BB#0: |
| 6907 | ; PPC64LE-NEXT: lwsync |
| 6908 | ; PPC64LE-NEXT: .LBB407_1: |
| 6909 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 6910 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 6911 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 6912 | ; PPC64LE-NEXT: bne 0, .LBB407_1 |
| 6913 | ; PPC64LE-NEXT: # BB#2: |
| 6914 | ; PPC64LE-NEXT: mr 3, 5 |
| 6915 | ; PPC64LE-NEXT: blr |
| 6916 | %ret = atomicrmw and i16* %ptr, i16 %val singlethread release |
| 6917 | ret i16 %ret |
| 6918 | } |
| 6919 | |
| 6920 | define i16 @test408(i16* %ptr, i16 %val) { |
| 6921 | ; PPC64LE-LABEL: test408: |
| 6922 | ; PPC64LE: # BB#0: |
| 6923 | ; PPC64LE-NEXT: lwsync |
| 6924 | ; PPC64LE-NEXT: .LBB408_1: |
| 6925 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 6926 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 6927 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 6928 | ; PPC64LE-NEXT: bne 0, .LBB408_1 |
| 6929 | ; PPC64LE-NEXT: # BB#2: |
| 6930 | ; PPC64LE-NEXT: mr 3, 5 |
| 6931 | ; PPC64LE-NEXT: lwsync |
| 6932 | ; PPC64LE-NEXT: blr |
| 6933 | %ret = atomicrmw and i16* %ptr, i16 %val singlethread acq_rel |
| 6934 | ret i16 %ret |
| 6935 | } |
| 6936 | |
| 6937 | define i16 @test409(i16* %ptr, i16 %val) { |
| 6938 | ; PPC64LE-LABEL: test409: |
| 6939 | ; PPC64LE: # BB#0: |
| 6940 | ; PPC64LE-NEXT: sync |
| 6941 | ; PPC64LE-NEXT: .LBB409_1: |
| 6942 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 6943 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 6944 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 6945 | ; PPC64LE-NEXT: bne 0, .LBB409_1 |
| 6946 | ; PPC64LE-NEXT: # BB#2: |
| 6947 | ; PPC64LE-NEXT: mr 3, 5 |
| 6948 | ; PPC64LE-NEXT: lwsync |
| 6949 | ; PPC64LE-NEXT: blr |
| 6950 | %ret = atomicrmw and i16* %ptr, i16 %val singlethread seq_cst |
| 6951 | ret i16 %ret |
| 6952 | } |
| 6953 | |
| 6954 | define i32 @test410(i32* %ptr, i32 %val) { |
| 6955 | ; PPC64LE-LABEL: test410: |
| 6956 | ; PPC64LE: # BB#0: |
| 6957 | ; PPC64LE-NEXT: .LBB410_1: |
| 6958 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6959 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 6960 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 6961 | ; PPC64LE-NEXT: bne 0, .LBB410_1 |
| 6962 | ; PPC64LE-NEXT: # BB#2: |
| 6963 | ; PPC64LE-NEXT: mr 3, 5 |
| 6964 | ; PPC64LE-NEXT: blr |
| 6965 | %ret = atomicrmw and i32* %ptr, i32 %val singlethread monotonic |
| 6966 | ret i32 %ret |
| 6967 | } |
| 6968 | |
| 6969 | define i32 @test411(i32* %ptr, i32 %val) { |
| 6970 | ; PPC64LE-LABEL: test411: |
| 6971 | ; PPC64LE: # BB#0: |
| 6972 | ; PPC64LE-NEXT: mr 5, 3 |
| 6973 | ; PPC64LE-NEXT: .LBB411_1: |
| 6974 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 6975 | ; PPC64LE-NEXT: and 6, 4, 3 |
| 6976 | ; PPC64LE-NEXT: stwcx. 6, 0, 5 |
| 6977 | ; PPC64LE-NEXT: bne 0, .LBB411_1 |
| 6978 | ; PPC64LE-NEXT: # BB#2: |
| 6979 | ; PPC64LE-NEXT: lwsync |
| 6980 | ; PPC64LE-NEXT: blr |
| 6981 | %ret = atomicrmw and i32* %ptr, i32 %val singlethread acquire |
| 6982 | ret i32 %ret |
| 6983 | } |
| 6984 | |
| 6985 | define i32 @test412(i32* %ptr, i32 %val) { |
| 6986 | ; PPC64LE-LABEL: test412: |
| 6987 | ; PPC64LE: # BB#0: |
| 6988 | ; PPC64LE-NEXT: lwsync |
| 6989 | ; PPC64LE-NEXT: .LBB412_1: |
| 6990 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 6991 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 6992 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 6993 | ; PPC64LE-NEXT: bne 0, .LBB412_1 |
| 6994 | ; PPC64LE-NEXT: # BB#2: |
| 6995 | ; PPC64LE-NEXT: mr 3, 5 |
| 6996 | ; PPC64LE-NEXT: blr |
| 6997 | %ret = atomicrmw and i32* %ptr, i32 %val singlethread release |
| 6998 | ret i32 %ret |
| 6999 | } |
| 7000 | |
| 7001 | define i32 @test413(i32* %ptr, i32 %val) { |
| 7002 | ; PPC64LE-LABEL: test413: |
| 7003 | ; PPC64LE: # BB#0: |
| 7004 | ; PPC64LE-NEXT: lwsync |
| 7005 | ; PPC64LE-NEXT: .LBB413_1: |
| 7006 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7007 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 7008 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7009 | ; PPC64LE-NEXT: bne 0, .LBB413_1 |
| 7010 | ; PPC64LE-NEXT: # BB#2: |
| 7011 | ; PPC64LE-NEXT: mr 3, 5 |
| 7012 | ; PPC64LE-NEXT: lwsync |
| 7013 | ; PPC64LE-NEXT: blr |
| 7014 | %ret = atomicrmw and i32* %ptr, i32 %val singlethread acq_rel |
| 7015 | ret i32 %ret |
| 7016 | } |
| 7017 | |
| 7018 | define i32 @test414(i32* %ptr, i32 %val) { |
| 7019 | ; PPC64LE-LABEL: test414: |
| 7020 | ; PPC64LE: # BB#0: |
| 7021 | ; PPC64LE-NEXT: sync |
| 7022 | ; PPC64LE-NEXT: .LBB414_1: |
| 7023 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7024 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 7025 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7026 | ; PPC64LE-NEXT: bne 0, .LBB414_1 |
| 7027 | ; PPC64LE-NEXT: # BB#2: |
| 7028 | ; PPC64LE-NEXT: mr 3, 5 |
| 7029 | ; PPC64LE-NEXT: lwsync |
| 7030 | ; PPC64LE-NEXT: blr |
| 7031 | %ret = atomicrmw and i32* %ptr, i32 %val singlethread seq_cst |
| 7032 | ret i32 %ret |
| 7033 | } |
| 7034 | |
| 7035 | define i64 @test415(i64* %ptr, i64 %val) { |
| 7036 | ; PPC64LE-LABEL: test415: |
| 7037 | ; PPC64LE: # BB#0: |
| 7038 | ; PPC64LE-NEXT: .LBB415_1: |
| 7039 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 7040 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 7041 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 7042 | ; PPC64LE-NEXT: bne 0, .LBB415_1 |
| 7043 | ; PPC64LE-NEXT: # BB#2: |
| 7044 | ; PPC64LE-NEXT: mr 3, 5 |
| 7045 | ; PPC64LE-NEXT: blr |
| 7046 | %ret = atomicrmw and i64* %ptr, i64 %val singlethread monotonic |
| 7047 | ret i64 %ret |
| 7048 | } |
| 7049 | |
| 7050 | define i64 @test416(i64* %ptr, i64 %val) { |
| 7051 | ; PPC64LE-LABEL: test416: |
| 7052 | ; PPC64LE: # BB#0: |
| 7053 | ; PPC64LE-NEXT: mr 5, 3 |
| 7054 | ; PPC64LE-NEXT: .LBB416_1: |
| 7055 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 7056 | ; PPC64LE-NEXT: and 6, 4, 3 |
| 7057 | ; PPC64LE-NEXT: stdcx. 6, 0, 5 |
| 7058 | ; PPC64LE-NEXT: bne 0, .LBB416_1 |
| 7059 | ; PPC64LE-NEXT: # BB#2: |
| 7060 | ; PPC64LE-NEXT: lwsync |
| 7061 | ; PPC64LE-NEXT: blr |
| 7062 | %ret = atomicrmw and i64* %ptr, i64 %val singlethread acquire |
| 7063 | ret i64 %ret |
| 7064 | } |
| 7065 | |
| 7066 | define i64 @test417(i64* %ptr, i64 %val) { |
| 7067 | ; PPC64LE-LABEL: test417: |
| 7068 | ; PPC64LE: # BB#0: |
| 7069 | ; PPC64LE-NEXT: lwsync |
| 7070 | ; PPC64LE-NEXT: .LBB417_1: |
| 7071 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 7072 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 7073 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 7074 | ; PPC64LE-NEXT: bne 0, .LBB417_1 |
| 7075 | ; PPC64LE-NEXT: # BB#2: |
| 7076 | ; PPC64LE-NEXT: mr 3, 5 |
| 7077 | ; PPC64LE-NEXT: blr |
| 7078 | %ret = atomicrmw and i64* %ptr, i64 %val singlethread release |
| 7079 | ret i64 %ret |
| 7080 | } |
| 7081 | |
| 7082 | define i64 @test418(i64* %ptr, i64 %val) { |
| 7083 | ; PPC64LE-LABEL: test418: |
| 7084 | ; PPC64LE: # BB#0: |
| 7085 | ; PPC64LE-NEXT: lwsync |
| 7086 | ; PPC64LE-NEXT: .LBB418_1: |
| 7087 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 7088 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 7089 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 7090 | ; PPC64LE-NEXT: bne 0, .LBB418_1 |
| 7091 | ; PPC64LE-NEXT: # BB#2: |
| 7092 | ; PPC64LE-NEXT: mr 3, 5 |
| 7093 | ; PPC64LE-NEXT: lwsync |
| 7094 | ; PPC64LE-NEXT: blr |
| 7095 | %ret = atomicrmw and i64* %ptr, i64 %val singlethread acq_rel |
| 7096 | ret i64 %ret |
| 7097 | } |
| 7098 | |
| 7099 | define i64 @test419(i64* %ptr, i64 %val) { |
| 7100 | ; PPC64LE-LABEL: test419: |
| 7101 | ; PPC64LE: # BB#0: |
| 7102 | ; PPC64LE-NEXT: sync |
| 7103 | ; PPC64LE-NEXT: .LBB419_1: |
| 7104 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 7105 | ; PPC64LE-NEXT: and 6, 4, 5 |
| 7106 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 7107 | ; PPC64LE-NEXT: bne 0, .LBB419_1 |
| 7108 | ; PPC64LE-NEXT: # BB#2: |
| 7109 | ; PPC64LE-NEXT: mr 3, 5 |
| 7110 | ; PPC64LE-NEXT: lwsync |
| 7111 | ; PPC64LE-NEXT: blr |
| 7112 | %ret = atomicrmw and i64* %ptr, i64 %val singlethread seq_cst |
| 7113 | ret i64 %ret |
| 7114 | } |
| 7115 | |
| 7116 | define i8 @test420(i8* %ptr, i8 %val) { |
| 7117 | ; PPC64LE-LABEL: test420: |
| 7118 | ; PPC64LE: # BB#0: |
| 7119 | ; PPC64LE-NEXT: .LBB420_1: |
| 7120 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 7121 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7122 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 7123 | ; PPC64LE-NEXT: bne 0, .LBB420_1 |
| 7124 | ; PPC64LE-NEXT: # BB#2: |
| 7125 | ; PPC64LE-NEXT: mr 3, 5 |
| 7126 | ; PPC64LE-NEXT: blr |
| 7127 | %ret = atomicrmw nand i8* %ptr, i8 %val singlethread monotonic |
| 7128 | ret i8 %ret |
| 7129 | } |
| 7130 | |
| 7131 | define i8 @test421(i8* %ptr, i8 %val) { |
| 7132 | ; PPC64LE-LABEL: test421: |
| 7133 | ; PPC64LE: # BB#0: |
| 7134 | ; PPC64LE-NEXT: mr 5, 3 |
| 7135 | ; PPC64LE-NEXT: .LBB421_1: |
| 7136 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 7137 | ; PPC64LE-NEXT: nand 6, 4, 3 |
| 7138 | ; PPC64LE-NEXT: stbcx. 6, 0, 5 |
| 7139 | ; PPC64LE-NEXT: bne 0, .LBB421_1 |
| 7140 | ; PPC64LE-NEXT: # BB#2: |
| 7141 | ; PPC64LE-NEXT: lwsync |
| 7142 | ; PPC64LE-NEXT: blr |
| 7143 | %ret = atomicrmw nand i8* %ptr, i8 %val singlethread acquire |
| 7144 | ret i8 %ret |
| 7145 | } |
| 7146 | |
| 7147 | define i8 @test422(i8* %ptr, i8 %val) { |
| 7148 | ; PPC64LE-LABEL: test422: |
| 7149 | ; PPC64LE: # BB#0: |
| 7150 | ; PPC64LE-NEXT: lwsync |
| 7151 | ; PPC64LE-NEXT: .LBB422_1: |
| 7152 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 7153 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7154 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 7155 | ; PPC64LE-NEXT: bne 0, .LBB422_1 |
| 7156 | ; PPC64LE-NEXT: # BB#2: |
| 7157 | ; PPC64LE-NEXT: mr 3, 5 |
| 7158 | ; PPC64LE-NEXT: blr |
| 7159 | %ret = atomicrmw nand i8* %ptr, i8 %val singlethread release |
| 7160 | ret i8 %ret |
| 7161 | } |
| 7162 | |
| 7163 | define i8 @test423(i8* %ptr, i8 %val) { |
| 7164 | ; PPC64LE-LABEL: test423: |
| 7165 | ; PPC64LE: # BB#0: |
| 7166 | ; PPC64LE-NEXT: lwsync |
| 7167 | ; PPC64LE-NEXT: .LBB423_1: |
| 7168 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 7169 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7170 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 7171 | ; PPC64LE-NEXT: bne 0, .LBB423_1 |
| 7172 | ; PPC64LE-NEXT: # BB#2: |
| 7173 | ; PPC64LE-NEXT: mr 3, 5 |
| 7174 | ; PPC64LE-NEXT: lwsync |
| 7175 | ; PPC64LE-NEXT: blr |
| 7176 | %ret = atomicrmw nand i8* %ptr, i8 %val singlethread acq_rel |
| 7177 | ret i8 %ret |
| 7178 | } |
| 7179 | |
| 7180 | define i8 @test424(i8* %ptr, i8 %val) { |
| 7181 | ; PPC64LE-LABEL: test424: |
| 7182 | ; PPC64LE: # BB#0: |
| 7183 | ; PPC64LE-NEXT: sync |
| 7184 | ; PPC64LE-NEXT: .LBB424_1: |
| 7185 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 7186 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7187 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 7188 | ; PPC64LE-NEXT: bne 0, .LBB424_1 |
| 7189 | ; PPC64LE-NEXT: # BB#2: |
| 7190 | ; PPC64LE-NEXT: mr 3, 5 |
| 7191 | ; PPC64LE-NEXT: lwsync |
| 7192 | ; PPC64LE-NEXT: blr |
| 7193 | %ret = atomicrmw nand i8* %ptr, i8 %val singlethread seq_cst |
| 7194 | ret i8 %ret |
| 7195 | } |
| 7196 | |
| 7197 | define i16 @test425(i16* %ptr, i16 %val) { |
| 7198 | ; PPC64LE-LABEL: test425: |
| 7199 | ; PPC64LE: # BB#0: |
| 7200 | ; PPC64LE-NEXT: .LBB425_1: |
| 7201 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 7202 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7203 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 7204 | ; PPC64LE-NEXT: bne 0, .LBB425_1 |
| 7205 | ; PPC64LE-NEXT: # BB#2: |
| 7206 | ; PPC64LE-NEXT: mr 3, 5 |
| 7207 | ; PPC64LE-NEXT: blr |
| 7208 | %ret = atomicrmw nand i16* %ptr, i16 %val singlethread monotonic |
| 7209 | ret i16 %ret |
| 7210 | } |
| 7211 | |
| 7212 | define i16 @test426(i16* %ptr, i16 %val) { |
| 7213 | ; PPC64LE-LABEL: test426: |
| 7214 | ; PPC64LE: # BB#0: |
| 7215 | ; PPC64LE-NEXT: mr 5, 3 |
| 7216 | ; PPC64LE-NEXT: .LBB426_1: |
| 7217 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 7218 | ; PPC64LE-NEXT: nand 6, 4, 3 |
| 7219 | ; PPC64LE-NEXT: sthcx. 6, 0, 5 |
| 7220 | ; PPC64LE-NEXT: bne 0, .LBB426_1 |
| 7221 | ; PPC64LE-NEXT: # BB#2: |
| 7222 | ; PPC64LE-NEXT: lwsync |
| 7223 | ; PPC64LE-NEXT: blr |
| 7224 | %ret = atomicrmw nand i16* %ptr, i16 %val singlethread acquire |
| 7225 | ret i16 %ret |
| 7226 | } |
| 7227 | |
| 7228 | define i16 @test427(i16* %ptr, i16 %val) { |
| 7229 | ; PPC64LE-LABEL: test427: |
| 7230 | ; PPC64LE: # BB#0: |
| 7231 | ; PPC64LE-NEXT: lwsync |
| 7232 | ; PPC64LE-NEXT: .LBB427_1: |
| 7233 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 7234 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7235 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 7236 | ; PPC64LE-NEXT: bne 0, .LBB427_1 |
| 7237 | ; PPC64LE-NEXT: # BB#2: |
| 7238 | ; PPC64LE-NEXT: mr 3, 5 |
| 7239 | ; PPC64LE-NEXT: blr |
| 7240 | %ret = atomicrmw nand i16* %ptr, i16 %val singlethread release |
| 7241 | ret i16 %ret |
| 7242 | } |
| 7243 | |
| 7244 | define i16 @test428(i16* %ptr, i16 %val) { |
| 7245 | ; PPC64LE-LABEL: test428: |
| 7246 | ; PPC64LE: # BB#0: |
| 7247 | ; PPC64LE-NEXT: lwsync |
| 7248 | ; PPC64LE-NEXT: .LBB428_1: |
| 7249 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 7250 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7251 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 7252 | ; PPC64LE-NEXT: bne 0, .LBB428_1 |
| 7253 | ; PPC64LE-NEXT: # BB#2: |
| 7254 | ; PPC64LE-NEXT: mr 3, 5 |
| 7255 | ; PPC64LE-NEXT: lwsync |
| 7256 | ; PPC64LE-NEXT: blr |
| 7257 | %ret = atomicrmw nand i16* %ptr, i16 %val singlethread acq_rel |
| 7258 | ret i16 %ret |
| 7259 | } |
| 7260 | |
| 7261 | define i16 @test429(i16* %ptr, i16 %val) { |
| 7262 | ; PPC64LE-LABEL: test429: |
| 7263 | ; PPC64LE: # BB#0: |
| 7264 | ; PPC64LE-NEXT: sync |
| 7265 | ; PPC64LE-NEXT: .LBB429_1: |
| 7266 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 7267 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7268 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 7269 | ; PPC64LE-NEXT: bne 0, .LBB429_1 |
| 7270 | ; PPC64LE-NEXT: # BB#2: |
| 7271 | ; PPC64LE-NEXT: mr 3, 5 |
| 7272 | ; PPC64LE-NEXT: lwsync |
| 7273 | ; PPC64LE-NEXT: blr |
| 7274 | %ret = atomicrmw nand i16* %ptr, i16 %val singlethread seq_cst |
| 7275 | ret i16 %ret |
| 7276 | } |
| 7277 | |
| 7278 | define i32 @test430(i32* %ptr, i32 %val) { |
| 7279 | ; PPC64LE-LABEL: test430: |
| 7280 | ; PPC64LE: # BB#0: |
| 7281 | ; PPC64LE-NEXT: .LBB430_1: |
| 7282 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7283 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7284 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7285 | ; PPC64LE-NEXT: bne 0, .LBB430_1 |
| 7286 | ; PPC64LE-NEXT: # BB#2: |
| 7287 | ; PPC64LE-NEXT: mr 3, 5 |
| 7288 | ; PPC64LE-NEXT: blr |
| 7289 | %ret = atomicrmw nand i32* %ptr, i32 %val singlethread monotonic |
| 7290 | ret i32 %ret |
| 7291 | } |
| 7292 | |
| 7293 | define i32 @test431(i32* %ptr, i32 %val) { |
| 7294 | ; PPC64LE-LABEL: test431: |
| 7295 | ; PPC64LE: # BB#0: |
| 7296 | ; PPC64LE-NEXT: mr 5, 3 |
| 7297 | ; PPC64LE-NEXT: .LBB431_1: |
| 7298 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 7299 | ; PPC64LE-NEXT: nand 6, 4, 3 |
| 7300 | ; PPC64LE-NEXT: stwcx. 6, 0, 5 |
| 7301 | ; PPC64LE-NEXT: bne 0, .LBB431_1 |
| 7302 | ; PPC64LE-NEXT: # BB#2: |
| 7303 | ; PPC64LE-NEXT: lwsync |
| 7304 | ; PPC64LE-NEXT: blr |
| 7305 | %ret = atomicrmw nand i32* %ptr, i32 %val singlethread acquire |
| 7306 | ret i32 %ret |
| 7307 | } |
| 7308 | |
| 7309 | define i32 @test432(i32* %ptr, i32 %val) { |
| 7310 | ; PPC64LE-LABEL: test432: |
| 7311 | ; PPC64LE: # BB#0: |
| 7312 | ; PPC64LE-NEXT: lwsync |
| 7313 | ; PPC64LE-NEXT: .LBB432_1: |
| 7314 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7315 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7316 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7317 | ; PPC64LE-NEXT: bne 0, .LBB432_1 |
| 7318 | ; PPC64LE-NEXT: # BB#2: |
| 7319 | ; PPC64LE-NEXT: mr 3, 5 |
| 7320 | ; PPC64LE-NEXT: blr |
| 7321 | %ret = atomicrmw nand i32* %ptr, i32 %val singlethread release |
| 7322 | ret i32 %ret |
| 7323 | } |
| 7324 | |
| 7325 | define i32 @test433(i32* %ptr, i32 %val) { |
| 7326 | ; PPC64LE-LABEL: test433: |
| 7327 | ; PPC64LE: # BB#0: |
| 7328 | ; PPC64LE-NEXT: lwsync |
| 7329 | ; PPC64LE-NEXT: .LBB433_1: |
| 7330 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7331 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7332 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7333 | ; PPC64LE-NEXT: bne 0, .LBB433_1 |
| 7334 | ; PPC64LE-NEXT: # BB#2: |
| 7335 | ; PPC64LE-NEXT: mr 3, 5 |
| 7336 | ; PPC64LE-NEXT: lwsync |
| 7337 | ; PPC64LE-NEXT: blr |
| 7338 | %ret = atomicrmw nand i32* %ptr, i32 %val singlethread acq_rel |
| 7339 | ret i32 %ret |
| 7340 | } |
| 7341 | |
| 7342 | define i32 @test434(i32* %ptr, i32 %val) { |
| 7343 | ; PPC64LE-LABEL: test434: |
| 7344 | ; PPC64LE: # BB#0: |
| 7345 | ; PPC64LE-NEXT: sync |
| 7346 | ; PPC64LE-NEXT: .LBB434_1: |
| 7347 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7348 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7349 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7350 | ; PPC64LE-NEXT: bne 0, .LBB434_1 |
| 7351 | ; PPC64LE-NEXT: # BB#2: |
| 7352 | ; PPC64LE-NEXT: mr 3, 5 |
| 7353 | ; PPC64LE-NEXT: lwsync |
| 7354 | ; PPC64LE-NEXT: blr |
| 7355 | %ret = atomicrmw nand i32* %ptr, i32 %val singlethread seq_cst |
| 7356 | ret i32 %ret |
| 7357 | } |
| 7358 | |
| 7359 | define i64 @test435(i64* %ptr, i64 %val) { |
| 7360 | ; PPC64LE-LABEL: test435: |
| 7361 | ; PPC64LE: # BB#0: |
| 7362 | ; PPC64LE-NEXT: .LBB435_1: |
| 7363 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 7364 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7365 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 7366 | ; PPC64LE-NEXT: bne 0, .LBB435_1 |
| 7367 | ; PPC64LE-NEXT: # BB#2: |
| 7368 | ; PPC64LE-NEXT: mr 3, 5 |
| 7369 | ; PPC64LE-NEXT: blr |
| 7370 | %ret = atomicrmw nand i64* %ptr, i64 %val singlethread monotonic |
| 7371 | ret i64 %ret |
| 7372 | } |
| 7373 | |
| 7374 | define i64 @test436(i64* %ptr, i64 %val) { |
| 7375 | ; PPC64LE-LABEL: test436: |
| 7376 | ; PPC64LE: # BB#0: |
| 7377 | ; PPC64LE-NEXT: mr 5, 3 |
| 7378 | ; PPC64LE-NEXT: .LBB436_1: |
| 7379 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 7380 | ; PPC64LE-NEXT: nand 6, 4, 3 |
| 7381 | ; PPC64LE-NEXT: stdcx. 6, 0, 5 |
| 7382 | ; PPC64LE-NEXT: bne 0, .LBB436_1 |
| 7383 | ; PPC64LE-NEXT: # BB#2: |
| 7384 | ; PPC64LE-NEXT: lwsync |
| 7385 | ; PPC64LE-NEXT: blr |
| 7386 | %ret = atomicrmw nand i64* %ptr, i64 %val singlethread acquire |
| 7387 | ret i64 %ret |
| 7388 | } |
| 7389 | |
| 7390 | define i64 @test437(i64* %ptr, i64 %val) { |
| 7391 | ; PPC64LE-LABEL: test437: |
| 7392 | ; PPC64LE: # BB#0: |
| 7393 | ; PPC64LE-NEXT: lwsync |
| 7394 | ; PPC64LE-NEXT: .LBB437_1: |
| 7395 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 7396 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7397 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 7398 | ; PPC64LE-NEXT: bne 0, .LBB437_1 |
| 7399 | ; PPC64LE-NEXT: # BB#2: |
| 7400 | ; PPC64LE-NEXT: mr 3, 5 |
| 7401 | ; PPC64LE-NEXT: blr |
| 7402 | %ret = atomicrmw nand i64* %ptr, i64 %val singlethread release |
| 7403 | ret i64 %ret |
| 7404 | } |
| 7405 | |
| 7406 | define i64 @test438(i64* %ptr, i64 %val) { |
| 7407 | ; PPC64LE-LABEL: test438: |
| 7408 | ; PPC64LE: # BB#0: |
| 7409 | ; PPC64LE-NEXT: lwsync |
| 7410 | ; PPC64LE-NEXT: .LBB438_1: |
| 7411 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 7412 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7413 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 7414 | ; PPC64LE-NEXT: bne 0, .LBB438_1 |
| 7415 | ; PPC64LE-NEXT: # BB#2: |
| 7416 | ; PPC64LE-NEXT: mr 3, 5 |
| 7417 | ; PPC64LE-NEXT: lwsync |
| 7418 | ; PPC64LE-NEXT: blr |
| 7419 | %ret = atomicrmw nand i64* %ptr, i64 %val singlethread acq_rel |
| 7420 | ret i64 %ret |
| 7421 | } |
| 7422 | |
| 7423 | define i64 @test439(i64* %ptr, i64 %val) { |
| 7424 | ; PPC64LE-LABEL: test439: |
| 7425 | ; PPC64LE: # BB#0: |
| 7426 | ; PPC64LE-NEXT: sync |
| 7427 | ; PPC64LE-NEXT: .LBB439_1: |
| 7428 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 7429 | ; PPC64LE-NEXT: nand 6, 4, 5 |
| 7430 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 7431 | ; PPC64LE-NEXT: bne 0, .LBB439_1 |
| 7432 | ; PPC64LE-NEXT: # BB#2: |
| 7433 | ; PPC64LE-NEXT: mr 3, 5 |
| 7434 | ; PPC64LE-NEXT: lwsync |
| 7435 | ; PPC64LE-NEXT: blr |
| 7436 | %ret = atomicrmw nand i64* %ptr, i64 %val singlethread seq_cst |
| 7437 | ret i64 %ret |
| 7438 | } |
| 7439 | |
| 7440 | define i8 @test440(i8* %ptr, i8 %val) { |
| 7441 | ; PPC64LE-LABEL: test440: |
| 7442 | ; PPC64LE: # BB#0: |
| 7443 | ; PPC64LE-NEXT: .LBB440_1: |
| 7444 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 7445 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7446 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 7447 | ; PPC64LE-NEXT: bne 0, .LBB440_1 |
| 7448 | ; PPC64LE-NEXT: # BB#2: |
| 7449 | ; PPC64LE-NEXT: mr 3, 5 |
| 7450 | ; PPC64LE-NEXT: blr |
| 7451 | %ret = atomicrmw or i8* %ptr, i8 %val singlethread monotonic |
| 7452 | ret i8 %ret |
| 7453 | } |
| 7454 | |
| 7455 | define i8 @test441(i8* %ptr, i8 %val) { |
| 7456 | ; PPC64LE-LABEL: test441: |
| 7457 | ; PPC64LE: # BB#0: |
| 7458 | ; PPC64LE-NEXT: mr 5, 3 |
| 7459 | ; PPC64LE-NEXT: .LBB441_1: |
| 7460 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 7461 | ; PPC64LE-NEXT: or 6, 4, 3 |
| 7462 | ; PPC64LE-NEXT: stbcx. 6, 0, 5 |
| 7463 | ; PPC64LE-NEXT: bne 0, .LBB441_1 |
| 7464 | ; PPC64LE-NEXT: # BB#2: |
| 7465 | ; PPC64LE-NEXT: lwsync |
| 7466 | ; PPC64LE-NEXT: blr |
| 7467 | %ret = atomicrmw or i8* %ptr, i8 %val singlethread acquire |
| 7468 | ret i8 %ret |
| 7469 | } |
| 7470 | |
| 7471 | define i8 @test442(i8* %ptr, i8 %val) { |
| 7472 | ; PPC64LE-LABEL: test442: |
| 7473 | ; PPC64LE: # BB#0: |
| 7474 | ; PPC64LE-NEXT: lwsync |
| 7475 | ; PPC64LE-NEXT: .LBB442_1: |
| 7476 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 7477 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7478 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 7479 | ; PPC64LE-NEXT: bne 0, .LBB442_1 |
| 7480 | ; PPC64LE-NEXT: # BB#2: |
| 7481 | ; PPC64LE-NEXT: mr 3, 5 |
| 7482 | ; PPC64LE-NEXT: blr |
| 7483 | %ret = atomicrmw or i8* %ptr, i8 %val singlethread release |
| 7484 | ret i8 %ret |
| 7485 | } |
| 7486 | |
| 7487 | define i8 @test443(i8* %ptr, i8 %val) { |
| 7488 | ; PPC64LE-LABEL: test443: |
| 7489 | ; PPC64LE: # BB#0: |
| 7490 | ; PPC64LE-NEXT: lwsync |
| 7491 | ; PPC64LE-NEXT: .LBB443_1: |
| 7492 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 7493 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7494 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 7495 | ; PPC64LE-NEXT: bne 0, .LBB443_1 |
| 7496 | ; PPC64LE-NEXT: # BB#2: |
| 7497 | ; PPC64LE-NEXT: mr 3, 5 |
| 7498 | ; PPC64LE-NEXT: lwsync |
| 7499 | ; PPC64LE-NEXT: blr |
| 7500 | %ret = atomicrmw or i8* %ptr, i8 %val singlethread acq_rel |
| 7501 | ret i8 %ret |
| 7502 | } |
| 7503 | |
| 7504 | define i8 @test444(i8* %ptr, i8 %val) { |
| 7505 | ; PPC64LE-LABEL: test444: |
| 7506 | ; PPC64LE: # BB#0: |
| 7507 | ; PPC64LE-NEXT: sync |
| 7508 | ; PPC64LE-NEXT: .LBB444_1: |
| 7509 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 7510 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7511 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 7512 | ; PPC64LE-NEXT: bne 0, .LBB444_1 |
| 7513 | ; PPC64LE-NEXT: # BB#2: |
| 7514 | ; PPC64LE-NEXT: mr 3, 5 |
| 7515 | ; PPC64LE-NEXT: lwsync |
| 7516 | ; PPC64LE-NEXT: blr |
| 7517 | %ret = atomicrmw or i8* %ptr, i8 %val singlethread seq_cst |
| 7518 | ret i8 %ret |
| 7519 | } |
| 7520 | |
| 7521 | define i16 @test445(i16* %ptr, i16 %val) { |
| 7522 | ; PPC64LE-LABEL: test445: |
| 7523 | ; PPC64LE: # BB#0: |
| 7524 | ; PPC64LE-NEXT: .LBB445_1: |
| 7525 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 7526 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7527 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 7528 | ; PPC64LE-NEXT: bne 0, .LBB445_1 |
| 7529 | ; PPC64LE-NEXT: # BB#2: |
| 7530 | ; PPC64LE-NEXT: mr 3, 5 |
| 7531 | ; PPC64LE-NEXT: blr |
| 7532 | %ret = atomicrmw or i16* %ptr, i16 %val singlethread monotonic |
| 7533 | ret i16 %ret |
| 7534 | } |
| 7535 | |
| 7536 | define i16 @test446(i16* %ptr, i16 %val) { |
| 7537 | ; PPC64LE-LABEL: test446: |
| 7538 | ; PPC64LE: # BB#0: |
| 7539 | ; PPC64LE-NEXT: mr 5, 3 |
| 7540 | ; PPC64LE-NEXT: .LBB446_1: |
| 7541 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 7542 | ; PPC64LE-NEXT: or 6, 4, 3 |
| 7543 | ; PPC64LE-NEXT: sthcx. 6, 0, 5 |
| 7544 | ; PPC64LE-NEXT: bne 0, .LBB446_1 |
| 7545 | ; PPC64LE-NEXT: # BB#2: |
| 7546 | ; PPC64LE-NEXT: lwsync |
| 7547 | ; PPC64LE-NEXT: blr |
| 7548 | %ret = atomicrmw or i16* %ptr, i16 %val singlethread acquire |
| 7549 | ret i16 %ret |
| 7550 | } |
| 7551 | |
| 7552 | define i16 @test447(i16* %ptr, i16 %val) { |
| 7553 | ; PPC64LE-LABEL: test447: |
| 7554 | ; PPC64LE: # BB#0: |
| 7555 | ; PPC64LE-NEXT: lwsync |
| 7556 | ; PPC64LE-NEXT: .LBB447_1: |
| 7557 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 7558 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7559 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 7560 | ; PPC64LE-NEXT: bne 0, .LBB447_1 |
| 7561 | ; PPC64LE-NEXT: # BB#2: |
| 7562 | ; PPC64LE-NEXT: mr 3, 5 |
| 7563 | ; PPC64LE-NEXT: blr |
| 7564 | %ret = atomicrmw or i16* %ptr, i16 %val singlethread release |
| 7565 | ret i16 %ret |
| 7566 | } |
| 7567 | |
| 7568 | define i16 @test448(i16* %ptr, i16 %val) { |
| 7569 | ; PPC64LE-LABEL: test448: |
| 7570 | ; PPC64LE: # BB#0: |
| 7571 | ; PPC64LE-NEXT: lwsync |
| 7572 | ; PPC64LE-NEXT: .LBB448_1: |
| 7573 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 7574 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7575 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 7576 | ; PPC64LE-NEXT: bne 0, .LBB448_1 |
| 7577 | ; PPC64LE-NEXT: # BB#2: |
| 7578 | ; PPC64LE-NEXT: mr 3, 5 |
| 7579 | ; PPC64LE-NEXT: lwsync |
| 7580 | ; PPC64LE-NEXT: blr |
| 7581 | %ret = atomicrmw or i16* %ptr, i16 %val singlethread acq_rel |
| 7582 | ret i16 %ret |
| 7583 | } |
| 7584 | |
| 7585 | define i16 @test449(i16* %ptr, i16 %val) { |
| 7586 | ; PPC64LE-LABEL: test449: |
| 7587 | ; PPC64LE: # BB#0: |
| 7588 | ; PPC64LE-NEXT: sync |
| 7589 | ; PPC64LE-NEXT: .LBB449_1: |
| 7590 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 7591 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7592 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 7593 | ; PPC64LE-NEXT: bne 0, .LBB449_1 |
| 7594 | ; PPC64LE-NEXT: # BB#2: |
| 7595 | ; PPC64LE-NEXT: mr 3, 5 |
| 7596 | ; PPC64LE-NEXT: lwsync |
| 7597 | ; PPC64LE-NEXT: blr |
| 7598 | %ret = atomicrmw or i16* %ptr, i16 %val singlethread seq_cst |
| 7599 | ret i16 %ret |
| 7600 | } |
| 7601 | |
| 7602 | define i32 @test450(i32* %ptr, i32 %val) { |
| 7603 | ; PPC64LE-LABEL: test450: |
| 7604 | ; PPC64LE: # BB#0: |
| 7605 | ; PPC64LE-NEXT: .LBB450_1: |
| 7606 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7607 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7608 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7609 | ; PPC64LE-NEXT: bne 0, .LBB450_1 |
| 7610 | ; PPC64LE-NEXT: # BB#2: |
| 7611 | ; PPC64LE-NEXT: mr 3, 5 |
| 7612 | ; PPC64LE-NEXT: blr |
| 7613 | %ret = atomicrmw or i32* %ptr, i32 %val singlethread monotonic |
| 7614 | ret i32 %ret |
| 7615 | } |
| 7616 | |
| 7617 | define i32 @test451(i32* %ptr, i32 %val) { |
| 7618 | ; PPC64LE-LABEL: test451: |
| 7619 | ; PPC64LE: # BB#0: |
| 7620 | ; PPC64LE-NEXT: mr 5, 3 |
| 7621 | ; PPC64LE-NEXT: .LBB451_1: |
| 7622 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 7623 | ; PPC64LE-NEXT: or 6, 4, 3 |
| 7624 | ; PPC64LE-NEXT: stwcx. 6, 0, 5 |
| 7625 | ; PPC64LE-NEXT: bne 0, .LBB451_1 |
| 7626 | ; PPC64LE-NEXT: # BB#2: |
| 7627 | ; PPC64LE-NEXT: lwsync |
| 7628 | ; PPC64LE-NEXT: blr |
| 7629 | %ret = atomicrmw or i32* %ptr, i32 %val singlethread acquire |
| 7630 | ret i32 %ret |
| 7631 | } |
| 7632 | |
| 7633 | define i32 @test452(i32* %ptr, i32 %val) { |
| 7634 | ; PPC64LE-LABEL: test452: |
| 7635 | ; PPC64LE: # BB#0: |
| 7636 | ; PPC64LE-NEXT: lwsync |
| 7637 | ; PPC64LE-NEXT: .LBB452_1: |
| 7638 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7639 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7640 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7641 | ; PPC64LE-NEXT: bne 0, .LBB452_1 |
| 7642 | ; PPC64LE-NEXT: # BB#2: |
| 7643 | ; PPC64LE-NEXT: mr 3, 5 |
| 7644 | ; PPC64LE-NEXT: blr |
| 7645 | %ret = atomicrmw or i32* %ptr, i32 %val singlethread release |
| 7646 | ret i32 %ret |
| 7647 | } |
| 7648 | |
| 7649 | define i32 @test453(i32* %ptr, i32 %val) { |
| 7650 | ; PPC64LE-LABEL: test453: |
| 7651 | ; PPC64LE: # BB#0: |
| 7652 | ; PPC64LE-NEXT: lwsync |
| 7653 | ; PPC64LE-NEXT: .LBB453_1: |
| 7654 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7655 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7656 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7657 | ; PPC64LE-NEXT: bne 0, .LBB453_1 |
| 7658 | ; PPC64LE-NEXT: # BB#2: |
| 7659 | ; PPC64LE-NEXT: mr 3, 5 |
| 7660 | ; PPC64LE-NEXT: lwsync |
| 7661 | ; PPC64LE-NEXT: blr |
| 7662 | %ret = atomicrmw or i32* %ptr, i32 %val singlethread acq_rel |
| 7663 | ret i32 %ret |
| 7664 | } |
| 7665 | |
| 7666 | define i32 @test454(i32* %ptr, i32 %val) { |
| 7667 | ; PPC64LE-LABEL: test454: |
| 7668 | ; PPC64LE: # BB#0: |
| 7669 | ; PPC64LE-NEXT: sync |
| 7670 | ; PPC64LE-NEXT: .LBB454_1: |
| 7671 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7672 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7673 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7674 | ; PPC64LE-NEXT: bne 0, .LBB454_1 |
| 7675 | ; PPC64LE-NEXT: # BB#2: |
| 7676 | ; PPC64LE-NEXT: mr 3, 5 |
| 7677 | ; PPC64LE-NEXT: lwsync |
| 7678 | ; PPC64LE-NEXT: blr |
| 7679 | %ret = atomicrmw or i32* %ptr, i32 %val singlethread seq_cst |
| 7680 | ret i32 %ret |
| 7681 | } |
| 7682 | |
| 7683 | define i64 @test455(i64* %ptr, i64 %val) { |
| 7684 | ; PPC64LE-LABEL: test455: |
| 7685 | ; PPC64LE: # BB#0: |
| 7686 | ; PPC64LE-NEXT: .LBB455_1: |
| 7687 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 7688 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7689 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 7690 | ; PPC64LE-NEXT: bne 0, .LBB455_1 |
| 7691 | ; PPC64LE-NEXT: # BB#2: |
| 7692 | ; PPC64LE-NEXT: mr 3, 5 |
| 7693 | ; PPC64LE-NEXT: blr |
| 7694 | %ret = atomicrmw or i64* %ptr, i64 %val singlethread monotonic |
| 7695 | ret i64 %ret |
| 7696 | } |
| 7697 | |
| 7698 | define i64 @test456(i64* %ptr, i64 %val) { |
| 7699 | ; PPC64LE-LABEL: test456: |
| 7700 | ; PPC64LE: # BB#0: |
| 7701 | ; PPC64LE-NEXT: mr 5, 3 |
| 7702 | ; PPC64LE-NEXT: .LBB456_1: |
| 7703 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 7704 | ; PPC64LE-NEXT: or 6, 4, 3 |
| 7705 | ; PPC64LE-NEXT: stdcx. 6, 0, 5 |
| 7706 | ; PPC64LE-NEXT: bne 0, .LBB456_1 |
| 7707 | ; PPC64LE-NEXT: # BB#2: |
| 7708 | ; PPC64LE-NEXT: lwsync |
| 7709 | ; PPC64LE-NEXT: blr |
| 7710 | %ret = atomicrmw or i64* %ptr, i64 %val singlethread acquire |
| 7711 | ret i64 %ret |
| 7712 | } |
| 7713 | |
| 7714 | define i64 @test457(i64* %ptr, i64 %val) { |
| 7715 | ; PPC64LE-LABEL: test457: |
| 7716 | ; PPC64LE: # BB#0: |
| 7717 | ; PPC64LE-NEXT: lwsync |
| 7718 | ; PPC64LE-NEXT: .LBB457_1: |
| 7719 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 7720 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7721 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 7722 | ; PPC64LE-NEXT: bne 0, .LBB457_1 |
| 7723 | ; PPC64LE-NEXT: # BB#2: |
| 7724 | ; PPC64LE-NEXT: mr 3, 5 |
| 7725 | ; PPC64LE-NEXT: blr |
| 7726 | %ret = atomicrmw or i64* %ptr, i64 %val singlethread release |
| 7727 | ret i64 %ret |
| 7728 | } |
| 7729 | |
| 7730 | define i64 @test458(i64* %ptr, i64 %val) { |
| 7731 | ; PPC64LE-LABEL: test458: |
| 7732 | ; PPC64LE: # BB#0: |
| 7733 | ; PPC64LE-NEXT: lwsync |
| 7734 | ; PPC64LE-NEXT: .LBB458_1: |
| 7735 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 7736 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7737 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 7738 | ; PPC64LE-NEXT: bne 0, .LBB458_1 |
| 7739 | ; PPC64LE-NEXT: # BB#2: |
| 7740 | ; PPC64LE-NEXT: mr 3, 5 |
| 7741 | ; PPC64LE-NEXT: lwsync |
| 7742 | ; PPC64LE-NEXT: blr |
| 7743 | %ret = atomicrmw or i64* %ptr, i64 %val singlethread acq_rel |
| 7744 | ret i64 %ret |
| 7745 | } |
| 7746 | |
| 7747 | define i64 @test459(i64* %ptr, i64 %val) { |
| 7748 | ; PPC64LE-LABEL: test459: |
| 7749 | ; PPC64LE: # BB#0: |
| 7750 | ; PPC64LE-NEXT: sync |
| 7751 | ; PPC64LE-NEXT: .LBB459_1: |
| 7752 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 7753 | ; PPC64LE-NEXT: or 6, 4, 5 |
| 7754 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 7755 | ; PPC64LE-NEXT: bne 0, .LBB459_1 |
| 7756 | ; PPC64LE-NEXT: # BB#2: |
| 7757 | ; PPC64LE-NEXT: mr 3, 5 |
| 7758 | ; PPC64LE-NEXT: lwsync |
| 7759 | ; PPC64LE-NEXT: blr |
| 7760 | %ret = atomicrmw or i64* %ptr, i64 %val singlethread seq_cst |
| 7761 | ret i64 %ret |
| 7762 | } |
| 7763 | |
| 7764 | define i8 @test460(i8* %ptr, i8 %val) { |
| 7765 | ; PPC64LE-LABEL: test460: |
| 7766 | ; PPC64LE: # BB#0: |
| 7767 | ; PPC64LE-NEXT: .LBB460_1: |
| 7768 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 7769 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 7770 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 7771 | ; PPC64LE-NEXT: bne 0, .LBB460_1 |
| 7772 | ; PPC64LE-NEXT: # BB#2: |
| 7773 | ; PPC64LE-NEXT: mr 3, 5 |
| 7774 | ; PPC64LE-NEXT: blr |
| 7775 | %ret = atomicrmw xor i8* %ptr, i8 %val singlethread monotonic |
| 7776 | ret i8 %ret |
| 7777 | } |
| 7778 | |
| 7779 | define i8 @test461(i8* %ptr, i8 %val) { |
| 7780 | ; PPC64LE-LABEL: test461: |
| 7781 | ; PPC64LE: # BB#0: |
| 7782 | ; PPC64LE-NEXT: mr 5, 3 |
| 7783 | ; PPC64LE-NEXT: .LBB461_1: |
| 7784 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 7785 | ; PPC64LE-NEXT: xor 6, 4, 3 |
| 7786 | ; PPC64LE-NEXT: stbcx. 6, 0, 5 |
| 7787 | ; PPC64LE-NEXT: bne 0, .LBB461_1 |
| 7788 | ; PPC64LE-NEXT: # BB#2: |
| 7789 | ; PPC64LE-NEXT: lwsync |
| 7790 | ; PPC64LE-NEXT: blr |
| 7791 | %ret = atomicrmw xor i8* %ptr, i8 %val singlethread acquire |
| 7792 | ret i8 %ret |
| 7793 | } |
| 7794 | |
| 7795 | define i8 @test462(i8* %ptr, i8 %val) { |
| 7796 | ; PPC64LE-LABEL: test462: |
| 7797 | ; PPC64LE: # BB#0: |
| 7798 | ; PPC64LE-NEXT: lwsync |
| 7799 | ; PPC64LE-NEXT: .LBB462_1: |
| 7800 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 7801 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 7802 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 7803 | ; PPC64LE-NEXT: bne 0, .LBB462_1 |
| 7804 | ; PPC64LE-NEXT: # BB#2: |
| 7805 | ; PPC64LE-NEXT: mr 3, 5 |
| 7806 | ; PPC64LE-NEXT: blr |
| 7807 | %ret = atomicrmw xor i8* %ptr, i8 %val singlethread release |
| 7808 | ret i8 %ret |
| 7809 | } |
| 7810 | |
| 7811 | define i8 @test463(i8* %ptr, i8 %val) { |
| 7812 | ; PPC64LE-LABEL: test463: |
| 7813 | ; PPC64LE: # BB#0: |
| 7814 | ; PPC64LE-NEXT: lwsync |
| 7815 | ; PPC64LE-NEXT: .LBB463_1: |
| 7816 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 7817 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 7818 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 7819 | ; PPC64LE-NEXT: bne 0, .LBB463_1 |
| 7820 | ; PPC64LE-NEXT: # BB#2: |
| 7821 | ; PPC64LE-NEXT: mr 3, 5 |
| 7822 | ; PPC64LE-NEXT: lwsync |
| 7823 | ; PPC64LE-NEXT: blr |
| 7824 | %ret = atomicrmw xor i8* %ptr, i8 %val singlethread acq_rel |
| 7825 | ret i8 %ret |
| 7826 | } |
| 7827 | |
| 7828 | define i8 @test464(i8* %ptr, i8 %val) { |
| 7829 | ; PPC64LE-LABEL: test464: |
| 7830 | ; PPC64LE: # BB#0: |
| 7831 | ; PPC64LE-NEXT: sync |
| 7832 | ; PPC64LE-NEXT: .LBB464_1: |
| 7833 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 7834 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 7835 | ; PPC64LE-NEXT: stbcx. 6, 0, 3 |
| 7836 | ; PPC64LE-NEXT: bne 0, .LBB464_1 |
| 7837 | ; PPC64LE-NEXT: # BB#2: |
| 7838 | ; PPC64LE-NEXT: mr 3, 5 |
| 7839 | ; PPC64LE-NEXT: lwsync |
| 7840 | ; PPC64LE-NEXT: blr |
| 7841 | %ret = atomicrmw xor i8* %ptr, i8 %val singlethread seq_cst |
| 7842 | ret i8 %ret |
| 7843 | } |
| 7844 | |
| 7845 | define i16 @test465(i16* %ptr, i16 %val) { |
| 7846 | ; PPC64LE-LABEL: test465: |
| 7847 | ; PPC64LE: # BB#0: |
| 7848 | ; PPC64LE-NEXT: .LBB465_1: |
| 7849 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 7850 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 7851 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 7852 | ; PPC64LE-NEXT: bne 0, .LBB465_1 |
| 7853 | ; PPC64LE-NEXT: # BB#2: |
| 7854 | ; PPC64LE-NEXT: mr 3, 5 |
| 7855 | ; PPC64LE-NEXT: blr |
| 7856 | %ret = atomicrmw xor i16* %ptr, i16 %val singlethread monotonic |
| 7857 | ret i16 %ret |
| 7858 | } |
| 7859 | |
| 7860 | define i16 @test466(i16* %ptr, i16 %val) { |
| 7861 | ; PPC64LE-LABEL: test466: |
| 7862 | ; PPC64LE: # BB#0: |
| 7863 | ; PPC64LE-NEXT: mr 5, 3 |
| 7864 | ; PPC64LE-NEXT: .LBB466_1: |
| 7865 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 7866 | ; PPC64LE-NEXT: xor 6, 4, 3 |
| 7867 | ; PPC64LE-NEXT: sthcx. 6, 0, 5 |
| 7868 | ; PPC64LE-NEXT: bne 0, .LBB466_1 |
| 7869 | ; PPC64LE-NEXT: # BB#2: |
| 7870 | ; PPC64LE-NEXT: lwsync |
| 7871 | ; PPC64LE-NEXT: blr |
| 7872 | %ret = atomicrmw xor i16* %ptr, i16 %val singlethread acquire |
| 7873 | ret i16 %ret |
| 7874 | } |
| 7875 | |
| 7876 | define i16 @test467(i16* %ptr, i16 %val) { |
| 7877 | ; PPC64LE-LABEL: test467: |
| 7878 | ; PPC64LE: # BB#0: |
| 7879 | ; PPC64LE-NEXT: lwsync |
| 7880 | ; PPC64LE-NEXT: .LBB467_1: |
| 7881 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 7882 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 7883 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 7884 | ; PPC64LE-NEXT: bne 0, .LBB467_1 |
| 7885 | ; PPC64LE-NEXT: # BB#2: |
| 7886 | ; PPC64LE-NEXT: mr 3, 5 |
| 7887 | ; PPC64LE-NEXT: blr |
| 7888 | %ret = atomicrmw xor i16* %ptr, i16 %val singlethread release |
| 7889 | ret i16 %ret |
| 7890 | } |
| 7891 | |
| 7892 | define i16 @test468(i16* %ptr, i16 %val) { |
| 7893 | ; PPC64LE-LABEL: test468: |
| 7894 | ; PPC64LE: # BB#0: |
| 7895 | ; PPC64LE-NEXT: lwsync |
| 7896 | ; PPC64LE-NEXT: .LBB468_1: |
| 7897 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 7898 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 7899 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 7900 | ; PPC64LE-NEXT: bne 0, .LBB468_1 |
| 7901 | ; PPC64LE-NEXT: # BB#2: |
| 7902 | ; PPC64LE-NEXT: mr 3, 5 |
| 7903 | ; PPC64LE-NEXT: lwsync |
| 7904 | ; PPC64LE-NEXT: blr |
| 7905 | %ret = atomicrmw xor i16* %ptr, i16 %val singlethread acq_rel |
| 7906 | ret i16 %ret |
| 7907 | } |
| 7908 | |
| 7909 | define i16 @test469(i16* %ptr, i16 %val) { |
| 7910 | ; PPC64LE-LABEL: test469: |
| 7911 | ; PPC64LE: # BB#0: |
| 7912 | ; PPC64LE-NEXT: sync |
| 7913 | ; PPC64LE-NEXT: .LBB469_1: |
| 7914 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 7915 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 7916 | ; PPC64LE-NEXT: sthcx. 6, 0, 3 |
| 7917 | ; PPC64LE-NEXT: bne 0, .LBB469_1 |
| 7918 | ; PPC64LE-NEXT: # BB#2: |
| 7919 | ; PPC64LE-NEXT: mr 3, 5 |
| 7920 | ; PPC64LE-NEXT: lwsync |
| 7921 | ; PPC64LE-NEXT: blr |
| 7922 | %ret = atomicrmw xor i16* %ptr, i16 %val singlethread seq_cst |
| 7923 | ret i16 %ret |
| 7924 | } |
| 7925 | |
| 7926 | define i32 @test470(i32* %ptr, i32 %val) { |
| 7927 | ; PPC64LE-LABEL: test470: |
| 7928 | ; PPC64LE: # BB#0: |
| 7929 | ; PPC64LE-NEXT: .LBB470_1: |
| 7930 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7931 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 7932 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7933 | ; PPC64LE-NEXT: bne 0, .LBB470_1 |
| 7934 | ; PPC64LE-NEXT: # BB#2: |
| 7935 | ; PPC64LE-NEXT: mr 3, 5 |
| 7936 | ; PPC64LE-NEXT: blr |
| 7937 | %ret = atomicrmw xor i32* %ptr, i32 %val singlethread monotonic |
| 7938 | ret i32 %ret |
| 7939 | } |
| 7940 | |
| 7941 | define i32 @test471(i32* %ptr, i32 %val) { |
| 7942 | ; PPC64LE-LABEL: test471: |
| 7943 | ; PPC64LE: # BB#0: |
| 7944 | ; PPC64LE-NEXT: mr 5, 3 |
| 7945 | ; PPC64LE-NEXT: .LBB471_1: |
| 7946 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 7947 | ; PPC64LE-NEXT: xor 6, 4, 3 |
| 7948 | ; PPC64LE-NEXT: stwcx. 6, 0, 5 |
| 7949 | ; PPC64LE-NEXT: bne 0, .LBB471_1 |
| 7950 | ; PPC64LE-NEXT: # BB#2: |
| 7951 | ; PPC64LE-NEXT: lwsync |
| 7952 | ; PPC64LE-NEXT: blr |
| 7953 | %ret = atomicrmw xor i32* %ptr, i32 %val singlethread acquire |
| 7954 | ret i32 %ret |
| 7955 | } |
| 7956 | |
| 7957 | define i32 @test472(i32* %ptr, i32 %val) { |
| 7958 | ; PPC64LE-LABEL: test472: |
| 7959 | ; PPC64LE: # BB#0: |
| 7960 | ; PPC64LE-NEXT: lwsync |
| 7961 | ; PPC64LE-NEXT: .LBB472_1: |
| 7962 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7963 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 7964 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7965 | ; PPC64LE-NEXT: bne 0, .LBB472_1 |
| 7966 | ; PPC64LE-NEXT: # BB#2: |
| 7967 | ; PPC64LE-NEXT: mr 3, 5 |
| 7968 | ; PPC64LE-NEXT: blr |
| 7969 | %ret = atomicrmw xor i32* %ptr, i32 %val singlethread release |
| 7970 | ret i32 %ret |
| 7971 | } |
| 7972 | |
| 7973 | define i32 @test473(i32* %ptr, i32 %val) { |
| 7974 | ; PPC64LE-LABEL: test473: |
| 7975 | ; PPC64LE: # BB#0: |
| 7976 | ; PPC64LE-NEXT: lwsync |
| 7977 | ; PPC64LE-NEXT: .LBB473_1: |
| 7978 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7979 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 7980 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7981 | ; PPC64LE-NEXT: bne 0, .LBB473_1 |
| 7982 | ; PPC64LE-NEXT: # BB#2: |
| 7983 | ; PPC64LE-NEXT: mr 3, 5 |
| 7984 | ; PPC64LE-NEXT: lwsync |
| 7985 | ; PPC64LE-NEXT: blr |
| 7986 | %ret = atomicrmw xor i32* %ptr, i32 %val singlethread acq_rel |
| 7987 | ret i32 %ret |
| 7988 | } |
| 7989 | |
| 7990 | define i32 @test474(i32* %ptr, i32 %val) { |
| 7991 | ; PPC64LE-LABEL: test474: |
| 7992 | ; PPC64LE: # BB#0: |
| 7993 | ; PPC64LE-NEXT: sync |
| 7994 | ; PPC64LE-NEXT: .LBB474_1: |
| 7995 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 7996 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 7997 | ; PPC64LE-NEXT: stwcx. 6, 0, 3 |
| 7998 | ; PPC64LE-NEXT: bne 0, .LBB474_1 |
| 7999 | ; PPC64LE-NEXT: # BB#2: |
| 8000 | ; PPC64LE-NEXT: mr 3, 5 |
| 8001 | ; PPC64LE-NEXT: lwsync |
| 8002 | ; PPC64LE-NEXT: blr |
| 8003 | %ret = atomicrmw xor i32* %ptr, i32 %val singlethread seq_cst |
| 8004 | ret i32 %ret |
| 8005 | } |
| 8006 | |
| 8007 | define i64 @test475(i64* %ptr, i64 %val) { |
| 8008 | ; PPC64LE-LABEL: test475: |
| 8009 | ; PPC64LE: # BB#0: |
| 8010 | ; PPC64LE-NEXT: .LBB475_1: |
| 8011 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 8012 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 8013 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 8014 | ; PPC64LE-NEXT: bne 0, .LBB475_1 |
| 8015 | ; PPC64LE-NEXT: # BB#2: |
| 8016 | ; PPC64LE-NEXT: mr 3, 5 |
| 8017 | ; PPC64LE-NEXT: blr |
| 8018 | %ret = atomicrmw xor i64* %ptr, i64 %val singlethread monotonic |
| 8019 | ret i64 %ret |
| 8020 | } |
| 8021 | |
| 8022 | define i64 @test476(i64* %ptr, i64 %val) { |
| 8023 | ; PPC64LE-LABEL: test476: |
| 8024 | ; PPC64LE: # BB#0: |
| 8025 | ; PPC64LE-NEXT: mr 5, 3 |
| 8026 | ; PPC64LE-NEXT: .LBB476_1: |
| 8027 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 8028 | ; PPC64LE-NEXT: xor 6, 4, 3 |
| 8029 | ; PPC64LE-NEXT: stdcx. 6, 0, 5 |
| 8030 | ; PPC64LE-NEXT: bne 0, .LBB476_1 |
| 8031 | ; PPC64LE-NEXT: # BB#2: |
| 8032 | ; PPC64LE-NEXT: lwsync |
| 8033 | ; PPC64LE-NEXT: blr |
| 8034 | %ret = atomicrmw xor i64* %ptr, i64 %val singlethread acquire |
| 8035 | ret i64 %ret |
| 8036 | } |
| 8037 | |
| 8038 | define i64 @test477(i64* %ptr, i64 %val) { |
| 8039 | ; PPC64LE-LABEL: test477: |
| 8040 | ; PPC64LE: # BB#0: |
| 8041 | ; PPC64LE-NEXT: lwsync |
| 8042 | ; PPC64LE-NEXT: .LBB477_1: |
| 8043 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 8044 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 8045 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 8046 | ; PPC64LE-NEXT: bne 0, .LBB477_1 |
| 8047 | ; PPC64LE-NEXT: # BB#2: |
| 8048 | ; PPC64LE-NEXT: mr 3, 5 |
| 8049 | ; PPC64LE-NEXT: blr |
| 8050 | %ret = atomicrmw xor i64* %ptr, i64 %val singlethread release |
| 8051 | ret i64 %ret |
| 8052 | } |
| 8053 | |
| 8054 | define i64 @test478(i64* %ptr, i64 %val) { |
| 8055 | ; PPC64LE-LABEL: test478: |
| 8056 | ; PPC64LE: # BB#0: |
| 8057 | ; PPC64LE-NEXT: lwsync |
| 8058 | ; PPC64LE-NEXT: .LBB478_1: |
| 8059 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 8060 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 8061 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 8062 | ; PPC64LE-NEXT: bne 0, .LBB478_1 |
| 8063 | ; PPC64LE-NEXT: # BB#2: |
| 8064 | ; PPC64LE-NEXT: mr 3, 5 |
| 8065 | ; PPC64LE-NEXT: lwsync |
| 8066 | ; PPC64LE-NEXT: blr |
| 8067 | %ret = atomicrmw xor i64* %ptr, i64 %val singlethread acq_rel |
| 8068 | ret i64 %ret |
| 8069 | } |
| 8070 | |
| 8071 | define i64 @test479(i64* %ptr, i64 %val) { |
| 8072 | ; PPC64LE-LABEL: test479: |
| 8073 | ; PPC64LE: # BB#0: |
| 8074 | ; PPC64LE-NEXT: sync |
| 8075 | ; PPC64LE-NEXT: .LBB479_1: |
| 8076 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 8077 | ; PPC64LE-NEXT: xor 6, 4, 5 |
| 8078 | ; PPC64LE-NEXT: stdcx. 6, 0, 3 |
| 8079 | ; PPC64LE-NEXT: bne 0, .LBB479_1 |
| 8080 | ; PPC64LE-NEXT: # BB#2: |
| 8081 | ; PPC64LE-NEXT: mr 3, 5 |
| 8082 | ; PPC64LE-NEXT: lwsync |
| 8083 | ; PPC64LE-NEXT: blr |
| 8084 | %ret = atomicrmw xor i64* %ptr, i64 %val singlethread seq_cst |
| 8085 | ret i64 %ret |
| 8086 | } |
| 8087 | |
| 8088 | define i8 @test480(i8* %ptr, i8 %val) { |
| 8089 | ; PPC64LE-LABEL: test480: |
| 8090 | ; PPC64LE: # BB#0: |
| 8091 | ; PPC64LE-NEXT: .LBB480_1: |
| 8092 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 8093 | ; PPC64LE-NEXT: extsb 6, 5 |
| 8094 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8095 | ; PPC64LE-NEXT: ble 0, .LBB480_3 |
| 8096 | ; PPC64LE-NEXT: # BB#2: |
| 8097 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 8098 | ; PPC64LE-NEXT: bne 0, .LBB480_1 |
| 8099 | ; PPC64LE-NEXT: .LBB480_3: |
| 8100 | ; PPC64LE-NEXT: mr 3, 5 |
| 8101 | ; PPC64LE-NEXT: blr |
| 8102 | %ret = atomicrmw max i8* %ptr, i8 %val singlethread monotonic |
| 8103 | ret i8 %ret |
| 8104 | } |
| 8105 | |
| 8106 | define i8 @test481(i8* %ptr, i8 %val) { |
| 8107 | ; PPC64LE-LABEL: test481: |
| 8108 | ; PPC64LE: # BB#0: |
| 8109 | ; PPC64LE-NEXT: mr 5, 3 |
| 8110 | ; PPC64LE-NEXT: .LBB481_1: |
| 8111 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 8112 | ; PPC64LE-NEXT: extsb 6, 3 |
| 8113 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8114 | ; PPC64LE-NEXT: ble 0, .LBB481_3 |
| 8115 | ; PPC64LE-NEXT: # BB#2: |
| 8116 | ; PPC64LE-NEXT: stbcx. 4, 0, 5 |
| 8117 | ; PPC64LE-NEXT: bne 0, .LBB481_1 |
| 8118 | ; PPC64LE-NEXT: .LBB481_3: |
| 8119 | ; PPC64LE-NEXT: lwsync |
| 8120 | ; PPC64LE-NEXT: blr |
| 8121 | %ret = atomicrmw max i8* %ptr, i8 %val singlethread acquire |
| 8122 | ret i8 %ret |
| 8123 | } |
| 8124 | |
| 8125 | define i8 @test482(i8* %ptr, i8 %val) { |
| 8126 | ; PPC64LE-LABEL: test482: |
| 8127 | ; PPC64LE: # BB#0: |
| 8128 | ; PPC64LE-NEXT: lwsync |
| 8129 | ; PPC64LE-NEXT: .LBB482_1: |
| 8130 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 8131 | ; PPC64LE-NEXT: extsb 6, 5 |
| 8132 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8133 | ; PPC64LE-NEXT: ble 0, .LBB482_3 |
| 8134 | ; PPC64LE-NEXT: # BB#2: |
| 8135 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 8136 | ; PPC64LE-NEXT: bne 0, .LBB482_1 |
| 8137 | ; PPC64LE-NEXT: .LBB482_3: |
| 8138 | ; PPC64LE-NEXT: mr 3, 5 |
| 8139 | ; PPC64LE-NEXT: blr |
| 8140 | %ret = atomicrmw max i8* %ptr, i8 %val singlethread release |
| 8141 | ret i8 %ret |
| 8142 | } |
| 8143 | |
| 8144 | define i8 @test483(i8* %ptr, i8 %val) { |
| 8145 | ; PPC64LE-LABEL: test483: |
| 8146 | ; PPC64LE: # BB#0: |
| 8147 | ; PPC64LE-NEXT: lwsync |
| 8148 | ; PPC64LE-NEXT: .LBB483_1: |
| 8149 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 8150 | ; PPC64LE-NEXT: extsb 6, 5 |
| 8151 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8152 | ; PPC64LE-NEXT: ble 0, .LBB483_3 |
| 8153 | ; PPC64LE-NEXT: # BB#2: |
| 8154 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 8155 | ; PPC64LE-NEXT: bne 0, .LBB483_1 |
| 8156 | ; PPC64LE-NEXT: .LBB483_3: |
| 8157 | ; PPC64LE-NEXT: mr 3, 5 |
| 8158 | ; PPC64LE-NEXT: lwsync |
| 8159 | ; PPC64LE-NEXT: blr |
| 8160 | %ret = atomicrmw max i8* %ptr, i8 %val singlethread acq_rel |
| 8161 | ret i8 %ret |
| 8162 | } |
| 8163 | |
| 8164 | define i8 @test484(i8* %ptr, i8 %val) { |
| 8165 | ; PPC64LE-LABEL: test484: |
| 8166 | ; PPC64LE: # BB#0: |
| 8167 | ; PPC64LE-NEXT: sync |
| 8168 | ; PPC64LE-NEXT: .LBB484_1: |
| 8169 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 8170 | ; PPC64LE-NEXT: extsb 6, 5 |
| 8171 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8172 | ; PPC64LE-NEXT: ble 0, .LBB484_3 |
| 8173 | ; PPC64LE-NEXT: # BB#2: |
| 8174 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 8175 | ; PPC64LE-NEXT: bne 0, .LBB484_1 |
| 8176 | ; PPC64LE-NEXT: .LBB484_3: |
| 8177 | ; PPC64LE-NEXT: mr 3, 5 |
| 8178 | ; PPC64LE-NEXT: lwsync |
| 8179 | ; PPC64LE-NEXT: blr |
| 8180 | %ret = atomicrmw max i8* %ptr, i8 %val singlethread seq_cst |
| 8181 | ret i8 %ret |
| 8182 | } |
| 8183 | |
| 8184 | define i16 @test485(i16* %ptr, i16 %val) { |
| 8185 | ; PPC64LE-LABEL: test485: |
| 8186 | ; PPC64LE: # BB#0: |
| 8187 | ; PPC64LE-NEXT: .LBB485_1: |
| 8188 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 8189 | ; PPC64LE-NEXT: extsh 6, 5 |
| 8190 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8191 | ; PPC64LE-NEXT: ble 0, .LBB485_3 |
| 8192 | ; PPC64LE-NEXT: # BB#2: |
| 8193 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 8194 | ; PPC64LE-NEXT: bne 0, .LBB485_1 |
| 8195 | ; PPC64LE-NEXT: .LBB485_3: |
| 8196 | ; PPC64LE-NEXT: mr 3, 5 |
| 8197 | ; PPC64LE-NEXT: blr |
| 8198 | %ret = atomicrmw max i16* %ptr, i16 %val singlethread monotonic |
| 8199 | ret i16 %ret |
| 8200 | } |
| 8201 | |
| 8202 | define i16 @test486(i16* %ptr, i16 %val) { |
| 8203 | ; PPC64LE-LABEL: test486: |
| 8204 | ; PPC64LE: # BB#0: |
| 8205 | ; PPC64LE-NEXT: mr 5, 3 |
| 8206 | ; PPC64LE-NEXT: .LBB486_1: |
| 8207 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 8208 | ; PPC64LE-NEXT: extsh 6, 3 |
| 8209 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8210 | ; PPC64LE-NEXT: ble 0, .LBB486_3 |
| 8211 | ; PPC64LE-NEXT: # BB#2: |
| 8212 | ; PPC64LE-NEXT: sthcx. 4, 0, 5 |
| 8213 | ; PPC64LE-NEXT: bne 0, .LBB486_1 |
| 8214 | ; PPC64LE-NEXT: .LBB486_3: |
| 8215 | ; PPC64LE-NEXT: lwsync |
| 8216 | ; PPC64LE-NEXT: blr |
| 8217 | %ret = atomicrmw max i16* %ptr, i16 %val singlethread acquire |
| 8218 | ret i16 %ret |
| 8219 | } |
| 8220 | |
| 8221 | define i16 @test487(i16* %ptr, i16 %val) { |
| 8222 | ; PPC64LE-LABEL: test487: |
| 8223 | ; PPC64LE: # BB#0: |
| 8224 | ; PPC64LE-NEXT: lwsync |
| 8225 | ; PPC64LE-NEXT: .LBB487_1: |
| 8226 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 8227 | ; PPC64LE-NEXT: extsh 6, 5 |
| 8228 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8229 | ; PPC64LE-NEXT: ble 0, .LBB487_3 |
| 8230 | ; PPC64LE-NEXT: # BB#2: |
| 8231 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 8232 | ; PPC64LE-NEXT: bne 0, .LBB487_1 |
| 8233 | ; PPC64LE-NEXT: .LBB487_3: |
| 8234 | ; PPC64LE-NEXT: mr 3, 5 |
| 8235 | ; PPC64LE-NEXT: blr |
| 8236 | %ret = atomicrmw max i16* %ptr, i16 %val singlethread release |
| 8237 | ret i16 %ret |
| 8238 | } |
| 8239 | |
| 8240 | define i16 @test488(i16* %ptr, i16 %val) { |
| 8241 | ; PPC64LE-LABEL: test488: |
| 8242 | ; PPC64LE: # BB#0: |
| 8243 | ; PPC64LE-NEXT: lwsync |
| 8244 | ; PPC64LE-NEXT: .LBB488_1: |
| 8245 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 8246 | ; PPC64LE-NEXT: extsh 6, 5 |
| 8247 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8248 | ; PPC64LE-NEXT: ble 0, .LBB488_3 |
| 8249 | ; PPC64LE-NEXT: # BB#2: |
| 8250 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 8251 | ; PPC64LE-NEXT: bne 0, .LBB488_1 |
| 8252 | ; PPC64LE-NEXT: .LBB488_3: |
| 8253 | ; PPC64LE-NEXT: mr 3, 5 |
| 8254 | ; PPC64LE-NEXT: lwsync |
| 8255 | ; PPC64LE-NEXT: blr |
| 8256 | %ret = atomicrmw max i16* %ptr, i16 %val singlethread acq_rel |
| 8257 | ret i16 %ret |
| 8258 | } |
| 8259 | |
| 8260 | define i16 @test489(i16* %ptr, i16 %val) { |
| 8261 | ; PPC64LE-LABEL: test489: |
| 8262 | ; PPC64LE: # BB#0: |
| 8263 | ; PPC64LE-NEXT: sync |
| 8264 | ; PPC64LE-NEXT: .LBB489_1: |
| 8265 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 8266 | ; PPC64LE-NEXT: extsh 6, 5 |
| 8267 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8268 | ; PPC64LE-NEXT: ble 0, .LBB489_3 |
| 8269 | ; PPC64LE-NEXT: # BB#2: |
| 8270 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 8271 | ; PPC64LE-NEXT: bne 0, .LBB489_1 |
| 8272 | ; PPC64LE-NEXT: .LBB489_3: |
| 8273 | ; PPC64LE-NEXT: mr 3, 5 |
| 8274 | ; PPC64LE-NEXT: lwsync |
| 8275 | ; PPC64LE-NEXT: blr |
| 8276 | %ret = atomicrmw max i16* %ptr, i16 %val singlethread seq_cst |
| 8277 | ret i16 %ret |
| 8278 | } |
| 8279 | |
| 8280 | define i32 @test490(i32* %ptr, i32 %val) { |
| 8281 | ; PPC64LE-LABEL: test490: |
| 8282 | ; PPC64LE: # BB#0: |
| 8283 | ; PPC64LE-NEXT: .LBB490_1: |
| 8284 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 8285 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 8286 | ; PPC64LE-NEXT: ble 0, .LBB490_3 |
| 8287 | ; PPC64LE-NEXT: # BB#2: |
| 8288 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 8289 | ; PPC64LE-NEXT: bne 0, .LBB490_1 |
| 8290 | ; PPC64LE-NEXT: .LBB490_3: |
| 8291 | ; PPC64LE-NEXT: mr 3, 5 |
| 8292 | ; PPC64LE-NEXT: blr |
| 8293 | %ret = atomicrmw max i32* %ptr, i32 %val singlethread monotonic |
| 8294 | ret i32 %ret |
| 8295 | } |
| 8296 | |
| 8297 | define i32 @test491(i32* %ptr, i32 %val) { |
| 8298 | ; PPC64LE-LABEL: test491: |
| 8299 | ; PPC64LE: # BB#0: |
| 8300 | ; PPC64LE-NEXT: mr 5, 3 |
| 8301 | ; PPC64LE-NEXT: .LBB491_1: |
| 8302 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 8303 | ; PPC64LE-NEXT: cmpw 4, 3 |
| 8304 | ; PPC64LE-NEXT: ble 0, .LBB491_3 |
| 8305 | ; PPC64LE-NEXT: # BB#2: |
| 8306 | ; PPC64LE-NEXT: stwcx. 4, 0, 5 |
| 8307 | ; PPC64LE-NEXT: bne 0, .LBB491_1 |
| 8308 | ; PPC64LE-NEXT: .LBB491_3: |
| 8309 | ; PPC64LE-NEXT: lwsync |
| 8310 | ; PPC64LE-NEXT: blr |
| 8311 | %ret = atomicrmw max i32* %ptr, i32 %val singlethread acquire |
| 8312 | ret i32 %ret |
| 8313 | } |
| 8314 | |
| 8315 | define i32 @test492(i32* %ptr, i32 %val) { |
| 8316 | ; PPC64LE-LABEL: test492: |
| 8317 | ; PPC64LE: # BB#0: |
| 8318 | ; PPC64LE-NEXT: lwsync |
| 8319 | ; PPC64LE-NEXT: .LBB492_1: |
| 8320 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 8321 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 8322 | ; PPC64LE-NEXT: ble 0, .LBB492_3 |
| 8323 | ; PPC64LE-NEXT: # BB#2: |
| 8324 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 8325 | ; PPC64LE-NEXT: bne 0, .LBB492_1 |
| 8326 | ; PPC64LE-NEXT: .LBB492_3: |
| 8327 | ; PPC64LE-NEXT: mr 3, 5 |
| 8328 | ; PPC64LE-NEXT: blr |
| 8329 | %ret = atomicrmw max i32* %ptr, i32 %val singlethread release |
| 8330 | ret i32 %ret |
| 8331 | } |
| 8332 | |
| 8333 | define i32 @test493(i32* %ptr, i32 %val) { |
| 8334 | ; PPC64LE-LABEL: test493: |
| 8335 | ; PPC64LE: # BB#0: |
| 8336 | ; PPC64LE-NEXT: lwsync |
| 8337 | ; PPC64LE-NEXT: .LBB493_1: |
| 8338 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 8339 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 8340 | ; PPC64LE-NEXT: ble 0, .LBB493_3 |
| 8341 | ; PPC64LE-NEXT: # BB#2: |
| 8342 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 8343 | ; PPC64LE-NEXT: bne 0, .LBB493_1 |
| 8344 | ; PPC64LE-NEXT: .LBB493_3: |
| 8345 | ; PPC64LE-NEXT: mr 3, 5 |
| 8346 | ; PPC64LE-NEXT: lwsync |
| 8347 | ; PPC64LE-NEXT: blr |
| 8348 | %ret = atomicrmw max i32* %ptr, i32 %val singlethread acq_rel |
| 8349 | ret i32 %ret |
| 8350 | } |
| 8351 | |
| 8352 | define i32 @test494(i32* %ptr, i32 %val) { |
| 8353 | ; PPC64LE-LABEL: test494: |
| 8354 | ; PPC64LE: # BB#0: |
| 8355 | ; PPC64LE-NEXT: sync |
| 8356 | ; PPC64LE-NEXT: .LBB494_1: |
| 8357 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 8358 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 8359 | ; PPC64LE-NEXT: ble 0, .LBB494_3 |
| 8360 | ; PPC64LE-NEXT: # BB#2: |
| 8361 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 8362 | ; PPC64LE-NEXT: bne 0, .LBB494_1 |
| 8363 | ; PPC64LE-NEXT: .LBB494_3: |
| 8364 | ; PPC64LE-NEXT: mr 3, 5 |
| 8365 | ; PPC64LE-NEXT: lwsync |
| 8366 | ; PPC64LE-NEXT: blr |
| 8367 | %ret = atomicrmw max i32* %ptr, i32 %val singlethread seq_cst |
| 8368 | ret i32 %ret |
| 8369 | } |
| 8370 | |
| 8371 | define i64 @test495(i64* %ptr, i64 %val) { |
| 8372 | ; PPC64LE-LABEL: test495: |
| 8373 | ; PPC64LE: # BB#0: |
| 8374 | ; PPC64LE-NEXT: .LBB495_1: |
| 8375 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 8376 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 8377 | ; PPC64LE-NEXT: ble 0, .LBB495_3 |
| 8378 | ; PPC64LE-NEXT: # BB#2: |
| 8379 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 8380 | ; PPC64LE-NEXT: bne 0, .LBB495_1 |
| 8381 | ; PPC64LE-NEXT: .LBB495_3: |
| 8382 | ; PPC64LE-NEXT: mr 3, 5 |
| 8383 | ; PPC64LE-NEXT: blr |
| 8384 | %ret = atomicrmw max i64* %ptr, i64 %val singlethread monotonic |
| 8385 | ret i64 %ret |
| 8386 | } |
| 8387 | |
| 8388 | define i64 @test496(i64* %ptr, i64 %val) { |
| 8389 | ; PPC64LE-LABEL: test496: |
| 8390 | ; PPC64LE: # BB#0: |
| 8391 | ; PPC64LE-NEXT: mr 5, 3 |
| 8392 | ; PPC64LE-NEXT: .LBB496_1: |
| 8393 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 8394 | ; PPC64LE-NEXT: cmpd 4, 3 |
| 8395 | ; PPC64LE-NEXT: ble 0, .LBB496_3 |
| 8396 | ; PPC64LE-NEXT: # BB#2: |
| 8397 | ; PPC64LE-NEXT: stdcx. 4, 0, 5 |
| 8398 | ; PPC64LE-NEXT: bne 0, .LBB496_1 |
| 8399 | ; PPC64LE-NEXT: .LBB496_3: |
| 8400 | ; PPC64LE-NEXT: lwsync |
| 8401 | ; PPC64LE-NEXT: blr |
| 8402 | %ret = atomicrmw max i64* %ptr, i64 %val singlethread acquire |
| 8403 | ret i64 %ret |
| 8404 | } |
| 8405 | |
| 8406 | define i64 @test497(i64* %ptr, i64 %val) { |
| 8407 | ; PPC64LE-LABEL: test497: |
| 8408 | ; PPC64LE: # BB#0: |
| 8409 | ; PPC64LE-NEXT: lwsync |
| 8410 | ; PPC64LE-NEXT: .LBB497_1: |
| 8411 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 8412 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 8413 | ; PPC64LE-NEXT: ble 0, .LBB497_3 |
| 8414 | ; PPC64LE-NEXT: # BB#2: |
| 8415 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 8416 | ; PPC64LE-NEXT: bne 0, .LBB497_1 |
| 8417 | ; PPC64LE-NEXT: .LBB497_3: |
| 8418 | ; PPC64LE-NEXT: mr 3, 5 |
| 8419 | ; PPC64LE-NEXT: blr |
| 8420 | %ret = atomicrmw max i64* %ptr, i64 %val singlethread release |
| 8421 | ret i64 %ret |
| 8422 | } |
| 8423 | |
| 8424 | define i64 @test498(i64* %ptr, i64 %val) { |
| 8425 | ; PPC64LE-LABEL: test498: |
| 8426 | ; PPC64LE: # BB#0: |
| 8427 | ; PPC64LE-NEXT: lwsync |
| 8428 | ; PPC64LE-NEXT: .LBB498_1: |
| 8429 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 8430 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 8431 | ; PPC64LE-NEXT: ble 0, .LBB498_3 |
| 8432 | ; PPC64LE-NEXT: # BB#2: |
| 8433 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 8434 | ; PPC64LE-NEXT: bne 0, .LBB498_1 |
| 8435 | ; PPC64LE-NEXT: .LBB498_3: |
| 8436 | ; PPC64LE-NEXT: mr 3, 5 |
| 8437 | ; PPC64LE-NEXT: lwsync |
| 8438 | ; PPC64LE-NEXT: blr |
| 8439 | %ret = atomicrmw max i64* %ptr, i64 %val singlethread acq_rel |
| 8440 | ret i64 %ret |
| 8441 | } |
| 8442 | |
| 8443 | define i64 @test499(i64* %ptr, i64 %val) { |
| 8444 | ; PPC64LE-LABEL: test499: |
| 8445 | ; PPC64LE: # BB#0: |
| 8446 | ; PPC64LE-NEXT: sync |
| 8447 | ; PPC64LE-NEXT: .LBB499_1: |
| 8448 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 8449 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 8450 | ; PPC64LE-NEXT: ble 0, .LBB499_3 |
| 8451 | ; PPC64LE-NEXT: # BB#2: |
| 8452 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 8453 | ; PPC64LE-NEXT: bne 0, .LBB499_1 |
| 8454 | ; PPC64LE-NEXT: .LBB499_3: |
| 8455 | ; PPC64LE-NEXT: mr 3, 5 |
| 8456 | ; PPC64LE-NEXT: lwsync |
| 8457 | ; PPC64LE-NEXT: blr |
| 8458 | %ret = atomicrmw max i64* %ptr, i64 %val singlethread seq_cst |
| 8459 | ret i64 %ret |
| 8460 | } |
| 8461 | |
| 8462 | define i8 @test500(i8* %ptr, i8 %val) { |
| 8463 | ; PPC64LE-LABEL: test500: |
| 8464 | ; PPC64LE: # BB#0: |
| 8465 | ; PPC64LE-NEXT: .LBB500_1: |
| 8466 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 8467 | ; PPC64LE-NEXT: extsb 6, 5 |
| 8468 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8469 | ; PPC64LE-NEXT: bge 0, .LBB500_3 |
| 8470 | ; PPC64LE-NEXT: # BB#2: |
| 8471 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 8472 | ; PPC64LE-NEXT: bne 0, .LBB500_1 |
| 8473 | ; PPC64LE-NEXT: .LBB500_3: |
| 8474 | ; PPC64LE-NEXT: mr 3, 5 |
| 8475 | ; PPC64LE-NEXT: blr |
| 8476 | %ret = atomicrmw min i8* %ptr, i8 %val singlethread monotonic |
| 8477 | ret i8 %ret |
| 8478 | } |
| 8479 | |
| 8480 | define i8 @test501(i8* %ptr, i8 %val) { |
| 8481 | ; PPC64LE-LABEL: test501: |
| 8482 | ; PPC64LE: # BB#0: |
| 8483 | ; PPC64LE-NEXT: mr 5, 3 |
| 8484 | ; PPC64LE-NEXT: .LBB501_1: |
| 8485 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 8486 | ; PPC64LE-NEXT: extsb 6, 3 |
| 8487 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8488 | ; PPC64LE-NEXT: bge 0, .LBB501_3 |
| 8489 | ; PPC64LE-NEXT: # BB#2: |
| 8490 | ; PPC64LE-NEXT: stbcx. 4, 0, 5 |
| 8491 | ; PPC64LE-NEXT: bne 0, .LBB501_1 |
| 8492 | ; PPC64LE-NEXT: .LBB501_3: |
| 8493 | ; PPC64LE-NEXT: lwsync |
| 8494 | ; PPC64LE-NEXT: blr |
| 8495 | %ret = atomicrmw min i8* %ptr, i8 %val singlethread acquire |
| 8496 | ret i8 %ret |
| 8497 | } |
| 8498 | |
| 8499 | define i8 @test502(i8* %ptr, i8 %val) { |
| 8500 | ; PPC64LE-LABEL: test502: |
| 8501 | ; PPC64LE: # BB#0: |
| 8502 | ; PPC64LE-NEXT: lwsync |
| 8503 | ; PPC64LE-NEXT: .LBB502_1: |
| 8504 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 8505 | ; PPC64LE-NEXT: extsb 6, 5 |
| 8506 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8507 | ; PPC64LE-NEXT: bge 0, .LBB502_3 |
| 8508 | ; PPC64LE-NEXT: # BB#2: |
| 8509 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 8510 | ; PPC64LE-NEXT: bne 0, .LBB502_1 |
| 8511 | ; PPC64LE-NEXT: .LBB502_3: |
| 8512 | ; PPC64LE-NEXT: mr 3, 5 |
| 8513 | ; PPC64LE-NEXT: blr |
| 8514 | %ret = atomicrmw min i8* %ptr, i8 %val singlethread release |
| 8515 | ret i8 %ret |
| 8516 | } |
| 8517 | |
| 8518 | define i8 @test503(i8* %ptr, i8 %val) { |
| 8519 | ; PPC64LE-LABEL: test503: |
| 8520 | ; PPC64LE: # BB#0: |
| 8521 | ; PPC64LE-NEXT: lwsync |
| 8522 | ; PPC64LE-NEXT: .LBB503_1: |
| 8523 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 8524 | ; PPC64LE-NEXT: extsb 6, 5 |
| 8525 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8526 | ; PPC64LE-NEXT: bge 0, .LBB503_3 |
| 8527 | ; PPC64LE-NEXT: # BB#2: |
| 8528 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 8529 | ; PPC64LE-NEXT: bne 0, .LBB503_1 |
| 8530 | ; PPC64LE-NEXT: .LBB503_3: |
| 8531 | ; PPC64LE-NEXT: mr 3, 5 |
| 8532 | ; PPC64LE-NEXT: lwsync |
| 8533 | ; PPC64LE-NEXT: blr |
| 8534 | %ret = atomicrmw min i8* %ptr, i8 %val singlethread acq_rel |
| 8535 | ret i8 %ret |
| 8536 | } |
| 8537 | |
| 8538 | define i8 @test504(i8* %ptr, i8 %val) { |
| 8539 | ; PPC64LE-LABEL: test504: |
| 8540 | ; PPC64LE: # BB#0: |
| 8541 | ; PPC64LE-NEXT: sync |
| 8542 | ; PPC64LE-NEXT: .LBB504_1: |
| 8543 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 8544 | ; PPC64LE-NEXT: extsb 6, 5 |
| 8545 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8546 | ; PPC64LE-NEXT: bge 0, .LBB504_3 |
| 8547 | ; PPC64LE-NEXT: # BB#2: |
| 8548 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 8549 | ; PPC64LE-NEXT: bne 0, .LBB504_1 |
| 8550 | ; PPC64LE-NEXT: .LBB504_3: |
| 8551 | ; PPC64LE-NEXT: mr 3, 5 |
| 8552 | ; PPC64LE-NEXT: lwsync |
| 8553 | ; PPC64LE-NEXT: blr |
| 8554 | %ret = atomicrmw min i8* %ptr, i8 %val singlethread seq_cst |
| 8555 | ret i8 %ret |
| 8556 | } |
| 8557 | |
| 8558 | define i16 @test505(i16* %ptr, i16 %val) { |
| 8559 | ; PPC64LE-LABEL: test505: |
| 8560 | ; PPC64LE: # BB#0: |
| 8561 | ; PPC64LE-NEXT: .LBB505_1: |
| 8562 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 8563 | ; PPC64LE-NEXT: extsh 6, 5 |
| 8564 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8565 | ; PPC64LE-NEXT: bge 0, .LBB505_3 |
| 8566 | ; PPC64LE-NEXT: # BB#2: |
| 8567 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 8568 | ; PPC64LE-NEXT: bne 0, .LBB505_1 |
| 8569 | ; PPC64LE-NEXT: .LBB505_3: |
| 8570 | ; PPC64LE-NEXT: mr 3, 5 |
| 8571 | ; PPC64LE-NEXT: blr |
| 8572 | %ret = atomicrmw min i16* %ptr, i16 %val singlethread monotonic |
| 8573 | ret i16 %ret |
| 8574 | } |
| 8575 | |
| 8576 | define i16 @test506(i16* %ptr, i16 %val) { |
| 8577 | ; PPC64LE-LABEL: test506: |
| 8578 | ; PPC64LE: # BB#0: |
| 8579 | ; PPC64LE-NEXT: mr 5, 3 |
| 8580 | ; PPC64LE-NEXT: .LBB506_1: |
| 8581 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 8582 | ; PPC64LE-NEXT: extsh 6, 3 |
| 8583 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8584 | ; PPC64LE-NEXT: bge 0, .LBB506_3 |
| 8585 | ; PPC64LE-NEXT: # BB#2: |
| 8586 | ; PPC64LE-NEXT: sthcx. 4, 0, 5 |
| 8587 | ; PPC64LE-NEXT: bne 0, .LBB506_1 |
| 8588 | ; PPC64LE-NEXT: .LBB506_3: |
| 8589 | ; PPC64LE-NEXT: lwsync |
| 8590 | ; PPC64LE-NEXT: blr |
| 8591 | %ret = atomicrmw min i16* %ptr, i16 %val singlethread acquire |
| 8592 | ret i16 %ret |
| 8593 | } |
| 8594 | |
| 8595 | define i16 @test507(i16* %ptr, i16 %val) { |
| 8596 | ; PPC64LE-LABEL: test507: |
| 8597 | ; PPC64LE: # BB#0: |
| 8598 | ; PPC64LE-NEXT: lwsync |
| 8599 | ; PPC64LE-NEXT: .LBB507_1: |
| 8600 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 8601 | ; PPC64LE-NEXT: extsh 6, 5 |
| 8602 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8603 | ; PPC64LE-NEXT: bge 0, .LBB507_3 |
| 8604 | ; PPC64LE-NEXT: # BB#2: |
| 8605 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 8606 | ; PPC64LE-NEXT: bne 0, .LBB507_1 |
| 8607 | ; PPC64LE-NEXT: .LBB507_3: |
| 8608 | ; PPC64LE-NEXT: mr 3, 5 |
| 8609 | ; PPC64LE-NEXT: blr |
| 8610 | %ret = atomicrmw min i16* %ptr, i16 %val singlethread release |
| 8611 | ret i16 %ret |
| 8612 | } |
| 8613 | |
| 8614 | define i16 @test508(i16* %ptr, i16 %val) { |
| 8615 | ; PPC64LE-LABEL: test508: |
| 8616 | ; PPC64LE: # BB#0: |
| 8617 | ; PPC64LE-NEXT: lwsync |
| 8618 | ; PPC64LE-NEXT: .LBB508_1: |
| 8619 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 8620 | ; PPC64LE-NEXT: extsh 6, 5 |
| 8621 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8622 | ; PPC64LE-NEXT: bge 0, .LBB508_3 |
| 8623 | ; PPC64LE-NEXT: # BB#2: |
| 8624 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 8625 | ; PPC64LE-NEXT: bne 0, .LBB508_1 |
| 8626 | ; PPC64LE-NEXT: .LBB508_3: |
| 8627 | ; PPC64LE-NEXT: mr 3, 5 |
| 8628 | ; PPC64LE-NEXT: lwsync |
| 8629 | ; PPC64LE-NEXT: blr |
| 8630 | %ret = atomicrmw min i16* %ptr, i16 %val singlethread acq_rel |
| 8631 | ret i16 %ret |
| 8632 | } |
| 8633 | |
| 8634 | define i16 @test509(i16* %ptr, i16 %val) { |
| 8635 | ; PPC64LE-LABEL: test509: |
| 8636 | ; PPC64LE: # BB#0: |
| 8637 | ; PPC64LE-NEXT: sync |
| 8638 | ; PPC64LE-NEXT: .LBB509_1: |
| 8639 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 8640 | ; PPC64LE-NEXT: extsh 6, 5 |
| 8641 | ; PPC64LE-NEXT: cmpw 4, 6 |
| 8642 | ; PPC64LE-NEXT: bge 0, .LBB509_3 |
| 8643 | ; PPC64LE-NEXT: # BB#2: |
| 8644 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 8645 | ; PPC64LE-NEXT: bne 0, .LBB509_1 |
| 8646 | ; PPC64LE-NEXT: .LBB509_3: |
| 8647 | ; PPC64LE-NEXT: mr 3, 5 |
| 8648 | ; PPC64LE-NEXT: lwsync |
| 8649 | ; PPC64LE-NEXT: blr |
| 8650 | %ret = atomicrmw min i16* %ptr, i16 %val singlethread seq_cst |
| 8651 | ret i16 %ret |
| 8652 | } |
| 8653 | |
| 8654 | define i32 @test510(i32* %ptr, i32 %val) { |
| 8655 | ; PPC64LE-LABEL: test510: |
| 8656 | ; PPC64LE: # BB#0: |
| 8657 | ; PPC64LE-NEXT: .LBB510_1: |
| 8658 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 8659 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 8660 | ; PPC64LE-NEXT: bge 0, .LBB510_3 |
| 8661 | ; PPC64LE-NEXT: # BB#2: |
| 8662 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 8663 | ; PPC64LE-NEXT: bne 0, .LBB510_1 |
| 8664 | ; PPC64LE-NEXT: .LBB510_3: |
| 8665 | ; PPC64LE-NEXT: mr 3, 5 |
| 8666 | ; PPC64LE-NEXT: blr |
| 8667 | %ret = atomicrmw min i32* %ptr, i32 %val singlethread monotonic |
| 8668 | ret i32 %ret |
| 8669 | } |
| 8670 | |
| 8671 | define i32 @test511(i32* %ptr, i32 %val) { |
| 8672 | ; PPC64LE-LABEL: test511: |
| 8673 | ; PPC64LE: # BB#0: |
| 8674 | ; PPC64LE-NEXT: mr 5, 3 |
| 8675 | ; PPC64LE-NEXT: .LBB511_1: |
| 8676 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 8677 | ; PPC64LE-NEXT: cmpw 4, 3 |
| 8678 | ; PPC64LE-NEXT: bge 0, .LBB511_3 |
| 8679 | ; PPC64LE-NEXT: # BB#2: |
| 8680 | ; PPC64LE-NEXT: stwcx. 4, 0, 5 |
| 8681 | ; PPC64LE-NEXT: bne 0, .LBB511_1 |
| 8682 | ; PPC64LE-NEXT: .LBB511_3: |
| 8683 | ; PPC64LE-NEXT: lwsync |
| 8684 | ; PPC64LE-NEXT: blr |
| 8685 | %ret = atomicrmw min i32* %ptr, i32 %val singlethread acquire |
| 8686 | ret i32 %ret |
| 8687 | } |
| 8688 | |
| 8689 | define i32 @test512(i32* %ptr, i32 %val) { |
| 8690 | ; PPC64LE-LABEL: test512: |
| 8691 | ; PPC64LE: # BB#0: |
| 8692 | ; PPC64LE-NEXT: lwsync |
| 8693 | ; PPC64LE-NEXT: .LBB512_1: |
| 8694 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 8695 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 8696 | ; PPC64LE-NEXT: bge 0, .LBB512_3 |
| 8697 | ; PPC64LE-NEXT: # BB#2: |
| 8698 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 8699 | ; PPC64LE-NEXT: bne 0, .LBB512_1 |
| 8700 | ; PPC64LE-NEXT: .LBB512_3: |
| 8701 | ; PPC64LE-NEXT: mr 3, 5 |
| 8702 | ; PPC64LE-NEXT: blr |
| 8703 | %ret = atomicrmw min i32* %ptr, i32 %val singlethread release |
| 8704 | ret i32 %ret |
| 8705 | } |
| 8706 | |
| 8707 | define i32 @test513(i32* %ptr, i32 %val) { |
| 8708 | ; PPC64LE-LABEL: test513: |
| 8709 | ; PPC64LE: # BB#0: |
| 8710 | ; PPC64LE-NEXT: lwsync |
| 8711 | ; PPC64LE-NEXT: .LBB513_1: |
| 8712 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 8713 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 8714 | ; PPC64LE-NEXT: bge 0, .LBB513_3 |
| 8715 | ; PPC64LE-NEXT: # BB#2: |
| 8716 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 8717 | ; PPC64LE-NEXT: bne 0, .LBB513_1 |
| 8718 | ; PPC64LE-NEXT: .LBB513_3: |
| 8719 | ; PPC64LE-NEXT: mr 3, 5 |
| 8720 | ; PPC64LE-NEXT: lwsync |
| 8721 | ; PPC64LE-NEXT: blr |
| 8722 | %ret = atomicrmw min i32* %ptr, i32 %val singlethread acq_rel |
| 8723 | ret i32 %ret |
| 8724 | } |
| 8725 | |
| 8726 | define i32 @test514(i32* %ptr, i32 %val) { |
| 8727 | ; PPC64LE-LABEL: test514: |
| 8728 | ; PPC64LE: # BB#0: |
| 8729 | ; PPC64LE-NEXT: sync |
| 8730 | ; PPC64LE-NEXT: .LBB514_1: |
| 8731 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 8732 | ; PPC64LE-NEXT: cmpw 4, 5 |
| 8733 | ; PPC64LE-NEXT: bge 0, .LBB514_3 |
| 8734 | ; PPC64LE-NEXT: # BB#2: |
| 8735 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 8736 | ; PPC64LE-NEXT: bne 0, .LBB514_1 |
| 8737 | ; PPC64LE-NEXT: .LBB514_3: |
| 8738 | ; PPC64LE-NEXT: mr 3, 5 |
| 8739 | ; PPC64LE-NEXT: lwsync |
| 8740 | ; PPC64LE-NEXT: blr |
| 8741 | %ret = atomicrmw min i32* %ptr, i32 %val singlethread seq_cst |
| 8742 | ret i32 %ret |
| 8743 | } |
| 8744 | |
| 8745 | define i64 @test515(i64* %ptr, i64 %val) { |
| 8746 | ; PPC64LE-LABEL: test515: |
| 8747 | ; PPC64LE: # BB#0: |
| 8748 | ; PPC64LE-NEXT: .LBB515_1: |
| 8749 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 8750 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 8751 | ; PPC64LE-NEXT: bge 0, .LBB515_3 |
| 8752 | ; PPC64LE-NEXT: # BB#2: |
| 8753 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 8754 | ; PPC64LE-NEXT: bne 0, .LBB515_1 |
| 8755 | ; PPC64LE-NEXT: .LBB515_3: |
| 8756 | ; PPC64LE-NEXT: mr 3, 5 |
| 8757 | ; PPC64LE-NEXT: blr |
| 8758 | %ret = atomicrmw min i64* %ptr, i64 %val singlethread monotonic |
| 8759 | ret i64 %ret |
| 8760 | } |
| 8761 | |
| 8762 | define i64 @test516(i64* %ptr, i64 %val) { |
| 8763 | ; PPC64LE-LABEL: test516: |
| 8764 | ; PPC64LE: # BB#0: |
| 8765 | ; PPC64LE-NEXT: mr 5, 3 |
| 8766 | ; PPC64LE-NEXT: .LBB516_1: |
| 8767 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 8768 | ; PPC64LE-NEXT: cmpd 4, 3 |
| 8769 | ; PPC64LE-NEXT: bge 0, .LBB516_3 |
| 8770 | ; PPC64LE-NEXT: # BB#2: |
| 8771 | ; PPC64LE-NEXT: stdcx. 4, 0, 5 |
| 8772 | ; PPC64LE-NEXT: bne 0, .LBB516_1 |
| 8773 | ; PPC64LE-NEXT: .LBB516_3: |
| 8774 | ; PPC64LE-NEXT: lwsync |
| 8775 | ; PPC64LE-NEXT: blr |
| 8776 | %ret = atomicrmw min i64* %ptr, i64 %val singlethread acquire |
| 8777 | ret i64 %ret |
| 8778 | } |
| 8779 | |
| 8780 | define i64 @test517(i64* %ptr, i64 %val) { |
| 8781 | ; PPC64LE-LABEL: test517: |
| 8782 | ; PPC64LE: # BB#0: |
| 8783 | ; PPC64LE-NEXT: lwsync |
| 8784 | ; PPC64LE-NEXT: .LBB517_1: |
| 8785 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 8786 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 8787 | ; PPC64LE-NEXT: bge 0, .LBB517_3 |
| 8788 | ; PPC64LE-NEXT: # BB#2: |
| 8789 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 8790 | ; PPC64LE-NEXT: bne 0, .LBB517_1 |
| 8791 | ; PPC64LE-NEXT: .LBB517_3: |
| 8792 | ; PPC64LE-NEXT: mr 3, 5 |
| 8793 | ; PPC64LE-NEXT: blr |
| 8794 | %ret = atomicrmw min i64* %ptr, i64 %val singlethread release |
| 8795 | ret i64 %ret |
| 8796 | } |
| 8797 | |
| 8798 | define i64 @test518(i64* %ptr, i64 %val) { |
| 8799 | ; PPC64LE-LABEL: test518: |
| 8800 | ; PPC64LE: # BB#0: |
| 8801 | ; PPC64LE-NEXT: lwsync |
| 8802 | ; PPC64LE-NEXT: .LBB518_1: |
| 8803 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 8804 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 8805 | ; PPC64LE-NEXT: bge 0, .LBB518_3 |
| 8806 | ; PPC64LE-NEXT: # BB#2: |
| 8807 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 8808 | ; PPC64LE-NEXT: bne 0, .LBB518_1 |
| 8809 | ; PPC64LE-NEXT: .LBB518_3: |
| 8810 | ; PPC64LE-NEXT: mr 3, 5 |
| 8811 | ; PPC64LE-NEXT: lwsync |
| 8812 | ; PPC64LE-NEXT: blr |
| 8813 | %ret = atomicrmw min i64* %ptr, i64 %val singlethread acq_rel |
| 8814 | ret i64 %ret |
| 8815 | } |
| 8816 | |
| 8817 | define i64 @test519(i64* %ptr, i64 %val) { |
| 8818 | ; PPC64LE-LABEL: test519: |
| 8819 | ; PPC64LE: # BB#0: |
| 8820 | ; PPC64LE-NEXT: sync |
| 8821 | ; PPC64LE-NEXT: .LBB519_1: |
| 8822 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 8823 | ; PPC64LE-NEXT: cmpd 4, 5 |
| 8824 | ; PPC64LE-NEXT: bge 0, .LBB519_3 |
| 8825 | ; PPC64LE-NEXT: # BB#2: |
| 8826 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 8827 | ; PPC64LE-NEXT: bne 0, .LBB519_1 |
| 8828 | ; PPC64LE-NEXT: .LBB519_3: |
| 8829 | ; PPC64LE-NEXT: mr 3, 5 |
| 8830 | ; PPC64LE-NEXT: lwsync |
| 8831 | ; PPC64LE-NEXT: blr |
| 8832 | %ret = atomicrmw min i64* %ptr, i64 %val singlethread seq_cst |
| 8833 | ret i64 %ret |
| 8834 | } |
| 8835 | |
| 8836 | define i8 @test520(i8* %ptr, i8 %val) { |
| 8837 | ; PPC64LE-LABEL: test520: |
| 8838 | ; PPC64LE: # BB#0: |
| 8839 | ; PPC64LE-NEXT: .LBB520_1: |
| 8840 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 8841 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 8842 | ; PPC64LE-NEXT: ble 0, .LBB520_3 |
| 8843 | ; PPC64LE-NEXT: # BB#2: |
| 8844 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 8845 | ; PPC64LE-NEXT: bne 0, .LBB520_1 |
| 8846 | ; PPC64LE-NEXT: .LBB520_3: |
| 8847 | ; PPC64LE-NEXT: mr 3, 5 |
| 8848 | ; PPC64LE-NEXT: blr |
| 8849 | %ret = atomicrmw umax i8* %ptr, i8 %val singlethread monotonic |
| 8850 | ret i8 %ret |
| 8851 | } |
| 8852 | |
| 8853 | define i8 @test521(i8* %ptr, i8 %val) { |
| 8854 | ; PPC64LE-LABEL: test521: |
| 8855 | ; PPC64LE: # BB#0: |
| 8856 | ; PPC64LE-NEXT: mr 5, 3 |
| 8857 | ; PPC64LE-NEXT: .LBB521_1: |
| 8858 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 8859 | ; PPC64LE-NEXT: cmplw 4, 3 |
| 8860 | ; PPC64LE-NEXT: ble 0, .LBB521_3 |
| 8861 | ; PPC64LE-NEXT: # BB#2: |
| 8862 | ; PPC64LE-NEXT: stbcx. 4, 0, 5 |
| 8863 | ; PPC64LE-NEXT: bne 0, .LBB521_1 |
| 8864 | ; PPC64LE-NEXT: .LBB521_3: |
| 8865 | ; PPC64LE-NEXT: lwsync |
| 8866 | ; PPC64LE-NEXT: blr |
| 8867 | %ret = atomicrmw umax i8* %ptr, i8 %val singlethread acquire |
| 8868 | ret i8 %ret |
| 8869 | } |
| 8870 | |
| 8871 | define i8 @test522(i8* %ptr, i8 %val) { |
| 8872 | ; PPC64LE-LABEL: test522: |
| 8873 | ; PPC64LE: # BB#0: |
| 8874 | ; PPC64LE-NEXT: lwsync |
| 8875 | ; PPC64LE-NEXT: .LBB522_1: |
| 8876 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 8877 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 8878 | ; PPC64LE-NEXT: ble 0, .LBB522_3 |
| 8879 | ; PPC64LE-NEXT: # BB#2: |
| 8880 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 8881 | ; PPC64LE-NEXT: bne 0, .LBB522_1 |
| 8882 | ; PPC64LE-NEXT: .LBB522_3: |
| 8883 | ; PPC64LE-NEXT: mr 3, 5 |
| 8884 | ; PPC64LE-NEXT: blr |
| 8885 | %ret = atomicrmw umax i8* %ptr, i8 %val singlethread release |
| 8886 | ret i8 %ret |
| 8887 | } |
| 8888 | |
| 8889 | define i8 @test523(i8* %ptr, i8 %val) { |
| 8890 | ; PPC64LE-LABEL: test523: |
| 8891 | ; PPC64LE: # BB#0: |
| 8892 | ; PPC64LE-NEXT: lwsync |
| 8893 | ; PPC64LE-NEXT: .LBB523_1: |
| 8894 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 8895 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 8896 | ; PPC64LE-NEXT: ble 0, .LBB523_3 |
| 8897 | ; PPC64LE-NEXT: # BB#2: |
| 8898 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 8899 | ; PPC64LE-NEXT: bne 0, .LBB523_1 |
| 8900 | ; PPC64LE-NEXT: .LBB523_3: |
| 8901 | ; PPC64LE-NEXT: mr 3, 5 |
| 8902 | ; PPC64LE-NEXT: lwsync |
| 8903 | ; PPC64LE-NEXT: blr |
| 8904 | %ret = atomicrmw umax i8* %ptr, i8 %val singlethread acq_rel |
| 8905 | ret i8 %ret |
| 8906 | } |
| 8907 | |
| 8908 | define i8 @test524(i8* %ptr, i8 %val) { |
| 8909 | ; PPC64LE-LABEL: test524: |
| 8910 | ; PPC64LE: # BB#0: |
| 8911 | ; PPC64LE-NEXT: sync |
| 8912 | ; PPC64LE-NEXT: .LBB524_1: |
| 8913 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 8914 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 8915 | ; PPC64LE-NEXT: ble 0, .LBB524_3 |
| 8916 | ; PPC64LE-NEXT: # BB#2: |
| 8917 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 8918 | ; PPC64LE-NEXT: bne 0, .LBB524_1 |
| 8919 | ; PPC64LE-NEXT: .LBB524_3: |
| 8920 | ; PPC64LE-NEXT: mr 3, 5 |
| 8921 | ; PPC64LE-NEXT: lwsync |
| 8922 | ; PPC64LE-NEXT: blr |
| 8923 | %ret = atomicrmw umax i8* %ptr, i8 %val singlethread seq_cst |
| 8924 | ret i8 %ret |
| 8925 | } |
| 8926 | |
| 8927 | define i16 @test525(i16* %ptr, i16 %val) { |
| 8928 | ; PPC64LE-LABEL: test525: |
| 8929 | ; PPC64LE: # BB#0: |
| 8930 | ; PPC64LE-NEXT: .LBB525_1: |
| 8931 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 8932 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 8933 | ; PPC64LE-NEXT: ble 0, .LBB525_3 |
| 8934 | ; PPC64LE-NEXT: # BB#2: |
| 8935 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 8936 | ; PPC64LE-NEXT: bne 0, .LBB525_1 |
| 8937 | ; PPC64LE-NEXT: .LBB525_3: |
| 8938 | ; PPC64LE-NEXT: mr 3, 5 |
| 8939 | ; PPC64LE-NEXT: blr |
| 8940 | %ret = atomicrmw umax i16* %ptr, i16 %val singlethread monotonic |
| 8941 | ret i16 %ret |
| 8942 | } |
| 8943 | |
| 8944 | define i16 @test526(i16* %ptr, i16 %val) { |
| 8945 | ; PPC64LE-LABEL: test526: |
| 8946 | ; PPC64LE: # BB#0: |
| 8947 | ; PPC64LE-NEXT: mr 5, 3 |
| 8948 | ; PPC64LE-NEXT: .LBB526_1: |
| 8949 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 8950 | ; PPC64LE-NEXT: cmplw 4, 3 |
| 8951 | ; PPC64LE-NEXT: ble 0, .LBB526_3 |
| 8952 | ; PPC64LE-NEXT: # BB#2: |
| 8953 | ; PPC64LE-NEXT: sthcx. 4, 0, 5 |
| 8954 | ; PPC64LE-NEXT: bne 0, .LBB526_1 |
| 8955 | ; PPC64LE-NEXT: .LBB526_3: |
| 8956 | ; PPC64LE-NEXT: lwsync |
| 8957 | ; PPC64LE-NEXT: blr |
| 8958 | %ret = atomicrmw umax i16* %ptr, i16 %val singlethread acquire |
| 8959 | ret i16 %ret |
| 8960 | } |
| 8961 | |
| 8962 | define i16 @test527(i16* %ptr, i16 %val) { |
| 8963 | ; PPC64LE-LABEL: test527: |
| 8964 | ; PPC64LE: # BB#0: |
| 8965 | ; PPC64LE-NEXT: lwsync |
| 8966 | ; PPC64LE-NEXT: .LBB527_1: |
| 8967 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 8968 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 8969 | ; PPC64LE-NEXT: ble 0, .LBB527_3 |
| 8970 | ; PPC64LE-NEXT: # BB#2: |
| 8971 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 8972 | ; PPC64LE-NEXT: bne 0, .LBB527_1 |
| 8973 | ; PPC64LE-NEXT: .LBB527_3: |
| 8974 | ; PPC64LE-NEXT: mr 3, 5 |
| 8975 | ; PPC64LE-NEXT: blr |
| 8976 | %ret = atomicrmw umax i16* %ptr, i16 %val singlethread release |
| 8977 | ret i16 %ret |
| 8978 | } |
| 8979 | |
| 8980 | define i16 @test528(i16* %ptr, i16 %val) { |
| 8981 | ; PPC64LE-LABEL: test528: |
| 8982 | ; PPC64LE: # BB#0: |
| 8983 | ; PPC64LE-NEXT: lwsync |
| 8984 | ; PPC64LE-NEXT: .LBB528_1: |
| 8985 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 8986 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 8987 | ; PPC64LE-NEXT: ble 0, .LBB528_3 |
| 8988 | ; PPC64LE-NEXT: # BB#2: |
| 8989 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 8990 | ; PPC64LE-NEXT: bne 0, .LBB528_1 |
| 8991 | ; PPC64LE-NEXT: .LBB528_3: |
| 8992 | ; PPC64LE-NEXT: mr 3, 5 |
| 8993 | ; PPC64LE-NEXT: lwsync |
| 8994 | ; PPC64LE-NEXT: blr |
| 8995 | %ret = atomicrmw umax i16* %ptr, i16 %val singlethread acq_rel |
| 8996 | ret i16 %ret |
| 8997 | } |
| 8998 | |
| 8999 | define i16 @test529(i16* %ptr, i16 %val) { |
| 9000 | ; PPC64LE-LABEL: test529: |
| 9001 | ; PPC64LE: # BB#0: |
| 9002 | ; PPC64LE-NEXT: sync |
| 9003 | ; PPC64LE-NEXT: .LBB529_1: |
| 9004 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 9005 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9006 | ; PPC64LE-NEXT: ble 0, .LBB529_3 |
| 9007 | ; PPC64LE-NEXT: # BB#2: |
| 9008 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 9009 | ; PPC64LE-NEXT: bne 0, .LBB529_1 |
| 9010 | ; PPC64LE-NEXT: .LBB529_3: |
| 9011 | ; PPC64LE-NEXT: mr 3, 5 |
| 9012 | ; PPC64LE-NEXT: lwsync |
| 9013 | ; PPC64LE-NEXT: blr |
| 9014 | %ret = atomicrmw umax i16* %ptr, i16 %val singlethread seq_cst |
| 9015 | ret i16 %ret |
| 9016 | } |
| 9017 | |
| 9018 | define i32 @test530(i32* %ptr, i32 %val) { |
| 9019 | ; PPC64LE-LABEL: test530: |
| 9020 | ; PPC64LE: # BB#0: |
| 9021 | ; PPC64LE-NEXT: .LBB530_1: |
| 9022 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 9023 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9024 | ; PPC64LE-NEXT: ble 0, .LBB530_3 |
| 9025 | ; PPC64LE-NEXT: # BB#2: |
| 9026 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 9027 | ; PPC64LE-NEXT: bne 0, .LBB530_1 |
| 9028 | ; PPC64LE-NEXT: .LBB530_3: |
| 9029 | ; PPC64LE-NEXT: mr 3, 5 |
| 9030 | ; PPC64LE-NEXT: blr |
| 9031 | %ret = atomicrmw umax i32* %ptr, i32 %val singlethread monotonic |
| 9032 | ret i32 %ret |
| 9033 | } |
| 9034 | |
| 9035 | define i32 @test531(i32* %ptr, i32 %val) { |
| 9036 | ; PPC64LE-LABEL: test531: |
| 9037 | ; PPC64LE: # BB#0: |
| 9038 | ; PPC64LE-NEXT: mr 5, 3 |
| 9039 | ; PPC64LE-NEXT: .LBB531_1: |
| 9040 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 9041 | ; PPC64LE-NEXT: cmplw 4, 3 |
| 9042 | ; PPC64LE-NEXT: ble 0, .LBB531_3 |
| 9043 | ; PPC64LE-NEXT: # BB#2: |
| 9044 | ; PPC64LE-NEXT: stwcx. 4, 0, 5 |
| 9045 | ; PPC64LE-NEXT: bne 0, .LBB531_1 |
| 9046 | ; PPC64LE-NEXT: .LBB531_3: |
| 9047 | ; PPC64LE-NEXT: lwsync |
| 9048 | ; PPC64LE-NEXT: blr |
| 9049 | %ret = atomicrmw umax i32* %ptr, i32 %val singlethread acquire |
| 9050 | ret i32 %ret |
| 9051 | } |
| 9052 | |
| 9053 | define i32 @test532(i32* %ptr, i32 %val) { |
| 9054 | ; PPC64LE-LABEL: test532: |
| 9055 | ; PPC64LE: # BB#0: |
| 9056 | ; PPC64LE-NEXT: lwsync |
| 9057 | ; PPC64LE-NEXT: .LBB532_1: |
| 9058 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 9059 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9060 | ; PPC64LE-NEXT: ble 0, .LBB532_3 |
| 9061 | ; PPC64LE-NEXT: # BB#2: |
| 9062 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 9063 | ; PPC64LE-NEXT: bne 0, .LBB532_1 |
| 9064 | ; PPC64LE-NEXT: .LBB532_3: |
| 9065 | ; PPC64LE-NEXT: mr 3, 5 |
| 9066 | ; PPC64LE-NEXT: blr |
| 9067 | %ret = atomicrmw umax i32* %ptr, i32 %val singlethread release |
| 9068 | ret i32 %ret |
| 9069 | } |
| 9070 | |
| 9071 | define i32 @test533(i32* %ptr, i32 %val) { |
| 9072 | ; PPC64LE-LABEL: test533: |
| 9073 | ; PPC64LE: # BB#0: |
| 9074 | ; PPC64LE-NEXT: lwsync |
| 9075 | ; PPC64LE-NEXT: .LBB533_1: |
| 9076 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 9077 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9078 | ; PPC64LE-NEXT: ble 0, .LBB533_3 |
| 9079 | ; PPC64LE-NEXT: # BB#2: |
| 9080 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 9081 | ; PPC64LE-NEXT: bne 0, .LBB533_1 |
| 9082 | ; PPC64LE-NEXT: .LBB533_3: |
| 9083 | ; PPC64LE-NEXT: mr 3, 5 |
| 9084 | ; PPC64LE-NEXT: lwsync |
| 9085 | ; PPC64LE-NEXT: blr |
| 9086 | %ret = atomicrmw umax i32* %ptr, i32 %val singlethread acq_rel |
| 9087 | ret i32 %ret |
| 9088 | } |
| 9089 | |
| 9090 | define i32 @test534(i32* %ptr, i32 %val) { |
| 9091 | ; PPC64LE-LABEL: test534: |
| 9092 | ; PPC64LE: # BB#0: |
| 9093 | ; PPC64LE-NEXT: sync |
| 9094 | ; PPC64LE-NEXT: .LBB534_1: |
| 9095 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 9096 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9097 | ; PPC64LE-NEXT: ble 0, .LBB534_3 |
| 9098 | ; PPC64LE-NEXT: # BB#2: |
| 9099 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 9100 | ; PPC64LE-NEXT: bne 0, .LBB534_1 |
| 9101 | ; PPC64LE-NEXT: .LBB534_3: |
| 9102 | ; PPC64LE-NEXT: mr 3, 5 |
| 9103 | ; PPC64LE-NEXT: lwsync |
| 9104 | ; PPC64LE-NEXT: blr |
| 9105 | %ret = atomicrmw umax i32* %ptr, i32 %val singlethread seq_cst |
| 9106 | ret i32 %ret |
| 9107 | } |
| 9108 | |
| 9109 | define i64 @test535(i64* %ptr, i64 %val) { |
| 9110 | ; PPC64LE-LABEL: test535: |
| 9111 | ; PPC64LE: # BB#0: |
| 9112 | ; PPC64LE-NEXT: .LBB535_1: |
| 9113 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 9114 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 9115 | ; PPC64LE-NEXT: ble 0, .LBB535_3 |
| 9116 | ; PPC64LE-NEXT: # BB#2: |
| 9117 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 9118 | ; PPC64LE-NEXT: bne 0, .LBB535_1 |
| 9119 | ; PPC64LE-NEXT: .LBB535_3: |
| 9120 | ; PPC64LE-NEXT: mr 3, 5 |
| 9121 | ; PPC64LE-NEXT: blr |
| 9122 | %ret = atomicrmw umax i64* %ptr, i64 %val singlethread monotonic |
| 9123 | ret i64 %ret |
| 9124 | } |
| 9125 | |
| 9126 | define i64 @test536(i64* %ptr, i64 %val) { |
| 9127 | ; PPC64LE-LABEL: test536: |
| 9128 | ; PPC64LE: # BB#0: |
| 9129 | ; PPC64LE-NEXT: mr 5, 3 |
| 9130 | ; PPC64LE-NEXT: .LBB536_1: |
| 9131 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 9132 | ; PPC64LE-NEXT: cmpld 4, 3 |
| 9133 | ; PPC64LE-NEXT: ble 0, .LBB536_3 |
| 9134 | ; PPC64LE-NEXT: # BB#2: |
| 9135 | ; PPC64LE-NEXT: stdcx. 4, 0, 5 |
| 9136 | ; PPC64LE-NEXT: bne 0, .LBB536_1 |
| 9137 | ; PPC64LE-NEXT: .LBB536_3: |
| 9138 | ; PPC64LE-NEXT: lwsync |
| 9139 | ; PPC64LE-NEXT: blr |
| 9140 | %ret = atomicrmw umax i64* %ptr, i64 %val singlethread acquire |
| 9141 | ret i64 %ret |
| 9142 | } |
| 9143 | |
| 9144 | define i64 @test537(i64* %ptr, i64 %val) { |
| 9145 | ; PPC64LE-LABEL: test537: |
| 9146 | ; PPC64LE: # BB#0: |
| 9147 | ; PPC64LE-NEXT: lwsync |
| 9148 | ; PPC64LE-NEXT: .LBB537_1: |
| 9149 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 9150 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 9151 | ; PPC64LE-NEXT: ble 0, .LBB537_3 |
| 9152 | ; PPC64LE-NEXT: # BB#2: |
| 9153 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 9154 | ; PPC64LE-NEXT: bne 0, .LBB537_1 |
| 9155 | ; PPC64LE-NEXT: .LBB537_3: |
| 9156 | ; PPC64LE-NEXT: mr 3, 5 |
| 9157 | ; PPC64LE-NEXT: blr |
| 9158 | %ret = atomicrmw umax i64* %ptr, i64 %val singlethread release |
| 9159 | ret i64 %ret |
| 9160 | } |
| 9161 | |
| 9162 | define i64 @test538(i64* %ptr, i64 %val) { |
| 9163 | ; PPC64LE-LABEL: test538: |
| 9164 | ; PPC64LE: # BB#0: |
| 9165 | ; PPC64LE-NEXT: lwsync |
| 9166 | ; PPC64LE-NEXT: .LBB538_1: |
| 9167 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 9168 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 9169 | ; PPC64LE-NEXT: ble 0, .LBB538_3 |
| 9170 | ; PPC64LE-NEXT: # BB#2: |
| 9171 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 9172 | ; PPC64LE-NEXT: bne 0, .LBB538_1 |
| 9173 | ; PPC64LE-NEXT: .LBB538_3: |
| 9174 | ; PPC64LE-NEXT: mr 3, 5 |
| 9175 | ; PPC64LE-NEXT: lwsync |
| 9176 | ; PPC64LE-NEXT: blr |
| 9177 | %ret = atomicrmw umax i64* %ptr, i64 %val singlethread acq_rel |
| 9178 | ret i64 %ret |
| 9179 | } |
| 9180 | |
| 9181 | define i64 @test539(i64* %ptr, i64 %val) { |
| 9182 | ; PPC64LE-LABEL: test539: |
| 9183 | ; PPC64LE: # BB#0: |
| 9184 | ; PPC64LE-NEXT: sync |
| 9185 | ; PPC64LE-NEXT: .LBB539_1: |
| 9186 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 9187 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 9188 | ; PPC64LE-NEXT: ble 0, .LBB539_3 |
| 9189 | ; PPC64LE-NEXT: # BB#2: |
| 9190 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 9191 | ; PPC64LE-NEXT: bne 0, .LBB539_1 |
| 9192 | ; PPC64LE-NEXT: .LBB539_3: |
| 9193 | ; PPC64LE-NEXT: mr 3, 5 |
| 9194 | ; PPC64LE-NEXT: lwsync |
| 9195 | ; PPC64LE-NEXT: blr |
| 9196 | %ret = atomicrmw umax i64* %ptr, i64 %val singlethread seq_cst |
| 9197 | ret i64 %ret |
| 9198 | } |
| 9199 | |
| 9200 | define i8 @test540(i8* %ptr, i8 %val) { |
| 9201 | ; PPC64LE-LABEL: test540: |
| 9202 | ; PPC64LE: # BB#0: |
| 9203 | ; PPC64LE-NEXT: .LBB540_1: |
| 9204 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 9205 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9206 | ; PPC64LE-NEXT: bge 0, .LBB540_3 |
| 9207 | ; PPC64LE-NEXT: # BB#2: |
| 9208 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 9209 | ; PPC64LE-NEXT: bne 0, .LBB540_1 |
| 9210 | ; PPC64LE-NEXT: .LBB540_3: |
| 9211 | ; PPC64LE-NEXT: mr 3, 5 |
| 9212 | ; PPC64LE-NEXT: blr |
| 9213 | %ret = atomicrmw umin i8* %ptr, i8 %val singlethread monotonic |
| 9214 | ret i8 %ret |
| 9215 | } |
| 9216 | |
| 9217 | define i8 @test541(i8* %ptr, i8 %val) { |
| 9218 | ; PPC64LE-LABEL: test541: |
| 9219 | ; PPC64LE: # BB#0: |
| 9220 | ; PPC64LE-NEXT: mr 5, 3 |
| 9221 | ; PPC64LE-NEXT: .LBB541_1: |
| 9222 | ; PPC64LE-NEXT: lbarx 3, 0, 5 |
| 9223 | ; PPC64LE-NEXT: cmplw 4, 3 |
| 9224 | ; PPC64LE-NEXT: bge 0, .LBB541_3 |
| 9225 | ; PPC64LE-NEXT: # BB#2: |
| 9226 | ; PPC64LE-NEXT: stbcx. 4, 0, 5 |
| 9227 | ; PPC64LE-NEXT: bne 0, .LBB541_1 |
| 9228 | ; PPC64LE-NEXT: .LBB541_3: |
| 9229 | ; PPC64LE-NEXT: lwsync |
| 9230 | ; PPC64LE-NEXT: blr |
| 9231 | %ret = atomicrmw umin i8* %ptr, i8 %val singlethread acquire |
| 9232 | ret i8 %ret |
| 9233 | } |
| 9234 | |
| 9235 | define i8 @test542(i8* %ptr, i8 %val) { |
| 9236 | ; PPC64LE-LABEL: test542: |
| 9237 | ; PPC64LE: # BB#0: |
| 9238 | ; PPC64LE-NEXT: lwsync |
| 9239 | ; PPC64LE-NEXT: .LBB542_1: |
| 9240 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 9241 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9242 | ; PPC64LE-NEXT: bge 0, .LBB542_3 |
| 9243 | ; PPC64LE-NEXT: # BB#2: |
| 9244 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 9245 | ; PPC64LE-NEXT: bne 0, .LBB542_1 |
| 9246 | ; PPC64LE-NEXT: .LBB542_3: |
| 9247 | ; PPC64LE-NEXT: mr 3, 5 |
| 9248 | ; PPC64LE-NEXT: blr |
| 9249 | %ret = atomicrmw umin i8* %ptr, i8 %val singlethread release |
| 9250 | ret i8 %ret |
| 9251 | } |
| 9252 | |
| 9253 | define i8 @test543(i8* %ptr, i8 %val) { |
| 9254 | ; PPC64LE-LABEL: test543: |
| 9255 | ; PPC64LE: # BB#0: |
| 9256 | ; PPC64LE-NEXT: lwsync |
| 9257 | ; PPC64LE-NEXT: .LBB543_1: |
| 9258 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 9259 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9260 | ; PPC64LE-NEXT: bge 0, .LBB543_3 |
| 9261 | ; PPC64LE-NEXT: # BB#2: |
| 9262 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 9263 | ; PPC64LE-NEXT: bne 0, .LBB543_1 |
| 9264 | ; PPC64LE-NEXT: .LBB543_3: |
| 9265 | ; PPC64LE-NEXT: mr 3, 5 |
| 9266 | ; PPC64LE-NEXT: lwsync |
| 9267 | ; PPC64LE-NEXT: blr |
| 9268 | %ret = atomicrmw umin i8* %ptr, i8 %val singlethread acq_rel |
| 9269 | ret i8 %ret |
| 9270 | } |
| 9271 | |
| 9272 | define i8 @test544(i8* %ptr, i8 %val) { |
| 9273 | ; PPC64LE-LABEL: test544: |
| 9274 | ; PPC64LE: # BB#0: |
| 9275 | ; PPC64LE-NEXT: sync |
| 9276 | ; PPC64LE-NEXT: .LBB544_1: |
| 9277 | ; PPC64LE-NEXT: lbarx 5, 0, 3 |
| 9278 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9279 | ; PPC64LE-NEXT: bge 0, .LBB544_3 |
| 9280 | ; PPC64LE-NEXT: # BB#2: |
| 9281 | ; PPC64LE-NEXT: stbcx. 4, 0, 3 |
| 9282 | ; PPC64LE-NEXT: bne 0, .LBB544_1 |
| 9283 | ; PPC64LE-NEXT: .LBB544_3: |
| 9284 | ; PPC64LE-NEXT: mr 3, 5 |
| 9285 | ; PPC64LE-NEXT: lwsync |
| 9286 | ; PPC64LE-NEXT: blr |
| 9287 | %ret = atomicrmw umin i8* %ptr, i8 %val singlethread seq_cst |
| 9288 | ret i8 %ret |
| 9289 | } |
| 9290 | |
| 9291 | define i16 @test545(i16* %ptr, i16 %val) { |
| 9292 | ; PPC64LE-LABEL: test545: |
| 9293 | ; PPC64LE: # BB#0: |
| 9294 | ; PPC64LE-NEXT: .LBB545_1: |
| 9295 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 9296 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9297 | ; PPC64LE-NEXT: bge 0, .LBB545_3 |
| 9298 | ; PPC64LE-NEXT: # BB#2: |
| 9299 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 9300 | ; PPC64LE-NEXT: bne 0, .LBB545_1 |
| 9301 | ; PPC64LE-NEXT: .LBB545_3: |
| 9302 | ; PPC64LE-NEXT: mr 3, 5 |
| 9303 | ; PPC64LE-NEXT: blr |
| 9304 | %ret = atomicrmw umin i16* %ptr, i16 %val singlethread monotonic |
| 9305 | ret i16 %ret |
| 9306 | } |
| 9307 | |
| 9308 | define i16 @test546(i16* %ptr, i16 %val) { |
| 9309 | ; PPC64LE-LABEL: test546: |
| 9310 | ; PPC64LE: # BB#0: |
| 9311 | ; PPC64LE-NEXT: mr 5, 3 |
| 9312 | ; PPC64LE-NEXT: .LBB546_1: |
| 9313 | ; PPC64LE-NEXT: lharx 3, 0, 5 |
| 9314 | ; PPC64LE-NEXT: cmplw 4, 3 |
| 9315 | ; PPC64LE-NEXT: bge 0, .LBB546_3 |
| 9316 | ; PPC64LE-NEXT: # BB#2: |
| 9317 | ; PPC64LE-NEXT: sthcx. 4, 0, 5 |
| 9318 | ; PPC64LE-NEXT: bne 0, .LBB546_1 |
| 9319 | ; PPC64LE-NEXT: .LBB546_3: |
| 9320 | ; PPC64LE-NEXT: lwsync |
| 9321 | ; PPC64LE-NEXT: blr |
| 9322 | %ret = atomicrmw umin i16* %ptr, i16 %val singlethread acquire |
| 9323 | ret i16 %ret |
| 9324 | } |
| 9325 | |
| 9326 | define i16 @test547(i16* %ptr, i16 %val) { |
| 9327 | ; PPC64LE-LABEL: test547: |
| 9328 | ; PPC64LE: # BB#0: |
| 9329 | ; PPC64LE-NEXT: lwsync |
| 9330 | ; PPC64LE-NEXT: .LBB547_1: |
| 9331 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 9332 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9333 | ; PPC64LE-NEXT: bge 0, .LBB547_3 |
| 9334 | ; PPC64LE-NEXT: # BB#2: |
| 9335 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 9336 | ; PPC64LE-NEXT: bne 0, .LBB547_1 |
| 9337 | ; PPC64LE-NEXT: .LBB547_3: |
| 9338 | ; PPC64LE-NEXT: mr 3, 5 |
| 9339 | ; PPC64LE-NEXT: blr |
| 9340 | %ret = atomicrmw umin i16* %ptr, i16 %val singlethread release |
| 9341 | ret i16 %ret |
| 9342 | } |
| 9343 | |
| 9344 | define i16 @test548(i16* %ptr, i16 %val) { |
| 9345 | ; PPC64LE-LABEL: test548: |
| 9346 | ; PPC64LE: # BB#0: |
| 9347 | ; PPC64LE-NEXT: lwsync |
| 9348 | ; PPC64LE-NEXT: .LBB548_1: |
| 9349 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 9350 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9351 | ; PPC64LE-NEXT: bge 0, .LBB548_3 |
| 9352 | ; PPC64LE-NEXT: # BB#2: |
| 9353 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 9354 | ; PPC64LE-NEXT: bne 0, .LBB548_1 |
| 9355 | ; PPC64LE-NEXT: .LBB548_3: |
| 9356 | ; PPC64LE-NEXT: mr 3, 5 |
| 9357 | ; PPC64LE-NEXT: lwsync |
| 9358 | ; PPC64LE-NEXT: blr |
| 9359 | %ret = atomicrmw umin i16* %ptr, i16 %val singlethread acq_rel |
| 9360 | ret i16 %ret |
| 9361 | } |
| 9362 | |
| 9363 | define i16 @test549(i16* %ptr, i16 %val) { |
| 9364 | ; PPC64LE-LABEL: test549: |
| 9365 | ; PPC64LE: # BB#0: |
| 9366 | ; PPC64LE-NEXT: sync |
| 9367 | ; PPC64LE-NEXT: .LBB549_1: |
| 9368 | ; PPC64LE-NEXT: lharx 5, 0, 3 |
| 9369 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9370 | ; PPC64LE-NEXT: bge 0, .LBB549_3 |
| 9371 | ; PPC64LE-NEXT: # BB#2: |
| 9372 | ; PPC64LE-NEXT: sthcx. 4, 0, 3 |
| 9373 | ; PPC64LE-NEXT: bne 0, .LBB549_1 |
| 9374 | ; PPC64LE-NEXT: .LBB549_3: |
| 9375 | ; PPC64LE-NEXT: mr 3, 5 |
| 9376 | ; PPC64LE-NEXT: lwsync |
| 9377 | ; PPC64LE-NEXT: blr |
| 9378 | %ret = atomicrmw umin i16* %ptr, i16 %val singlethread seq_cst |
| 9379 | ret i16 %ret |
| 9380 | } |
| 9381 | |
| 9382 | define i32 @test550(i32* %ptr, i32 %val) { |
| 9383 | ; PPC64LE-LABEL: test550: |
| 9384 | ; PPC64LE: # BB#0: |
| 9385 | ; PPC64LE-NEXT: .LBB550_1: |
| 9386 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 9387 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9388 | ; PPC64LE-NEXT: bge 0, .LBB550_3 |
| 9389 | ; PPC64LE-NEXT: # BB#2: |
| 9390 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 9391 | ; PPC64LE-NEXT: bne 0, .LBB550_1 |
| 9392 | ; PPC64LE-NEXT: .LBB550_3: |
| 9393 | ; PPC64LE-NEXT: mr 3, 5 |
| 9394 | ; PPC64LE-NEXT: blr |
| 9395 | %ret = atomicrmw umin i32* %ptr, i32 %val singlethread monotonic |
| 9396 | ret i32 %ret |
| 9397 | } |
| 9398 | |
| 9399 | define i32 @test551(i32* %ptr, i32 %val) { |
| 9400 | ; PPC64LE-LABEL: test551: |
| 9401 | ; PPC64LE: # BB#0: |
| 9402 | ; PPC64LE-NEXT: mr 5, 3 |
| 9403 | ; PPC64LE-NEXT: .LBB551_1: |
| 9404 | ; PPC64LE-NEXT: lwarx 3, 0, 5 |
| 9405 | ; PPC64LE-NEXT: cmplw 4, 3 |
| 9406 | ; PPC64LE-NEXT: bge 0, .LBB551_3 |
| 9407 | ; PPC64LE-NEXT: # BB#2: |
| 9408 | ; PPC64LE-NEXT: stwcx. 4, 0, 5 |
| 9409 | ; PPC64LE-NEXT: bne 0, .LBB551_1 |
| 9410 | ; PPC64LE-NEXT: .LBB551_3: |
| 9411 | ; PPC64LE-NEXT: lwsync |
| 9412 | ; PPC64LE-NEXT: blr |
| 9413 | %ret = atomicrmw umin i32* %ptr, i32 %val singlethread acquire |
| 9414 | ret i32 %ret |
| 9415 | } |
| 9416 | |
| 9417 | define i32 @test552(i32* %ptr, i32 %val) { |
| 9418 | ; PPC64LE-LABEL: test552: |
| 9419 | ; PPC64LE: # BB#0: |
| 9420 | ; PPC64LE-NEXT: lwsync |
| 9421 | ; PPC64LE-NEXT: .LBB552_1: |
| 9422 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 9423 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9424 | ; PPC64LE-NEXT: bge 0, .LBB552_3 |
| 9425 | ; PPC64LE-NEXT: # BB#2: |
| 9426 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 9427 | ; PPC64LE-NEXT: bne 0, .LBB552_1 |
| 9428 | ; PPC64LE-NEXT: .LBB552_3: |
| 9429 | ; PPC64LE-NEXT: mr 3, 5 |
| 9430 | ; PPC64LE-NEXT: blr |
| 9431 | %ret = atomicrmw umin i32* %ptr, i32 %val singlethread release |
| 9432 | ret i32 %ret |
| 9433 | } |
| 9434 | |
| 9435 | define i32 @test553(i32* %ptr, i32 %val) { |
| 9436 | ; PPC64LE-LABEL: test553: |
| 9437 | ; PPC64LE: # BB#0: |
| 9438 | ; PPC64LE-NEXT: lwsync |
| 9439 | ; PPC64LE-NEXT: .LBB553_1: |
| 9440 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 9441 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9442 | ; PPC64LE-NEXT: bge 0, .LBB553_3 |
| 9443 | ; PPC64LE-NEXT: # BB#2: |
| 9444 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 9445 | ; PPC64LE-NEXT: bne 0, .LBB553_1 |
| 9446 | ; PPC64LE-NEXT: .LBB553_3: |
| 9447 | ; PPC64LE-NEXT: mr 3, 5 |
| 9448 | ; PPC64LE-NEXT: lwsync |
| 9449 | ; PPC64LE-NEXT: blr |
| 9450 | %ret = atomicrmw umin i32* %ptr, i32 %val singlethread acq_rel |
| 9451 | ret i32 %ret |
| 9452 | } |
| 9453 | |
| 9454 | define i32 @test554(i32* %ptr, i32 %val) { |
| 9455 | ; PPC64LE-LABEL: test554: |
| 9456 | ; PPC64LE: # BB#0: |
| 9457 | ; PPC64LE-NEXT: sync |
| 9458 | ; PPC64LE-NEXT: .LBB554_1: |
| 9459 | ; PPC64LE-NEXT: lwarx 5, 0, 3 |
| 9460 | ; PPC64LE-NEXT: cmplw 4, 5 |
| 9461 | ; PPC64LE-NEXT: bge 0, .LBB554_3 |
| 9462 | ; PPC64LE-NEXT: # BB#2: |
| 9463 | ; PPC64LE-NEXT: stwcx. 4, 0, 3 |
| 9464 | ; PPC64LE-NEXT: bne 0, .LBB554_1 |
| 9465 | ; PPC64LE-NEXT: .LBB554_3: |
| 9466 | ; PPC64LE-NEXT: mr 3, 5 |
| 9467 | ; PPC64LE-NEXT: lwsync |
| 9468 | ; PPC64LE-NEXT: blr |
| 9469 | %ret = atomicrmw umin i32* %ptr, i32 %val singlethread seq_cst |
| 9470 | ret i32 %ret |
| 9471 | } |
| 9472 | |
| 9473 | define i64 @test555(i64* %ptr, i64 %val) { |
| 9474 | ; PPC64LE-LABEL: test555: |
| 9475 | ; PPC64LE: # BB#0: |
| 9476 | ; PPC64LE-NEXT: .LBB555_1: |
| 9477 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 9478 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 9479 | ; PPC64LE-NEXT: bge 0, .LBB555_3 |
| 9480 | ; PPC64LE-NEXT: # BB#2: |
| 9481 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 9482 | ; PPC64LE-NEXT: bne 0, .LBB555_1 |
| 9483 | ; PPC64LE-NEXT: .LBB555_3: |
| 9484 | ; PPC64LE-NEXT: mr 3, 5 |
| 9485 | ; PPC64LE-NEXT: blr |
| 9486 | %ret = atomicrmw umin i64* %ptr, i64 %val singlethread monotonic |
| 9487 | ret i64 %ret |
| 9488 | } |
| 9489 | |
| 9490 | define i64 @test556(i64* %ptr, i64 %val) { |
| 9491 | ; PPC64LE-LABEL: test556: |
| 9492 | ; PPC64LE: # BB#0: |
| 9493 | ; PPC64LE-NEXT: mr 5, 3 |
| 9494 | ; PPC64LE-NEXT: .LBB556_1: |
| 9495 | ; PPC64LE-NEXT: ldarx 3, 0, 5 |
| 9496 | ; PPC64LE-NEXT: cmpld 4, 3 |
| 9497 | ; PPC64LE-NEXT: bge 0, .LBB556_3 |
| 9498 | ; PPC64LE-NEXT: # BB#2: |
| 9499 | ; PPC64LE-NEXT: stdcx. 4, 0, 5 |
| 9500 | ; PPC64LE-NEXT: bne 0, .LBB556_1 |
| 9501 | ; PPC64LE-NEXT: .LBB556_3: |
| 9502 | ; PPC64LE-NEXT: lwsync |
| 9503 | ; PPC64LE-NEXT: blr |
| 9504 | %ret = atomicrmw umin i64* %ptr, i64 %val singlethread acquire |
| 9505 | ret i64 %ret |
| 9506 | } |
| 9507 | |
| 9508 | define i64 @test557(i64* %ptr, i64 %val) { |
| 9509 | ; PPC64LE-LABEL: test557: |
| 9510 | ; PPC64LE: # BB#0: |
| 9511 | ; PPC64LE-NEXT: lwsync |
| 9512 | ; PPC64LE-NEXT: .LBB557_1: |
| 9513 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 9514 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 9515 | ; PPC64LE-NEXT: bge 0, .LBB557_3 |
| 9516 | ; PPC64LE-NEXT: # BB#2: |
| 9517 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 9518 | ; PPC64LE-NEXT: bne 0, .LBB557_1 |
| 9519 | ; PPC64LE-NEXT: .LBB557_3: |
| 9520 | ; PPC64LE-NEXT: mr 3, 5 |
| 9521 | ; PPC64LE-NEXT: blr |
| 9522 | %ret = atomicrmw umin i64* %ptr, i64 %val singlethread release |
| 9523 | ret i64 %ret |
| 9524 | } |
| 9525 | |
| 9526 | define i64 @test558(i64* %ptr, i64 %val) { |
| 9527 | ; PPC64LE-LABEL: test558: |
| 9528 | ; PPC64LE: # BB#0: |
| 9529 | ; PPC64LE-NEXT: lwsync |
| 9530 | ; PPC64LE-NEXT: .LBB558_1: |
| 9531 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 9532 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 9533 | ; PPC64LE-NEXT: bge 0, .LBB558_3 |
| 9534 | ; PPC64LE-NEXT: # BB#2: |
| 9535 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 9536 | ; PPC64LE-NEXT: bne 0, .LBB558_1 |
| 9537 | ; PPC64LE-NEXT: .LBB558_3: |
| 9538 | ; PPC64LE-NEXT: mr 3, 5 |
| 9539 | ; PPC64LE-NEXT: lwsync |
| 9540 | ; PPC64LE-NEXT: blr |
| 9541 | %ret = atomicrmw umin i64* %ptr, i64 %val singlethread acq_rel |
| 9542 | ret i64 %ret |
| 9543 | } |
| 9544 | |
| 9545 | define i64 @test559(i64* %ptr, i64 %val) { |
| 9546 | ; PPC64LE-LABEL: test559: |
| 9547 | ; PPC64LE: # BB#0: |
| 9548 | ; PPC64LE-NEXT: sync |
| 9549 | ; PPC64LE-NEXT: .LBB559_1: |
| 9550 | ; PPC64LE-NEXT: ldarx 5, 0, 3 |
| 9551 | ; PPC64LE-NEXT: cmpld 4, 5 |
| 9552 | ; PPC64LE-NEXT: bge 0, .LBB559_3 |
| 9553 | ; PPC64LE-NEXT: # BB#2: |
| 9554 | ; PPC64LE-NEXT: stdcx. 4, 0, 3 |
| 9555 | ; PPC64LE-NEXT: bne 0, .LBB559_1 |
| 9556 | ; PPC64LE-NEXT: .LBB559_3: |
| 9557 | ; PPC64LE-NEXT: mr 3, 5 |
| 9558 | ; PPC64LE-NEXT: lwsync |
| 9559 | ; PPC64LE-NEXT: blr |
| 9560 | %ret = atomicrmw umin i64* %ptr, i64 %val singlethread seq_cst |
| 9561 | ret i64 %ret |
| 9562 | } |
Tim Shen | 3bef27c | 2017-05-16 20:18:06 +0000 | [diff] [blame] | 9563 | |
| 9564 | ; The second load should never be scheduled before isync. |
| 9565 | define i32 @test_ordering0(i32* %ptr1, i32* %ptr2) { |
| 9566 | ; PPC64LE-LABEL: test_ordering0: |
| 9567 | ; PPC64LE: # BB#0: |
| 9568 | ; PPC64LE-NEXT: lwz 4, 0(3) |
Hiroshi Inoue | 7a08bb1 | 2017-06-15 16:51:28 +0000 | [diff] [blame^] | 9569 | ; PPC64LE-NEXT: cmpd 7, 4, 4 |
Tim Shen | 3bef27c | 2017-05-16 20:18:06 +0000 | [diff] [blame] | 9570 | ; PPC64LE-NEXT: bne- 7, .+4 |
| 9571 | ; PPC64LE-NEXT: isync |
| 9572 | ; PPC64LE-NEXT: lwz 3, 0(3) |
| 9573 | ; PPC64LE-NEXT: add 3, 4, 3 |
| 9574 | ; PPC64LE-NEXT: blr |
| 9575 | %val1 = load atomic i32, i32* %ptr1 acquire, align 4 |
| 9576 | %val2 = load i32, i32* %ptr1 |
| 9577 | %add = add i32 %val1, %val2 |
| 9578 | ret i32 %add |
| 9579 | } |
| 9580 | |
| 9581 | ; The second store should never be scheduled before isync. |
| 9582 | define i32 @test_ordering1(i32* %ptr1, i32 %val1, i32* %ptr2) { |
| 9583 | ; PPC64LE-LABEL: test_ordering1: |
| 9584 | ; PPC64LE: # BB#0: |
| 9585 | ; PPC64LE-NEXT: lwz 3, 0(3) |
Hiroshi Inoue | 7a08bb1 | 2017-06-15 16:51:28 +0000 | [diff] [blame^] | 9586 | ; PPC64LE-NEXT: cmpd 7, 3, 3 |
Tim Shen | 3bef27c | 2017-05-16 20:18:06 +0000 | [diff] [blame] | 9587 | ; PPC64LE-NEXT: bne- 7, .+4 |
| 9588 | ; PPC64LE-NEXT: isync |
| 9589 | ; PPC64LE-NEXT: stw 4, 0(5) |
| 9590 | ; PPC64LE-NEXT: blr |
| 9591 | %val2 = load atomic i32, i32* %ptr1 acquire, align 4 |
| 9592 | store i32 %val1, i32* %ptr2 |
| 9593 | ret i32 %val2 |
| 9594 | } |