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gerrit-public.fairphone.software / toolchain / llvm-project / 28a5cadb3ae0dfed9530dcbee8a0ec154f3f9f91 / . / llvm / lib / Target / AMDGPU / AMDGPUInstructionSelector.h
blob: b7af40ac916725e04510bac08af9e1dd04e90b43 [file] [log] [blame]
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +0000[diff] [blame]3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the InstructionSelector class for
10/// AMDGPU.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000[diff] [blame]16#include "AMDGPU.h"
Matt Arsenaultb1cc4f52018-06-25 16:17:48 +0000[diff] [blame]17#include "AMDGPUArgumentUsageInfo.h"
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/SmallVector.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +0000[diff] [blame]20#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]21
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]22namespace {
23#define GET_GLOBALISEL_PREDICATE_BITSET
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]24#define AMDGPUSubtarget GCNSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]25#include "AMDGPUGenGlobalISel.inc"
26#undef GET_GLOBALISEL_PREDICATE_BITSET
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]27#undef AMDGPUSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]28}
29
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]30namespace llvm {
31
32class AMDGPUInstrInfo;
33class AMDGPURegisterBankInfo;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]34class GCNSubtarget;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]35class MachineInstr;
36class MachineOperand;
37class MachineRegisterInfo;
38class SIInstrInfo;
Matt Arsenaultb1cc4f52018-06-25 16:17:48 +0000[diff] [blame]39class SIMachineFunctionInfo;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]40class SIRegisterInfo;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]41
42class AMDGPUInstructionSelector : public InstructionSelector {
43public:
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]44 AMDGPUInstructionSelector(const GCNSubtarget &STI,
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]45 const AMDGPURegisterBankInfo &RBI,
46 const AMDGPUTargetMachine &TM);
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]47
Daniel Sandersf76f3152017-11-16 00:46:35 +0000[diff] [blame]48 bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]49 static const char *getName();
Daniel Sandersf76f3152017-11-16 00:46:35 +0000[diff] [blame]50
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]51private:
52 struct GEPInfo {
53 const MachineInstr &GEP;
54 SmallVector<unsigned, 2> SgprParts;
55 SmallVector<unsigned, 2> VgprParts;
56 int64_t Imm;
57 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
58 };
59
Tom Stellard79b5c382019-02-20 21:02:37 +0000[diff] [blame]60 bool isInstrUniform(const MachineInstr &MI) const;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]61 /// tblgen-erated 'select' implementation.
62 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
63
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]64 MachineOperand getSubOperand64(MachineOperand &MO, unsigned SubIdx) const;
Tom Stellard1e0edad2018-05-10 21:20:10 +0000[diff] [blame]65 bool selectCOPY(MachineInstr &I) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]66 bool selectG_CONSTANT(MachineInstr &I) const;
67 bool selectG_ADD(MachineInstr &I) const;
Tom Stellard41f32192019-02-28 23:37:48 +0000[diff] [blame]68 bool selectG_EXTRACT(MachineInstr &I) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]69 bool selectG_GEP(MachineInstr &I) const;
Tom Stellard3f1c6fe2018-06-21 23:38:20 +0000[diff] [blame]70 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
Tom Stellard33634d1b2019-03-01 00:50:26 +0000[diff] [blame]71 bool selectG_INSERT(MachineInstr &I) const;
Tom Stellarda9284732018-06-14 19:26:37 +0000[diff] [blame]72 bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
Tom Stellard390a5f42018-07-13 21:05:14 +0000[diff] [blame]73 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I,
74 CodeGenCoverage &CoverageInfo) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]75 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
76 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
77 SmallVectorImpl<GEPInfo> &AddrInfo) const;
78 bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
79 bool selectG_LOAD(MachineInstr &I) const;
80 bool selectG_STORE(MachineInstr &I) const;
81
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]82 InstructionSelector::ComplexRendererFns
Tom Stellard26fac0f2018-06-22 02:54:57 +0000[diff] [blame]83 selectVCSRC(MachineOperand &Root) const;
84
85 InstructionSelector::ComplexRendererFns
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]86 selectVSRC0(MachineOperand &Root) const;
87
Tom Stellarddcc95e92018-05-11 05:44:16 +0000[diff] [blame]88 InstructionSelector::ComplexRendererFns
89 selectVOP3Mods0(MachineOperand &Root) const;
Tom Stellard46bbbc32018-06-13 22:30:47 +0000[diff] [blame]90 InstructionSelector::ComplexRendererFns
Tom Stellard9a653572018-06-22 02:34:29 +0000[diff] [blame]91 selectVOP3OMods(MachineOperand &Root) const;
92 InstructionSelector::ComplexRendererFns
Tom Stellard46bbbc32018-06-13 22:30:47 +0000[diff] [blame]93 selectVOP3Mods(MachineOperand &Root) const;
Tom Stellarddcc95e92018-05-11 05:44:16 +0000[diff] [blame]94
Tom Stellard79b5c382019-02-20 21:02:37 +0000[diff] [blame]95 InstructionSelector::ComplexRendererFns
96 selectSmrdImm(MachineOperand &Root) const;
97 InstructionSelector::ComplexRendererFns
98 selectSmrdImm32(MachineOperand &Root) const;
99 InstructionSelector::ComplexRendererFns
100 selectSmrdSgpr(MachineOperand &Root) const;
101
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]102 const SIInstrInfo &TII;
103 const SIRegisterInfo &TRI;
104 const AMDGPURegisterBankInfo &RBI;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]105 const AMDGPUTargetMachine &TM;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]106 const GCNSubtarget &STI;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]107 bool EnableLateStructurizeCFG;
108#define GET_GLOBALISEL_PREDICATES_DECL
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]109#define AMDGPUSubtarget GCNSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]110#include "AMDGPUGenGlobalISel.inc"
111#undef GET_GLOBALISEL_PREDICATES_DECL
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]112#undef AMDGPUSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]113
114#define GET_GLOBALISEL_TEMPORARIES_DECL
115#include "AMDGPUGenGlobalISel.inc"
116#undef GET_GLOBALISEL_TEMPORARIES_DECL
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]117};
118
119} // End llvm namespace.
120#endif