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gerrit-public.fairphone.software / toolchain / llvm-project / 2ce2ab3a4dc1df6ec87a42aa2baa6741c2456e0c / . / llvm / lib / Target / ARM / ARM.td
blob: 1aa975bd54ae4dfd0283a78e62526a124b248497 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// Target-independent interfaces which we are implementing
15//===----------------------------------------------------------------------===//
16
Evan Cheng977e7be2008-11-24 07:34:46 +0000[diff] [blame]17include "llvm/Target/Target.td"
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]18
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]19//===----------------------------------------------------------------------===//
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]20// ARM Helper classes.
21//
22
23class ProcNoItin<string Name, list<SubtargetFeature> Features>
24 : Processor<Name, NoItineraries, Features>;
25
26class Architecture<string fname, string aname, list<SubtargetFeature> features >
27 : SubtargetFeature<fname, "ARMArch", aname,
28 !strconcat(aname, " architecture"), features>;
29
30//===----------------------------------------------------------------------===//
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]31// ARM Subtarget state.
32//
33
Evan Cheng1834f5d2011-07-07 19:05:12 +0000[diff] [blame]34def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]35 "Thumb mode">;
Jim Grosbach080fdf42010-09-30 01:57:53 +0000[diff] [blame]36
Eric Christopher824f42f2015-05-12 01:26:05 +0000[diff] [blame]37def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
38 "Use software floating point features.">;
39
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]40//===----------------------------------------------------------------------===//
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]41// ARM Subtarget features.
42//
43
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]44def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
Anton Korobeynikovb6f45382009-05-29 23:41:08 +0000[diff] [blame]45 "Enable VFP2 instructions">;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]46def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
47 "Enable VFP3 instructions",
48 [FeatureVFP2]>;
49def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
50 "Enable NEON instructions",
51 [FeatureVFP3]>;
Evan Cheng2bd65362011-07-07 00:08:19 +0000[diff] [blame]52def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
Anton Korobeynikovb6f45382009-05-29 23:41:08 +0000[diff] [blame]53 "Enable Thumb2 instructions">;
Evan Cheng5190f092010-08-11 07:17:46 +0000[diff] [blame]54def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
Tim Northovera2292d02013-06-10 23:20:58 +0000[diff] [blame]55 "Does not support ARM mode execution",
56 [ModeThumb]>;
Anton Korobeynikov0a65a372010-03-14 18:42:38 +0000[diff] [blame]57def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
58 "Enable half-precision floating point">;
Bob Wilsone8a549c2012-09-29 21:43:49 +0000[diff] [blame]59def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
60 "Enable VFP4 instructions",
61 [FeatureVFP3, FeatureFP16]>;
Joey Goulyccd04892013-09-13 13:46:57 +0000[diff] [blame]62def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
Joey Goulyb1b0dd82013-06-27 11:49:26 +0000[diff] [blame]63 "true", "Enable ARMv8 FP",
64 [FeatureVFP4]>;
Oliver Stannard8addbf42015-12-01 10:23:06 +0000[diff] [blame]65def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
66 "Enable full half-precision floating point",
67 [FeatureFPARMv8]>;
Bob Wilsondd6eb5b2010-10-12 16:22:47 +0000[diff] [blame]68def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]69 "Restrict FP to 16 double registers">;
Jim Grosbach151cd8f2010-05-05 23:44:43 +0000[diff] [blame]70def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
71 "Enable divide instructions">;
Bob Wilsone8a549c2012-09-29 21:43:49 +0000[diff] [blame]72def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
73 "HasHardwareDivideInARM", "true",
74 "Enable divide instructions in ARM mode">;
Evan Cheng40921a42010-08-11 06:51:54 +0000[diff] [blame]75def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
Jim Grosbach151cd8f2010-05-05 23:44:43 +0000[diff] [blame]76 "Enable Thumb2 extract and pack instructions">;
Evan Cheng40921a42010-08-11 06:51:54 +0000[diff] [blame]77def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
78 "Has data barrier (dmb / dsb) instructions">;
Bradley Smith4c21cba2016-01-15 10:23:46 +0000[diff] [blame]79def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
80 "Has v7 clrex instruction">;
81def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
82 "HasAcquireRelease", "true",
83 "Has v8 acquire/release (lda/ldaex etc) instructions">;
Evan Cheng58066e32010-07-13 19:21:50 +0000[diff] [blame]84def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
85 "FP compare + branch is slow">;
Jim Grosbach4d5dc3e2010-08-11 15:44:15 +0000[diff] [blame]86def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
87 "Floating point unit supports single precision only">;
Tim Northovercedd4812013-05-23 19:11:14 +0000[diff] [blame]88def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
89 "Enable support for Performance Monitor extensions">;
Tim Northoverc6047652013-04-10 12:08:35 +0000[diff] [blame]90def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
91 "Enable support for TrustZone security extensions">;
Bradley Smithfed3e4a2016-01-25 11:24:47 +0000[diff] [blame]92def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
93 "Enable support for ARMv8-M Security Extensions">;
Amara Emerson33089092013-09-19 11:59:01 +0000[diff] [blame]94def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
95 "Enable support for Cryptography extensions",
96 [FeatureNEON]>;
Bernard Ogdenee87e852013-10-29 09:47:35 +0000[diff] [blame]97def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
98 "Enable support for CRC instructions">;
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]99// Not to be confused with FeatureHasRetAddrStack (return address stack)
100def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
101 "Enable Reliability, Availability and Serviceability extensions">;
102
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]103
Tim Northover13510302014-04-01 13:22:02 +0000[diff] [blame]104// Cyclone has preferred instructions for zeroing VFP registers, which can
105// execute in 0 cycles.
106def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
107 "Has zero-cycle zeroing instructions">;
108
Diana Picusc5baa432016-06-23 07:47:35 +0000[diff] [blame]109// Whether or not it may be profitable to unpredicate certain instructions
110// during if conversion.
111def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
112 "IsProfitableToUnpredicate",
113 "true",
114 "Is profitable to unpredicate">;
115
116// Some targets (e.g. Swift) have microcoded VGETLNi32.
117def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
118 "HasSlowVGETLNi32", "true",
119 "Has slow VGETLNi32 - prefer VMOV">;
120
121// Some targets (e.g. Swift) have microcoded VDUP32.
122def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true",
123 "Has slow VDUP32 - prefer VMOV">;
124
125// Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
126// for scalar FP, as this allows more effective execution domain optimization.
127def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
128 "true", "Prefer VMOVSR">;
129
130// Swift has ISHST barriers compatible with Atomic Release semantics but weaker
131// than ISH
132def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
133 "true", "Prefer ISHST barriers">;
134
Diana Picus4879b052016-07-06 09:22:23 +0000[diff] [blame]135// Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
136def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true",
137 "Has muxed AGU and NEON/FPU">;
138
139// On some targets, a VLDM/VSTM starting with an odd register number needs more
140// microops than single VLDRS.
141def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
142 "true", "VLDM/VSTM starting with an odd register is slow">;
143
144// Some targets have a renaming dependency when loading into D subregisters.
145def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
146 "SlowLoadDSubregister", "true",
147 "Loading into D subregs is slow">;
Diana Picusb772e402016-07-06 11:22:11 +0000[diff] [blame]148// Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
149def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
150 "DontWidenVMOVS", "true",
151 "Don't widen VMOVS to VMOVD">;
Diana Picus4879b052016-07-06 09:22:23 +0000[diff] [blame]152
Diana Picus575f2bb2016-07-07 09:11:39 +0000[diff] [blame]153// Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
154def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true",
155 "Expand VFP/NEON MLA/MLS instructions">;
156
157// Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
158def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
159 "true", "Has VMLx hazards">;
160
Diana Picusc5baa432016-06-23 07:47:35 +0000[diff] [blame]161// Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
162// VFP to NEON, as an execution domain optimization.
163def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs",
164 "true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">;
165
166// Some processors benefit from using NEON instructions for scalar
167// single-precision FP operations. This affects instruction selection and should
168// only be enabled if the handling of denormals is not important.
169def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
170 "true",
171 "Use NEON for single precision FP">;
172
Diana Picus92423ce2016-06-27 09:08:23 +0000[diff] [blame]173// On some processors, VLDn instructions that access unaligned data take one
174// extra cycle. Take that into account when computing operand latencies.
175def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
176 "true",
177 "Check for VLDn unaligned access">;
178
179// Some processors have a nonpipelined VFP coprocessor.
180def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
181 "NonpipelinedVFP", "true",
182 "VFP instructions are not pipelined">;
183
Evan Cheng62c7b5b2010-12-05 22:04:16 +0000[diff] [blame]184// Some processors have FP multiply-accumulate instructions that don't
185// play nicely with other VFP / NEON instructions, and it's generally better
Jim Grosbacha43386b2010-03-25 23:11:16 +0000[diff] [blame]186// to just not use them.
Evan Cheng62c7b5b2010-12-05 22:04:16 +0000[diff] [blame]187def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
188 "Disable VFP / NEON MAC instructions">;
Evan Cheng38bf5ad2011-03-31 19:38:48 +0000[diff] [blame]189
190// Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
191def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
192 "HasVMLxForwarding", "true",
193 "Has multiplier accumulator forwarding">;
194
Evan Chengce8fb682010-08-09 18:35:19 +0000[diff] [blame]195// Disable 32-bit to 16-bit narrowing for experimentation.
196def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
197 "Prefer 32-bit Thumb instrs">;
Jim Grosbacha43386b2010-03-25 23:11:16 +0000[diff] [blame]198
Bob Wilsona2881ee2011-04-19 18:11:49 +0000[diff] [blame]199/// Some instructions update CPSR partially, which can add false dependency for
200/// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
201/// mapped to a separate physical register. Avoid partial CPSR update for these
202/// processors.
203def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
204 "AvoidCPSRPartialUpdate", "true",
205 "Avoid CPSR partial update for OOO execution">;
206
Evan Chengddc0cb62012-12-20 19:59:30 +0000[diff] [blame]207def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
208 "AvoidMOVsShifterOperand", "true",
209 "Avoid movs instructions with shifter operand">;
210
Evan Cheng65f9d192012-02-28 18:51:51 +0000[diff] [blame]211// Some processors perform return stack prediction. CodeGen should avoid issue
212// "normal" call instructions to callees which do not return.
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]213def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true",
Evan Cheng65f9d192012-02-28 18:51:51 +0000[diff] [blame]214 "Has return address stack">;
215
Artyom Skrobov5a6e3942015-10-23 17:19:19 +0000[diff] [blame]216/// DSP extension.
217def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
Artyom Skrobovcf296442015-09-24 17:31:16 +0000[diff] [blame]218 "Supports DSP instructions in ARM and/or Thumb2">;
Jim Grosbachcf1464d2011-07-01 21:12:19 +0000[diff] [blame]219
Evan Cheng8740ee32010-11-03 06:34:55 +0000[diff] [blame]220// Multiprocessing extension.
221def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
222 "Supports Multiprocessing extension">;
Evan Cheng40921a42010-08-11 06:51:54 +0000[diff] [blame]223
Bradley Smith25219752013-11-01 13:27:35 +0000[diff] [blame]224// Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
225def FeatureVirtualization : SubtargetFeature<"virtualization",
226 "HasVirtualization", "true",
227 "Supports Virtualization extension",
228 [FeatureHWDiv, FeatureHWDivARM]>;
229
Amara Emerson330afb52013-09-23 14:26:15 +0000[diff] [blame]230// M-series ISA
231def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
James Molloy21efa7d2011-09-28 14:21:38 +0000[diff] [blame]232 "Is microcontroller profile ('M' series)">;
233
Amara Emerson330afb52013-09-23 14:26:15 +0000[diff] [blame]234// R-series ISA
235def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
236 "Is realtime profile ('R' series)">;
237
238// A-series ISA
239def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
240 "Is application profile ('A' series)">;
241
Eli Bendersky2e2ce492013-01-30 16:30:19 +0000[diff] [blame]242// Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
243// See ARMInstrInfo.td for details.
244def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
245 "NaCl trap">;
246
Akira Hatanaka2670f4a2015-07-28 22:44:28 +0000[diff] [blame]247def FeatureStrictAlign : SubtargetFeature<"strict-align",
248 "StrictAlign", "true",
249 "Disallow all unaligned memory "
250 "access">;
251
Akira Hatanaka1bc8af72015-07-07 06:54:42 +0000[diff] [blame]252def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
253 "Generate calls via indirect call "
254 "instructions">;
255
Akira Hatanaka28581522015-07-21 01:42:02 +0000[diff] [blame]256def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
257 "Reserve R9, making it unavailable as "
258 "GPR">;
259
Akira Hatanaka024d91a2015-07-16 00:58:23 +0000[diff] [blame]260def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
261 "Don't use movt/movw pairs for 32-bit "
262 "imms">;
263
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]264
265//===----------------------------------------------------------------------===//
266// ARM ISAa.
267//
268
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]269def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]270 "Support ARM v4T instructions">;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]271def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]272 "Support ARM v5T instructions",
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]273 [HasV4TOps]>;
274def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]275 "Support ARM v5TE, v5TEj, and v5TExp instructions",
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]276 [HasV5TOps]>;
277def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]278 "Support ARM v6 instructions",
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]279 [HasV5TEOps]>;
Tim Northoverf86d1f02013-10-07 11:10:47 +0000[diff] [blame]280def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
281 "Support ARM v6M instructions",
282 [HasV6Ops]>;
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]283def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
284 "Support ARM v8M Baseline instructions",
285 [HasV6MOps]>;
Renato Golin12350602015-03-17 11:55:28 +0000[diff] [blame]286def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
287 "Support ARM v6k instructions",
288 [HasV6Ops]>;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]289def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]290 "Support ARM v6t2 instructions",
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]291 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]292def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
Evan Chengf2c26162011-07-07 08:26:46 +0000[diff] [blame]293 "Support ARM v7 instructions",
Bradley Smith4c21cba2016-01-15 10:23:46 +0000[diff] [blame]294 [HasV6T2Ops, FeaturePerfMon,
295 FeatureV7Clrex]>;
Joey Goulyb3f550e2013-06-26 16:58:26 +0000[diff] [blame]296def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
297 "Support ARM v8 instructions",
Tim Northover554fbd02016-07-19 19:49:13 +0000[diff] [blame]298 [HasV7Ops, FeatureAcquireRelease,
299 FeatureT2XtPk]>;
Vladimir Sukharev2afdb322015-04-01 14:54:56 +0000[diff] [blame]300def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
Vladimir Sukharevc632cda2015-03-26 17:05:54 +0000[diff] [blame]301 "Support ARM v8.1a instructions",
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]302 [HasV8Ops]>;
Oliver Stannard8addbf42015-12-01 10:23:06 +0000[diff] [blame]303def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
304 "Support ARM v8.2a instructions",
305 [HasV8_1aOps]>;
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]306def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
307 "Support ARM v8M Mainline instructions",
308 [HasV7Ops]>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]309
Evan Cheng40921a42010-08-11 06:51:54 +0000[diff] [blame]310
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]311//===----------------------------------------------------------------------===//
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]312// ARM Processor subtarget features.
313//
314
315def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
316 "Cortex-A5 ARM processors", []>;
317def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
318 "Cortex-A7 ARM processors", []>;
319def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
320 "Cortex-A8 ARM processors", []>;
321def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
322 "Cortex-A9 ARM processors", []>;
323def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
324 "Cortex-A12 ARM processors", []>;
325def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
326 "Cortex-A15 ARM processors", []>;
327def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
328 "Cortex-A17 ARM processors", []>;
Renato Golin2b6b7ff2016-03-21 17:29:01 +0000[diff] [blame]329def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
330 "Cortex-A32 ARM processors", []>;
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]331def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
332 "Cortex-A35 ARM processors", []>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]333def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
334 "Cortex-A53 ARM processors", []>;
335def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
336 "Cortex-A57 ARM processors", []>;
337def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
338 "Cortex-A72 ARM processors", []>;
Sjoerd Meijer0b7bb162016-06-02 10:48:52 +0000[diff] [blame]339def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
340 "Cortex-A73 ARM processors", []>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]341
342def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
343 "Qualcomm ARM processors", []>;
344def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
345 "Swift ARM processors", []>;
346
MinSeong Kima7385eb2016-01-05 12:51:59 +0000[diff] [blame]347def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
348 "Samsung Exynos-M1 processors", []>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]349
350def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
Bradley Smith4c21cba2016-01-15 10:23:46 +0000[diff] [blame]351 "Cortex-R4 ARM processors", []>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]352def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
353 "Cortex-R5 ARM processors", []>;
354def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
355 "Cortex-R7 ARM processors", []>;
356
Artyom Skrobove6f1b7f2016-03-23 16:18:13 +0000[diff] [blame]357def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
358 "Cortex-M3 ARM processors", []>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]359
360//===----------------------------------------------------------------------===//
361// ARM schedules.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]362//
363
Evan Cheng4e712de2009-06-19 01:51:50 +0000[diff] [blame]364include "ARMSchedule.td"
365
Richard Bartonc31078c2013-11-22 11:53:16 +0000[diff] [blame]366
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]367//===----------------------------------------------------------------------===//
368// ARM architectures
369//
Bob Wilsone8a549c2012-09-29 21:43:49 +0000[diff] [blame]370
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]371def ARMv2 : Architecture<"armv2", "ARMv2", []>;
Bernard Ogden4400cde2013-10-14 13:16:57 +0000[diff] [blame]372
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]373def ARMv2a : Architecture<"armv2a", "ARMv2a", []>;
Renato Golin16ea8ba2014-10-13 10:22:19 +0000[diff] [blame]374
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]375def ARMv3 : Architecture<"armv3", "ARMv3", []>;
Bernard Ogden4400cde2013-10-14 13:16:57 +0000[diff] [blame]376
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]377def ARMv3m : Architecture<"armv3m", "ARMv3m", []>;
Bernard Ogden53169762013-10-14 13:17:07 +0000[diff] [blame]378
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]379def ARMv4 : Architecture<"armv4", "ARMv4", []>;
Javed Absar5c5e3c52015-04-09 14:07:28 +0000[diff] [blame]380
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]381def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>;
Evan Chengbf407072010-09-10 01:29:16 +0000[diff] [blame]382
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]383def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>;
Ana Pazos93a07c22013-12-06 22:48:17 +0000[diff] [blame]384
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]385def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>;
Rafael Espindolad89b16d2014-01-02 13:40:08 +0000[diff] [blame]386
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]387def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]388
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]389def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]390
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]391def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
Tim Northover554fbd02016-07-19 19:49:13 +0000[diff] [blame]392 FeatureDSP,
393 FeatureT2XtPk]>;
Anton Korobeynikovb6f45382009-05-29 23:41:08 +0000[diff] [blame]394
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]395def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
396
Artyom Skrobovf187a652015-11-16 14:05:32 +0000[diff] [blame]397def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]398 FeatureTrustZone]>;
399
400def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps,
401 FeatureNoARM,
402 FeatureDB,
403 FeatureMClass]>;
404
405def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps,
406 FeatureNoARM,
407 FeatureDB,
408 FeatureMClass]>;
409
410def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
411 FeatureNEON,
412 FeatureDB,
413 FeatureDSP,
Tim Northover554fbd02016-07-19 19:49:13 +0000[diff] [blame]414 FeatureAClass,
415 FeatureT2XtPk]>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]416
417def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
418 FeatureDB,
419 FeatureDSP,
420 FeatureHWDiv,
Tim Northover554fbd02016-07-19 19:49:13 +0000[diff] [blame]421 FeatureRClass,
422 FeatureT2XtPk]>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]423
424def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
425 FeatureThumb2,
426 FeatureNoARM,
427 FeatureDB,
428 FeatureHWDiv,
429 FeatureMClass]>;
430
431def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
432 FeatureThumb2,
433 FeatureNoARM,
434 FeatureDB,
435 FeatureHWDiv,
436 FeatureMClass,
437 FeatureDSP,
438 FeatureT2XtPk]>;
439
440def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops,
441 FeatureAClass,
442 FeatureDB,
443 FeatureFPARMv8,
444 FeatureNEON,
445 FeatureDSP,
446 FeatureTrustZone,
447 FeatureMP,
448 FeatureVirtualization,
449 FeatureCrypto,
450 FeatureCRC]>;
451
452def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps,
453 FeatureAClass,
454 FeatureDB,
455 FeatureFPARMv8,
456 FeatureNEON,
457 FeatureDSP,
458 FeatureTrustZone,
459 FeatureMP,
460 FeatureVirtualization,
461 FeatureCrypto,
462 FeatureCRC]>;
463
Oliver Stannard46670712015-12-01 10:33:56 +0000[diff] [blame]464def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps,
465 FeatureAClass,
466 FeatureDB,
467 FeatureFPARMv8,
468 FeatureNEON,
469 FeatureDSP,
470 FeatureTrustZone,
471 FeatureMP,
472 FeatureVirtualization,
473 FeatureCrypto,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]474 FeatureCRC,
475 FeatureRAS]>;
Oliver Stannard46670712015-12-01 10:33:56 +0000[diff] [blame]476
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]477def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
478 [HasV8MBaselineOps,
479 FeatureNoARM,
480 FeatureDB,
481 FeatureHWDiv,
Bradley Smith433c22e2016-01-15 10:26:51 +0000[diff] [blame]482 FeatureV7Clrex,
Bradley Smithfed3e4a2016-01-25 11:24:47 +0000[diff] [blame]483 Feature8MSecExt,
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]484 FeatureAcquireRelease,
485 FeatureMClass]>;
486
487def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
488 [HasV8MMainlineOps,
489 FeatureNoARM,
490 FeatureDB,
491 FeatureHWDiv,
Bradley Smithfed3e4a2016-01-25 11:24:47 +0000[diff] [blame]492 Feature8MSecExt,
Bradley Smithe26f7992016-01-15 10:24:39 +0000[diff] [blame]493 FeatureAcquireRelease,
494 FeatureMClass]>;
495
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]496// Aliases
497def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>;
498def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>;
499def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>;
500def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>;
501def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>;
502def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>;
503
504
505//===----------------------------------------------------------------------===//
506// ARM processors
507//
508
509// Dummy CPU, used to target architectures
510def : ProcNoItin<"generic", []>;
511
512def : ProcNoItin<"arm8", [ARMv4]>;
513def : ProcNoItin<"arm810", [ARMv4]>;
514def : ProcNoItin<"strongarm", [ARMv4]>;
515def : ProcNoItin<"strongarm110", [ARMv4]>;
516def : ProcNoItin<"strongarm1100", [ARMv4]>;
517def : ProcNoItin<"strongarm1110", [ARMv4]>;
518
519def : ProcNoItin<"arm7tdmi", [ARMv4t]>;
520def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>;
521def : ProcNoItin<"arm710t", [ARMv4t]>;
522def : ProcNoItin<"arm720t", [ARMv4t]>;
523def : ProcNoItin<"arm9", [ARMv4t]>;
524def : ProcNoItin<"arm9tdmi", [ARMv4t]>;
525def : ProcNoItin<"arm920", [ARMv4t]>;
526def : ProcNoItin<"arm920t", [ARMv4t]>;
527def : ProcNoItin<"arm922t", [ARMv4t]>;
528def : ProcNoItin<"arm940t", [ARMv4t]>;
529def : ProcNoItin<"ep9312", [ARMv4t]>;
530
531def : ProcNoItin<"arm10tdmi", [ARMv5t]>;
532def : ProcNoItin<"arm1020t", [ARMv5t]>;
533
534def : ProcNoItin<"arm9e", [ARMv5te]>;
535def : ProcNoItin<"arm926ej-s", [ARMv5te]>;
536def : ProcNoItin<"arm946e-s", [ARMv5te]>;
537def : ProcNoItin<"arm966e-s", [ARMv5te]>;
538def : ProcNoItin<"arm968e-s", [ARMv5te]>;
539def : ProcNoItin<"arm10e", [ARMv5te]>;
540def : ProcNoItin<"arm1020e", [ARMv5te]>;
541def : ProcNoItin<"arm1022e", [ARMv5te]>;
542def : ProcNoItin<"xscale", [ARMv5te]>;
543def : ProcNoItin<"iwmmxt", [ARMv5te]>;
544
545def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>;
546def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6,
547 FeatureVFP2,
548 FeatureHasSlowFPVMLx]>;
549
550def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>;
551def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>;
552def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>;
553def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>;
554
Artyom Skrobovf187a652015-11-16 14:05:32 +0000[diff] [blame]555def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>;
556def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]557 FeatureVFP2,
558 FeatureHasSlowFPVMLx]>;
559
560def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>;
561def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k,
562 FeatureVFP2,
563 FeatureHasSlowFPVMLx]>;
564
565def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>;
566def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2,
567 FeatureVFP2,
568 FeatureHasSlowFPVMLx]>;
569
Quentin Colombet13cd5212012-11-29 19:48:01 +0000[diff] [blame]570// FIXME: A5 has currently the same Schedule model as A8
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]571def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]572 FeatureHasRetAddrStack,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]573 FeatureTrustZone,
574 FeatureSlowFPBrcc,
575 FeatureHasSlowFPVMLx,
576 FeatureVMLxForwarding,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]577 FeatureMP,
578 FeatureVFP4]>;
579
580def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]581 FeatureHasRetAddrStack,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]582 FeatureTrustZone,
583 FeatureSlowFPBrcc,
Diana Picus575f2bb2016-07-07 09:11:39 +0000[diff] [blame]584 FeatureHasVMLxHazards,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]585 FeatureHasSlowFPVMLx,
586 FeatureVMLxForwarding,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]587 FeatureMP,
588 FeatureVFP4,
589 FeatureHWDiv,
590 FeatureHWDivARM,
591 FeatureVirtualization]>;
592
593def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]594 FeatureHasRetAddrStack,
Diana Picus92423ce2016-06-27 09:08:23 +0000[diff] [blame]595 FeatureNonpipelinedVFP,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]596 FeatureTrustZone,
597 FeatureSlowFPBrcc,
Diana Picus575f2bb2016-07-07 09:11:39 +0000[diff] [blame]598 FeatureHasVMLxHazards,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]599 FeatureHasSlowFPVMLx,
Tim Northover554fbd02016-07-19 19:49:13 +0000[diff] [blame]600 FeatureVMLxForwarding]>;
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]601
602def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]603 FeatureHasRetAddrStack,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]604 FeatureTrustZone,
Diana Picus575f2bb2016-07-07 09:11:39 +0000[diff] [blame]605 FeatureHasVMLxHazards,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]606 FeatureVMLxForwarding,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]607 FeatureFP16,
608 FeatureAvoidPartialCPSR,
Diana Picus575f2bb2016-07-07 09:11:39 +0000[diff] [blame]609 FeatureExpandMLx,
Diana Picusc5baa432016-06-23 07:47:35 +0000[diff] [blame]610 FeaturePreferVMOVSR,
Diana Picus4879b052016-07-06 09:22:23 +0000[diff] [blame]611 FeatureMuxedUnits,
Diana Picusc5baa432016-06-23 07:47:35 +0000[diff] [blame]612 FeatureNEONForFPMovs,
Diana Picus92423ce2016-06-27 09:08:23 +0000[diff] [blame]613 FeatureCheckVLDnAlign,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]614 FeatureMP]>;
Richard Bartonc31078c2013-11-22 11:53:16 +0000[diff] [blame]615
616// FIXME: A12 has currently the same Schedule model as A9
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]617def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]618 FeatureHasRetAddrStack,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]619 FeatureTrustZone,
620 FeatureVMLxForwarding,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]621 FeatureVFP4,
622 FeatureHWDiv,
623 FeatureHWDivARM,
624 FeatureAvoidPartialCPSR,
625 FeatureVirtualization,
626 FeatureMP]>;
Richard Bartonc31078c2013-11-22 11:53:16 +0000[diff] [blame]627
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]628// FIXME: A15 has currently the same Schedule model as A9.
629def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
Diana Picusb772e402016-07-06 11:22:11 +0000[diff] [blame]630 FeatureDontWidenVMOVS,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]631 FeatureHasRetAddrStack,
Diana Picus4879b052016-07-06 09:22:23 +0000[diff] [blame]632 FeatureMuxedUnits,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]633 FeatureTrustZone,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]634 FeatureVFP4,
635 FeatureMP,
Diana Picus92423ce2016-06-27 09:08:23 +0000[diff] [blame]636 FeatureCheckVLDnAlign,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]637 FeatureHWDiv,
638 FeatureHWDivARM,
639 FeatureAvoidPartialCPSR,
640 FeatureVirtualization]>;
Richard Bartonc31078c2013-11-22 11:53:16 +0000[diff] [blame]641
Renato Golin16ea8ba2014-10-13 10:22:19 +0000[diff] [blame]642// FIXME: A17 has currently the same Schedule model as A9
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]643def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]644 FeatureHasRetAddrStack,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]645 FeatureTrustZone,
646 FeatureMP,
647 FeatureVMLxForwarding,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]648 FeatureVFP4,
649 FeatureHWDiv,
650 FeatureHWDivARM,
651 FeatureAvoidPartialCPSR,
652 FeatureVirtualization]>;
Renato Golin16ea8ba2014-10-13 10:22:19 +0000[diff] [blame]653
Tim Northover13510302014-04-01 13:22:02 +0000[diff] [blame]654// FIXME: krait has currently the same Schedule model as A9
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]655// FIXME: krait has currently the same features as A9 plus VFP4 and hardware
656// division features.
657def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]658 FeatureHasRetAddrStack,
Diana Picus4879b052016-07-06 09:22:23 +0000[diff] [blame]659 FeatureMuxedUnits,
Diana Picus92423ce2016-06-27 09:08:23 +0000[diff] [blame]660 FeatureCheckVLDnAlign,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]661 FeatureVMLxForwarding,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]662 FeatureFP16,
663 FeatureAvoidPartialCPSR,
664 FeatureVFP4,
665 FeatureHWDiv,
666 FeatureHWDivARM]>;
667
668def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]669 FeatureHasRetAddrStack,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]670 FeatureNEONForFP,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]671 FeatureVFP4,
672 FeatureMP,
673 FeatureHWDiv,
674 FeatureHWDivARM,
675 FeatureAvoidPartialCPSR,
676 FeatureAvoidMOVsShOp,
Diana Picusc5baa432016-06-23 07:47:35 +0000[diff] [blame]677 FeatureHasSlowFPVMLx,
Diana Picus575f2bb2016-07-07 09:11:39 +0000[diff] [blame]678 FeatureHasVMLxHazards,
Diana Picusc5baa432016-06-23 07:47:35 +0000[diff] [blame]679 FeatureProfUnpredicate,
680 FeaturePrefISHSTBarrier,
Diana Picus4879b052016-07-06 09:22:23 +0000[diff] [blame]681 FeatureSlowOddRegister,
682 FeatureSlowLoadDSubreg,
Diana Picusc5baa432016-06-23 07:47:35 +0000[diff] [blame]683 FeatureSlowVGETLNi32,
684 FeatureSlowVDUP32]>;
Tim Northover13510302014-04-01 13:22:02 +0000[diff] [blame]685
Javed Absar5c5e3c52015-04-09 14:07:28 +0000[diff] [blame]686// FIXME: R4 has currently the same ProcessorModel as A8.
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]687def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]688 FeatureHasRetAddrStack,
Tim Northover554fbd02016-07-19 19:49:13 +0000[diff] [blame]689 FeatureAvoidPartialCPSR]>;
Javed Absar5c5e3c52015-04-09 14:07:28 +0000[diff] [blame]690
691// FIXME: R4F has currently the same ProcessorModel as A8.
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]692def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]693 FeatureHasRetAddrStack,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]694 FeatureSlowFPBrcc,
695 FeatureHasSlowFPVMLx,
696 FeatureVFP3,
697 FeatureD16,
Tim Northover554fbd02016-07-19 19:49:13 +0000[diff] [blame]698 FeatureAvoidPartialCPSR]>;
Javed Absar5c5e3c52015-04-09 14:07:28 +0000[diff] [blame]699
Quentin Colombetb1b66e72012-12-21 04:35:05 +0000[diff] [blame]700// FIXME: R5 has currently the same ProcessorModel as A8.
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]701def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]702 FeatureHasRetAddrStack,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]703 FeatureVFP3,
704 FeatureD16,
705 FeatureSlowFPBrcc,
706 FeatureHWDivARM,
707 FeatureHasSlowFPVMLx,
Tim Northover554fbd02016-07-19 19:49:13 +0000[diff] [blame]708 FeatureAvoidPartialCPSR]>;
Evan Cheng49e02fc2010-08-11 06:30:38 +0000[diff] [blame]709
Bradley Smith26c99222015-02-18 10:33:30 +0000[diff] [blame]710// FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]711def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]712 FeatureHasRetAddrStack,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]713 FeatureVFP3,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]714 FeatureD16,
Bradley Smithd5a1f472015-12-07 10:54:36 +0000[diff] [blame]715 FeatureFP16,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]716 FeatureMP,
717 FeatureSlowFPBrcc,
718 FeatureHWDivARM,
719 FeatureHasSlowFPVMLx,
Tim Northover554fbd02016-07-19 19:49:13 +0000[diff] [blame]720 FeatureAvoidPartialCPSR]>;
Bradley Smith26c99222015-02-18 10:33:30 +0000[diff] [blame]721
Alexandros Lamprineas84316422016-03-10 17:38:41 +0000[diff] [blame]722def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]723 FeatureHasRetAddrStack,
Alexandros Lamprineas84316422016-03-10 17:38:41 +0000[diff] [blame]724 FeatureVFP3,
725 FeatureD16,
726 FeatureFP16,
727 FeatureMP,
728 FeatureSlowFPBrcc,
729 FeatureHWDivARM,
730 FeatureHasSlowFPVMLx,
Tim Northover554fbd02016-07-19 19:49:13 +0000[diff] [blame]731 FeatureAvoidPartialCPSR]>;
Alexandros Lamprineas84316422016-03-10 17:38:41 +0000[diff] [blame]732
Artyom Skrobove6f1b7f2016-03-23 16:18:13 +0000[diff] [blame]733def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>;
734def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>;
Evan Cheng8b2bda02011-07-07 03:55:05 +0000[diff] [blame]735
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]736def : ProcNoItin<"cortex-m4", [ARMv7em,
737 FeatureVFP4,
738 FeatureVFPOnlySP,
739 FeatureD16]>;
740
741def : ProcNoItin<"cortex-m7", [ARMv7em,
742 FeatureFPARMv8,
743 FeatureD16]>;
Oliver Stannard37e4daa2014-10-01 09:02:17 +0000[diff] [blame]744
Renato Golin2b6b7ff2016-03-21 17:29:01 +0000[diff] [blame]745def : ProcNoItin<"cortex-a32", [ARMv8a,
746 FeatureHWDiv,
747 FeatureHWDivARM,
Renato Golin2b6b7ff2016-03-21 17:29:01 +0000[diff] [blame]748 FeatureCrypto,
749 FeatureCRC]>;
Anton Korobeynikov0b91cc42009-05-23 19:51:43 +0000[diff] [blame]750
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]751def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
752 FeatureHWDiv,
753 FeatureHWDivARM,
Christof Douma8b5dc2c2015-12-02 11:53:44 +0000[diff] [blame]754 FeatureCrypto,
755 FeatureCRC]>;
756
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]757def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
758 FeatureHWDiv,
759 FeatureHWDivARM,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]760 FeatureCrypto,
761 FeatureCRC]>;
Bob Wilsone8a549c2012-09-29 21:43:49 +0000[diff] [blame]762
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]763def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
764 FeatureHWDiv,
765 FeatureHWDivARM,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]766 FeatureCrypto,
767 FeatureCRC]>;
768
769def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
770 FeatureHWDiv,
771 FeatureHWDivARM,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]772 FeatureCrypto,
773 FeatureCRC]>;
Joey Goulyb3f550e2013-06-26 16:58:26 +0000[diff] [blame]774
Sjoerd Meijer0b7bb162016-06-02 10:48:52 +0000[diff] [blame]775def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
776 FeatureHWDiv,
777 FeatureHWDivARM,
Sjoerd Meijer0b7bb162016-06-02 10:48:52 +0000[diff] [blame]778 FeatureCrypto,
779 FeatureCRC]>;
780
Tim Northover13510302014-04-01 13:22:02 +0000[diff] [blame]781// Cyclone is very similar to swift
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]782def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
Sjoerd Meijerd906bf12016-06-03 14:03:27 +0000[diff] [blame]783 FeatureHasRetAddrStack,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]784 FeatureNEONForFP,
Bradley Smith323fee12015-11-16 11:10:19 +0000[diff] [blame]785 FeatureVFP4,
786 FeatureMP,
787 FeatureHWDiv,
788 FeatureHWDivARM,
789 FeatureAvoidPartialCPSR,
790 FeatureAvoidMOVsShOp,
791 FeatureHasSlowFPVMLx,
792 FeatureCrypto,
793 FeatureZCZeroing]>;
794
MinSeong Kima7385eb2016-01-05 12:51:59 +0000[diff] [blame]795def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
796 FeatureHWDiv,
797 FeatureHWDivARM,
MinSeong Kima7385eb2016-01-05 12:51:59 +0000[diff] [blame]798 FeatureCrypto,
799 FeatureCRC]>;
Ana Pazos93a07c22013-12-06 22:48:17 +0000[diff] [blame]800
Evandro Menezes82e245a2016-08-01 18:39:45 +0000[diff] [blame]801def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1,
802 FeatureHWDiv,
803 FeatureHWDivARM,
804 FeatureCrypto,
805 FeatureCRC]>;
806
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]807//===----------------------------------------------------------------------===//
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]808// Register File Description
809//===----------------------------------------------------------------------===//
810
811include "ARMRegisterInfo.td"
812
Bob Wilsona4c22902009-04-17 19:07:39 +0000[diff] [blame]813include "ARMCallingConv.td"
814
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]815//===----------------------------------------------------------------------===//
816// Instruction Descriptions
817//===----------------------------------------------------------------------===//
818
819include "ARMInstrInfo.td"
820
Jakob Stoklund Olesenb93331f2010-04-05 03:10:20 +0000[diff] [blame]821def ARMInstrInfo : InstrInfo;
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]822
823//===----------------------------------------------------------------------===//
824// Declare the target which we are implementing
825//===----------------------------------------------------------------------===//
826
Akira Hatanakaee974752015-03-27 23:41:42 +0000[diff] [blame]827def ARMAsmWriter : AsmWriter {
828 string AsmWriterClassName = "InstPrinter";
829 int PassSubtarget = 1;
830 int Variant = 0;
831 bit isMCAsmWriter = 1;
832}
833
Colin LeMahieu8a0453e2015-11-09 00:31:07 +0000[diff] [blame]834def ARMAsmParserVariant : AsmParserVariant {
835 int Variant = 0;
836 string Name = "ARM";
837 string BreakCharacters = ".";
838}
839
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]840def ARM : Target {
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]841 // Pull in Instruction Info:
842 let InstructionSet = ARMInstrInfo;
Akira Hatanakaee974752015-03-27 23:41:42 +0000[diff] [blame]843 let AssemblyWriters = [ARMAsmWriter];
Colin LeMahieu8a0453e2015-11-09 00:31:07 +0000[diff] [blame]844 let AssemblyParserVariants = [ARMAsmParserVariant];
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000[diff] [blame]845}