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gerrit-public.fairphone.software / toolchain / llvm-project / 2e408aefe00b725008bd1f2c185f3c76a9d15c5d / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 038f8d84429157ff2bd500fa4e80831da4e442a2 [file] [log] [blame]
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1// Bitcasts between 512-bit vector types. Return the original type since
2// no instruction is needed for the conversion
3let Predicates = [HasAVX512] in {
4 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
5 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
6 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
7 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
8 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
9 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
10 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
11 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
12 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
13 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
14 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
15 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
16 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
17
18 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
19 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
20 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
21 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
22 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
23 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
24 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
25 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
26 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
27 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
28 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
29 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
30 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
31 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
32 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
33 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
34 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
35 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
36 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
37 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
38 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
39 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
40 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
41 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
42 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
43 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
44 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
45 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
46 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
47 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
48
49// Bitcasts between 256-bit vector types. Return the original type since
50// no instruction is needed for the conversion
51 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
52 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
53 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
54 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
55 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
56 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
57 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
58 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
59 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
60 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
61 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
62 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
63 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
64 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
65 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
66 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
67 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
68 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
69 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
70 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
71 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
72 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
73 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
74 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
75 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
76 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
77 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
78 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
79 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
80 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
81}
82
83//
84// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
85//
86
87let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
88 isPseudo = 1, Predicates = [HasAVX512] in {
89def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
90 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
91}
92
93def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
94def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
95def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
96def : Pat<(v16f32 immAllZerosV), (AVX512_512_SET0)>;
97
98//===----------------------------------------------------------------------===//
99// AVX-512 - VECTOR INSERT
100//
101// -- 32x8 form --
102let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
103def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
104 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
105 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
106 []>, EVEX_4V, EVEX_V512;
107let mayLoad = 1 in
108def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
109 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
110 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
111 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
112}
113
114// -- 64x4 fp form --
115let neverHasSideEffects = 1, ExeDomain = SSEPackedDouble in {
116def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
117 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
118 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
119 []>, EVEX_4V, EVEX_V512, VEX_W;
120let mayLoad = 1 in
121def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
122 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
123 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
124 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
125}
126// -- 32x4 integer form --
127let neverHasSideEffects = 1 in {
128def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
129 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
130 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
131 []>, EVEX_4V, EVEX_V512;
132let mayLoad = 1 in
133def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
134 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
135 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
136 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
137
138}
139
140let neverHasSideEffects = 1 in {
141// -- 64x4 form --
142def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
143 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
144 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
145 []>, EVEX_4V, EVEX_V512, VEX_W;
146let mayLoad = 1 in
147def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
148 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
149 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
150 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
151}
152
153def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
154 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
155 (INSERT_get_vinsert128_imm VR512:$ins))>;
156def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
157 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
158 (INSERT_get_vinsert128_imm VR512:$ins))>;
159def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
160 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
161 (INSERT_get_vinsert128_imm VR512:$ins))>;
162def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
163 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
164 (INSERT_get_vinsert128_imm VR512:$ins))>;
165
166def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
167 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
168 (INSERT_get_vinsert128_imm VR512:$ins))>;
169def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
170 (bc_v4i32 (loadv2i64 addr:$src2)),
171 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
172 (INSERT_get_vinsert128_imm VR512:$ins))>;
173def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
174 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
175 (INSERT_get_vinsert128_imm VR512:$ins))>;
176def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
177 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
178 (INSERT_get_vinsert128_imm VR512:$ins))>;
179
180def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
181 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
182 (INSERT_get_vinsert256_imm VR512:$ins))>;
183def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
184 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
185 (INSERT_get_vinsert256_imm VR512:$ins))>;
186def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
187 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
188 (INSERT_get_vinsert256_imm VR512:$ins))>;
189def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
190 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
191 (INSERT_get_vinsert256_imm VR512:$ins))>;
192
193def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
194 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
195 (INSERT_get_vinsert256_imm VR512:$ins))>;
196def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
197 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
198 (INSERT_get_vinsert256_imm VR512:$ins))>;
199def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
200 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
201 (INSERT_get_vinsert256_imm VR512:$ins))>;
202def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
203 (bc_v8i32 (loadv4i64 addr:$src2)),
204 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
205 (INSERT_get_vinsert256_imm VR512:$ins))>;
206
207// vinsertps - insert f32 to XMM
208def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
209 (ins VR128X:$src1, VR128X:$src2, u32u8imm:$src3),
210 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
211 [(set VR128X:$dst, (X86insrtps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
212 EVEX_4V;
213def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
214 (ins VR128X:$src1, f32mem:$src2, u32u8imm:$src3),
215 "vinsertps{z}\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
216 [(set VR128X:$dst, (X86insrtps VR128X:$src1,
217 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
218 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
219
220//===----------------------------------------------------------------------===//
221// AVX-512 VECTOR EXTRACT
222//---
223let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
224// -- 32x4 form --
225def VEXTRACTF32x4rr : AVX512AIi8<0x19, MRMDestReg, (outs VR128X:$dst),
226 (ins VR512:$src1, i8imm:$src2),
227 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
228 []>, EVEX, EVEX_V512;
229def VEXTRACTF32x4mr : AVX512AIi8<0x19, MRMDestMem, (outs),
230 (ins f128mem:$dst, VR512:$src1, i8imm:$src2),
231 "vextractf32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
232 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
233
234// -- 64x4 form --
235def VEXTRACTF64x4rr : AVX512AIi8<0x1b, MRMDestReg, (outs VR256X:$dst),
236 (ins VR512:$src1, i8imm:$src2),
237 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
238 []>, EVEX, EVEX_V512, VEX_W;
239let mayStore = 1 in
240def VEXTRACTF64x4mr : AVX512AIi8<0x1b, MRMDestMem, (outs),
241 (ins f256mem:$dst, VR512:$src1, i8imm:$src2),
242 "vextractf64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
243 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
244}
245
246let neverHasSideEffects = 1 in {
247// -- 32x4 form --
248def VEXTRACTI32x4rr : AVX512AIi8<0x39, MRMDestReg, (outs VR128X:$dst),
249 (ins VR512:$src1, i8imm:$src2),
250 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
251 []>, EVEX, EVEX_V512;
252def VEXTRACTI32x4mr : AVX512AIi8<0x39, MRMDestMem, (outs),
253 (ins i128mem:$dst, VR512:$src1, i8imm:$src2),
254 "vextracti32x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
255 []>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VT4>;
256
257// -- 64x4 form --
258def VEXTRACTI64x4rr : AVX512AIi8<0x3b, MRMDestReg, (outs VR256X:$dst),
259 (ins VR512:$src1, i8imm:$src2),
260 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
261 []>, EVEX, EVEX_V512, VEX_W;
262let mayStore = 1 in
263def VEXTRACTI64x4mr : AVX512AIi8<0x3b, MRMDestMem, (outs),
264 (ins i256mem:$dst, VR512:$src1, i8imm:$src2),
265 "vextracti64x4\t{$src2, $src1, $dst|$dst, $src1, $src2}",
266 []>, EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
267}
268
269def : Pat<(vextract128_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
270 (v4f32 (VEXTRACTF32x4rr VR512:$src1,
271 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
272
273def : Pat<(vextract128_extract:$ext VR512:$src1, (iPTR imm)),
274 (v4i32 (VEXTRACTF32x4rr VR512:$src1,
275 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
276
277def : Pat<(vextract128_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
278 (v2f64 (VEXTRACTF32x4rr VR512:$src1,
279 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
280
281def : Pat<(vextract128_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
282 (v2i64 (VEXTRACTI32x4rr VR512:$src1,
283 (EXTRACT_get_vextract128_imm VR128X:$ext)))>;
284
285
286def : Pat<(vextract256_extract:$ext (v16f32 VR512:$src1), (iPTR imm)),
287 (v8f32 (VEXTRACTF64x4rr VR512:$src1,
288 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
289
290def : Pat<(vextract256_extract:$ext (v16i32 VR512:$src1), (iPTR imm)),
291 (v8i32 (VEXTRACTI64x4rr VR512:$src1,
292 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
293
294def : Pat<(vextract256_extract:$ext (v8f64 VR512:$src1), (iPTR imm)),
295 (v4f64 (VEXTRACTF64x4rr VR512:$src1,
296 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
297
298def : Pat<(vextract256_extract:$ext (v8i64 VR512:$src1), (iPTR imm)),
299 (v4i64 (VEXTRACTI64x4rr VR512:$src1,
300 (EXTRACT_get_vextract256_imm VR256X:$ext)))>;
301
302// A 256-bit subvector extract from the first 512-bit vector position
303// is a subregister copy that needs no instruction.
304def : Pat<(v8i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
305 (v8i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_ymm))>;
306def : Pat<(v8f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
307 (v8f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_ymm))>;
308def : Pat<(v4i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
309 (v4i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_ymm))>;
310def : Pat<(v4f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
311 (v4f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_ymm))>;
312
313// zmm -> xmm
314def : Pat<(v4i32 (extract_subvector (v16i32 VR512:$src), (iPTR 0))),
315 (v4i32 (EXTRACT_SUBREG (v16i32 VR512:$src), sub_xmm))>;
316def : Pat<(v2i64 (extract_subvector (v8i64 VR512:$src), (iPTR 0))),
317 (v2i64 (EXTRACT_SUBREG (v8i64 VR512:$src), sub_xmm))>;
318def : Pat<(v2f64 (extract_subvector (v8f64 VR512:$src), (iPTR 0))),
319 (v2f64 (EXTRACT_SUBREG (v8f64 VR512:$src), sub_xmm))>;
320def : Pat<(v4f32 (extract_subvector (v16f32 VR512:$src), (iPTR 0))),
321 (v4f32 (EXTRACT_SUBREG (v16f32 VR512:$src), sub_xmm))>;
322
323
324// A 128-bit subvector insert to the first 512-bit vector position
325// is a subregister copy that needs no instruction.
326def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
327 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
328 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
329 sub_ymm)>;
330def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
331 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
332 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
333 sub_ymm)>;
334def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
335 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
336 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
337 sub_ymm)>;
338def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
339 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
340 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
341 sub_ymm)>;
342
343def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
344 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
345def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
346 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
347def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
348 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
349def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
350 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
351
352// vextractps - extract 32 bits from XMM
353def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
354 (ins VR128X:$src1, u32u8imm:$src2),
355 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
356 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
357 EVEX;
358
359def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
360 (ins f32mem:$dst, VR128X:$src1, u32u8imm:$src2),
361 "vextractps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
362 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
363 addr:$dst)]>, EVEX;
364
365//===---------------------------------------------------------------------===//
366// AVX-512 BROADCAST
367//---
368multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
369 RegisterClass DestRC,
370 RegisterClass SrcRC, X86MemOperand x86memop> {
371 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
372 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
373 []>, EVEX;
374 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
375 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),[]>, EVEX;
376}
377let ExeDomain = SSEPackedSingle in {
378 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss{z}", VR512,
379 VR128X, f32mem>,
380 EVEX_V512, EVEX_CD8<32, CD8VT1>;
381}
382
383let ExeDomain = SSEPackedDouble in {
384 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd{z}", VR512,
385 VR128X, f64mem>,
386 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
387}
388
389def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
390 (VBROADCASTSSZrm addr:$src)>;
391def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
392 (VBROADCASTSDZrm addr:$src)>;
393
394multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
395 RegisterClass SrcRC, RegisterClass KRC> {
396 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
397 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
398 []>, EVEX, EVEX_V512;
399 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
400 (ins KRC:$mask, SrcRC:$src),
401 !strconcat(OpcodeStr,
402 "\t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
403 []>, EVEX, EVEX_V512, EVEX_KZ;
404}
405
406defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
407defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
408 VEX_W;
409
410def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
411 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
412
413def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
414 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
415
416def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
417 (VPBROADCASTDrZrr GR32:$src)>;
418def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
419 (VPBROADCASTQrZrr GR64:$src)>;
420
421multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
422 X86MemOperand x86memop, PatFrag ld_frag,
423 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
424 RegisterClass KRC> {
425 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
426 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
427 [(set DstRC:$dst,
428 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
429 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
430 VR128X:$src),
431 !strconcat(OpcodeStr,
432 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
433 [(set DstRC:$dst,
434 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
435 EVEX, EVEX_KZ;
436 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
437 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
438 [(set DstRC:$dst,
439 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
440 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
441 x86memop:$src),
442 !strconcat(OpcodeStr,
443 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
444 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
445 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
446}
447
448defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
449 loadi32, VR512, v16i32, v4i32, VK16WM>,
450 EVEX_V512, EVEX_CD8<32, CD8VT1>;
451defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
452 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
453 EVEX_CD8<64, CD8VT1>;
454
455def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
456 (VBROADCASTSSZrr VR128X:$src)>;
457def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
458 (VBROADCASTSDZrr VR128X:$src)>;
459
460// Provide fallback in case the load node that is used in the patterns above
461// is used by additional users, which prevents the pattern selection.
462def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
463 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
464def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
465 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
466
467
468let Predicates = [HasAVX512] in {
469def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
470 (EXTRACT_SUBREG
471 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
472 addr:$src)), sub_ymm)>;
473}
474//===----------------------------------------------------------------------===//
475// AVX-512 BROADCAST MASK TO VECTOR REGISTER
476//---
477
478multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
479 RegisterClass DstRC, RegisterClass KRC,
480 ValueType OpVT, ValueType SrcVT> {
481def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
482 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
483 []>, EVEX;
484}
485
486defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
487 VK16, v16i32, v16i1>, EVEX_V512;
488defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
489 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
490
491//===----------------------------------------------------------------------===//
492// AVX-512 - VPERM
493//
494// -- immediate form --
495multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
496 SDNode OpNode, PatFrag mem_frag,
497 X86MemOperand x86memop, ValueType OpVT> {
498 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
499 (ins RC:$src1, i8imm:$src2),
500 !strconcat(OpcodeStr,
501 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
502 [(set RC:$dst,
503 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
504 EVEX;
505 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
506 (ins x86memop:$src1, i8imm:$src2),
507 !strconcat(OpcodeStr,
508 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
509 [(set RC:$dst,
510 (OpVT (OpNode (mem_frag addr:$src1),
511 (i8 imm:$src2))))]>, EVEX;
512}
513
514defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
515 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
516let ExeDomain = SSEPackedDouble in
517defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
518 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
519
520// -- VPERM - register form --
521multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
522 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
523
524 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
525 (ins RC:$src1, RC:$src2),
526 !strconcat(OpcodeStr,
527 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
528 [(set RC:$dst,
529 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
530
531 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
532 (ins RC:$src1, x86memop:$src2),
533 !strconcat(OpcodeStr,
534 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
535 [(set RC:$dst,
536 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
537 EVEX_4V;
538}
539
540defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
541 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
542defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
543 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
544let ExeDomain = SSEPackedSingle in
545defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
546 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
547let ExeDomain = SSEPackedDouble in
548defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
549 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
550
551// -- VPERM2I - 3 source operands form --
552multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
553 PatFrag mem_frag, X86MemOperand x86memop,
554 ValueType OpVT> {
555let Constraints = "$src1 = $dst" in {
556 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
557 (ins RC:$src1, RC:$src2, RC:$src3),
558 !strconcat(OpcodeStr,
559 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
560 [(set RC:$dst,
561 (OpVT (X86VPermv3 RC:$src1, RC:$src2, RC:$src3)))]>,
562 EVEX_4V;
563
564 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
565 (ins RC:$src1, RC:$src2, x86memop:$src3),
566 !strconcat(OpcodeStr,
567 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
568 [(set RC:$dst,
569 (OpVT (X86VPermv3 RC:$src1, RC:$src2,
570 (mem_frag addr:$src3))))]>, EVEX_4V;
571 }
572}
573defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32, i512mem,
574 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
575defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64, i512mem,
576 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
577defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32, i512mem,
578 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
579defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64, i512mem,
580 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
581
582//===----------------------------------------------------------------------===//
583// AVX-512 - BLEND using mask
584//
585multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
586 RegisterClass KRC, RegisterClass RC,
587 X86MemOperand x86memop, PatFrag mem_frag,
588 SDNode OpNode, ValueType vt> {
589 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
590 (ins KRC:$mask, RC:$src1, RC:$src2),
591 !strconcat(OpcodeStr,
592 "\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
593 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
594 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
595
596 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
597 (ins KRC:$mask, RC:$src1, x86memop:$src2),
598 !strconcat(OpcodeStr,
599 "\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
600 []>,
601 EVEX_4V, EVEX_K;
602}
603
604let ExeDomain = SSEPackedSingle in
605defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps", VK16WM, VR512, f512mem,
606 memopv16f32, vselect, v16f32>,
607 EVEX_CD8<32, CD8VF>, EVEX_V512;
608let ExeDomain = SSEPackedDouble in
609defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd", VK8WM, VR512, f512mem,
610 memopv8f64, vselect, v8f64>,
611 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
612
613defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd", VK16WM, VR512, f512mem,
614 memopv8i64, vselect, v16i32>,
615 EVEX_CD8<32, CD8VF>, EVEX_V512;
616
617defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq", VK8WM, VR512, f512mem,
618 memopv8i64, vselect, v8i64>, VEX_W,
619 EVEX_CD8<64, CD8VF>, EVEX_V512;
620
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]621let Predicates = [HasAVX512] in {
622def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
623 (v8f32 VR256X:$src2))),
624 (EXTRACT_SUBREG
625 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
626 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
627 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
628
629def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
630 (v8i32 VR256X:$src2))),
631 (EXTRACT_SUBREG
632 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
633 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
634 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
635}
636
637multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, RegisterClass KRC,
638 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
639 SDNode OpNode, ValueType vt> {
640 def rr : AVX512BI<opc, MRMSrcReg,
641 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
642 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
643 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
644 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
645 def rm : AVX512BI<opc, MRMSrcMem,
646 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
647 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
648 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2)))],
649 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
650}
651
652defm VPCMPEQDZ : avx512_icmp_packed<0x76, "vpcmpeqd", VK16, VR512, i512mem,
653 memopv16i32, X86pcmpeqm, v16i32>, EVEX_V512;
654defm VPCMPEQQZ : avx512_icmp_packed<0x29, "vpcmpeqq", VK8, VR512, i512mem,
655 memopv8i64, X86pcmpeqm, v8i64>, T8, EVEX_V512, VEX_W;
656
657defm VPCMPGTDZ : avx512_icmp_packed<0x66, "vpcmpgtd", VK16, VR512, i512mem,
658 memopv16i32, X86pcmpgtm, v16i32>, EVEX_V512;
659defm VPCMPGTQZ : avx512_icmp_packed<0x37, "vpcmpgtq", VK8, VR512, i512mem,
660 memopv8i64, X86pcmpgtm, v8i64>, T8, EVEX_V512, VEX_W;
661
662def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
663 (COPY_TO_REGCLASS (VPCMPGTDZrr
664 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
665 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
666
667def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
668 (COPY_TO_REGCLASS (VPCMPEQDZrr
669 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
670 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
671
672multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
673 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
674 SDNode OpNode, ValueType vt, Operand CC, string asm,
675 string asm_alt> {
676 def rri : AVX512AIi8<opc, MRMSrcReg,
677 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
678 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))],
679 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
680 def rmi : AVX512AIi8<opc, MRMSrcMem,
681 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
682 [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
683 imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
684 // Accept explicit immediate argument form instead of comparison code.
685 let neverHasSideEffects = 1 in {
686 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
687 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
688 asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
689 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
690 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
691 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
692 }
693}
694
695defm VPCMPDZ : avx512_icmp_cc<0x1F, VK16, VR512, i512mem, memopv16i32,
696 X86cmpm, v16i32, AVXCC,
697 "vpcmp${cc}d\t{$src2, $src1, $dst|$dst, $src1, $src2}",
698 "vpcmpd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
699 EVEX_V512, EVEX_CD8<32, CD8VF>;
700defm VPCMPUDZ : avx512_icmp_cc<0x1E, VK16, VR512, i512mem, memopv16i32,
701 X86cmpmu, v16i32, AVXCC,
702 "vpcmp${cc}ud\t{$src2, $src1, $dst|$dst, $src1, $src2}",
703 "vpcmpud\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
704 EVEX_V512, EVEX_CD8<32, CD8VF>;
705
706defm VPCMPQZ : avx512_icmp_cc<0x1F, VK8, VR512, i512mem, memopv8i64,
707 X86cmpm, v8i64, AVXCC,
708 "vpcmp${cc}q\t{$src2, $src1, $dst|$dst, $src1, $src2}",
709 "vpcmpq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
710 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
711defm VPCMPUQZ : avx512_icmp_cc<0x1E, VK8, VR512, i512mem, memopv8i64,
712 X86cmpmu, v8i64, AVXCC,
713 "vpcmp${cc}uq\t{$src2, $src1, $dst|$dst, $src1, $src2}",
714 "vpcmpuq\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
715 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
716
717// avx512_cmp_packed - sse 1 & 2 compare packed instructions
718multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
719 X86MemOperand x86memop, Operand CC,
720 SDNode OpNode, ValueType vt, string asm,
721 string asm_alt, Domain d> {
722 def rri : AVX512PIi8<0xC2, MRMSrcReg,
723 (outs KRC:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
724 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
725 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
726 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
727 [(set KRC:$dst,
728 (OpNode (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
729
730 // Accept explicit immediate argument form instead of comparison code.
731 let neverHasSideEffects = 1 in {
732 def rri_alt : PIi8<0xC2, MRMSrcReg,
733 (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
734 asm_alt, [], IIC_SSE_ALU_F32P_RR, d>;
735 def rmi_alt : PIi8<0xC2, MRMSrcMem,
736 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
737 asm_alt, [], IIC_SSE_ALU_F32P_RM, d>;
738 }
739}
740
741defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, AVXCC, X86cmpm, v16f32,
742 "vcmp${cc}ps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
743 "vcmpps\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]744 SSEPackedSingle>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]745defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, AVXCC, X86cmpm, v8f64,
746 "vcmp${cc}pd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
747 "vcmppd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}",
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]748 SSEPackedDouble>, OpSize, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]749 EVEX_CD8<64, CD8VF>;
750
751def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
752 (COPY_TO_REGCLASS (VCMPPSZrri
753 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
754 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
755 imm:$cc), VK8)>;
756def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
757 (COPY_TO_REGCLASS (VPCMPDZrri
758 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
759 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
760 imm:$cc), VK8)>;
761def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
762 (COPY_TO_REGCLASS (VPCMPUDZrri
763 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
764 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
765 imm:$cc), VK8)>;
766
767// Mask register copy, including
768// - copy between mask registers
769// - load/store mask registers
770// - copy from GPR to mask register and vice versa
771//
772multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
773 string OpcodeStr, RegisterClass KRC,
774 ValueType vt, X86MemOperand x86memop> {
775 let neverHasSideEffects = 1 in {
776 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
777 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
778 let mayLoad = 1 in
779 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
780 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
781 [(set KRC:$dst, (vt (load addr:$src)))]>;
782 let mayStore = 1 in
783 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
784 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
785 }
786}
787
788multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
789 string OpcodeStr,
790 RegisterClass KRC, RegisterClass GRC> {
791 let neverHasSideEffects = 1 in {
792 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
793 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
794 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
795 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>;
796 }
797}
798
799let Predicates = [HasAVX512] in {
800 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
801 VEX, TB;
802 defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
803 VEX, TB;
804}
805
806let Predicates = [HasAVX512] in {
807 // GR16 from/to 16-bit mask
808 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
809 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
810 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
811 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
812
813 // Store kreg in memory
814 def : Pat<(store (v16i1 VK16:$src), addr:$dst),
815 (KMOVWmk addr:$dst, VK16:$src)>;
816
817 def : Pat<(store (v8i1 VK8:$src), addr:$dst),
818 (KMOVWmk addr:$dst, (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16)))>;
819}
820// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
821let Predicates = [HasAVX512] in {
822 // GR from/to 8-bit mask without native support
823 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
824 (COPY_TO_REGCLASS
825 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
826 VK8)>;
827 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
828 (EXTRACT_SUBREG
829 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
830 sub_8bit)>;
831}
832
833// Mask unary operation
834// - KNOT
835multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
836 RegisterClass KRC, SDPatternOperator OpNode> {
837 let Predicates = [HasAVX512] in
838 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
839 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
840 [(set KRC:$dst, (OpNode KRC:$src))]>;
841}
842
843multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
844 SDPatternOperator OpNode> {
845 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
846 VEX, TB;
847}
848
849defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
850
851def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
852def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
853 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
854
855// With AVX-512, 8-bit mask is promoted to 16-bit mask.
856def : Pat<(not VK8:$src),
857 (COPY_TO_REGCLASS
858 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
859
860// Mask binary operation
861// - KADD, KAND, KANDN, KOR, KXNOR, KXOR
862multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
863 RegisterClass KRC, SDPatternOperator OpNode> {
864 let Predicates = [HasAVX512] in
865 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
866 !strconcat(OpcodeStr,
867 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
868 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
869}
870
871multiclass avx512_mask_binop_w<bits<8> opc, string OpcodeStr,
872 SDPatternOperator OpNode> {
873 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
874 VEX_4V, VEX_L, TB;
875}
876
877def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
878def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
879
880let isCommutable = 1 in {
881 defm KADD : avx512_mask_binop_w<0x4a, "kadd", add>;
882 defm KAND : avx512_mask_binop_w<0x41, "kand", and>;
883 let isCommutable = 0 in
884 defm KANDN : avx512_mask_binop_w<0x42, "kandn", andn>;
885 defm KOR : avx512_mask_binop_w<0x45, "kor", or>;
886 defm KXNOR : avx512_mask_binop_w<0x46, "kxnor", xnor>;
887 defm KXOR : avx512_mask_binop_w<0x47, "kxor", xor>;
888}
889
890multiclass avx512_mask_binop_int<string IntName, string InstName> {
891 let Predicates = [HasAVX512] in
892 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
893 VK16:$src1, VK16:$src2),
894 (!cast<Instruction>(InstName##"Wrr") VK16:$src1, VK16:$src2)>;
895}
896
897defm : avx512_mask_binop_int<"kadd", "KADD">;
898defm : avx512_mask_binop_int<"kand", "KAND">;
899defm : avx512_mask_binop_int<"kandn", "KANDN">;
900defm : avx512_mask_binop_int<"kor", "KOR">;
901defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
902defm : avx512_mask_binop_int<"kxor", "KXOR">;
903// With AVX-512, 8-bit mask is promoted to 16-bit mask.
904multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
905 let Predicates = [HasAVX512] in
906 def : Pat<(OpNode VK8:$src1, VK8:$src2),
907 (COPY_TO_REGCLASS
908 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
909 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
910}
911
912defm : avx512_binop_pat<and, KANDWrr>;
913defm : avx512_binop_pat<andn, KANDNWrr>;
914defm : avx512_binop_pat<or, KORWrr>;
915defm : avx512_binop_pat<xnor, KXNORWrr>;
916defm : avx512_binop_pat<xor, KXORWrr>;
917
918// Mask unpacking
919multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
920 RegisterClass KRC1, RegisterClass KRC2> {
921 let Predicates = [HasAVX512] in
922 def rr : I<opc, MRMSrcReg, (outs KRC1:$dst), (ins KRC2:$src1, KRC2:$src2),
923 !strconcat(OpcodeStr,
924 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
925}
926
927multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
928 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16, VK8>,
929 VEX_4V, VEX_L, OpSize, TB;
930}
931
932defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
933
934multiclass avx512_mask_unpck_int<string IntName, string InstName> {
935 let Predicates = [HasAVX512] in
936 def : Pat<(!cast<Intrinsic>("int_x86_"##IntName##"_v16i1")
937 VK8:$src1, VK8:$src2),
938 (!cast<Instruction>(InstName##"BWrr") VK8:$src1, VK8:$src2)>;
939}
940
941defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
942// Mask bit testing
943multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
944 SDNode OpNode> {
945 let Predicates = [HasAVX512], Defs = [EFLAGS] in
946 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
947 !strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
948 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
949}
950
951multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
952 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
953 VEX, TB;
954}
955
956defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
957defm KTEST : avx512_mask_testop_w<0x99, "ktest", X86ktest>;
958
959// Mask shift
960multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
961 SDNode OpNode> {
962 let Predicates = [HasAVX512] in
963 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
964 !strconcat(OpcodeStr,
965 "\t{$imm, $src, $dst|$dst, $src, $imm}"),
966 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
967}
968
969multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
970 SDNode OpNode> {
971 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
972 VEX, OpSize, TA, VEX_W;
973}
974
975defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", shl>;
976defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", srl>;
977
978// Mask setting all 0s or 1s
979multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
980 let Predicates = [HasAVX512] in
981 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
982 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
983 [(set KRC:$dst, (VT Val))]>;
984}
985
986multiclass avx512_mask_setop_w<PatFrag Val> {
987 defm B : avx512_mask_setop<VK8, v8i1, Val>;
988 defm W : avx512_mask_setop<VK16, v16i1, Val>;
989}
990
991defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
992defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
993
994// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
995let Predicates = [HasAVX512] in {
996 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
997 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
998}
999def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1000 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1001
1002def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1003 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1004
1005def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1006 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1007
1008//===----------------------------------------------------------------------===//
1009// AVX-512 - Aligned and unaligned load and store
1010//
1011
1012multiclass avx512_mov_packed<bits<8> opc, RegisterClass RC, RegisterClass KRC,
1013 X86MemOperand x86memop, PatFrag ld_frag,
1014 string asm, Domain d> {
1015let neverHasSideEffects = 1 in
1016 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1017 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [], d>,
1018 EVEX;
1019let canFoldAsLoad = 1 in
1020 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1021 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1022 [(set RC:$dst, (ld_frag addr:$src))], d>, EVEX;
1023let Constraints = "$src1 = $dst" in {
1024 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1025 (ins RC:$src1, KRC:$mask, RC:$src2),
1026 !strconcat(asm,
1027 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
1028 EVEX, EVEX_K;
1029 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1030 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1031 !strconcat(asm,
1032 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1033 [], d>, EVEX, EVEX_K;
1034}
1035}
1036
1037defm VMOVAPSZ : avx512_mov_packed<0x28, VR512, VK16WM, f512mem, alignedloadv16f32,
1038 "vmovaps", SSEPackedSingle>,
1039 EVEX_V512, EVEX_CD8<32, CD8VF>;
1040defm VMOVAPDZ : avx512_mov_packed<0x28, VR512, VK8WM, f512mem, alignedloadv8f64,
1041 "vmovapd", SSEPackedDouble>,
1042 OpSize, EVEX_V512, VEX_W,
1043 EVEX_CD8<64, CD8VF>;
1044defm VMOVUPSZ : avx512_mov_packed<0x10, VR512, VK16WM, f512mem, loadv16f32,
1045 "vmovups", SSEPackedSingle>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1046 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1047defm VMOVUPDZ : avx512_mov_packed<0x10, VR512, VK8WM, f512mem, loadv8f64,
1048 "vmovupd", SSEPackedDouble>,
1049 OpSize, EVEX_V512, VEX_W,
1050 EVEX_CD8<64, CD8VF>;
1051def VMOVAPSZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1052 "vmovaps\t{$src, $dst|$dst, $src}",
1053 [(alignedstore512 (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1054 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1055def VMOVAPDZmr : AVX512PI<0x29, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1056 "vmovapd\t{$src, $dst|$dst, $src}",
1057 [(alignedstore512 (v8f64 VR512:$src), addr:$dst)],
1058 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1059 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1060def VMOVUPSZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1061 "vmovups\t{$src, $dst|$dst, $src}",
1062 [(store (v16f32 VR512:$src), addr:$dst)],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1063 SSEPackedSingle>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1064def VMOVUPDZmr : AVX512PI<0x11, MRMDestMem, (outs), (ins f512mem:$dst, VR512:$src),
1065 "vmovupd\t{$src, $dst|$dst, $src}",
1066 [(store (v8f64 VR512:$src), addr:$dst)],
1067 SSEPackedDouble>, EVEX, EVEX_V512,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1068 OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1069
1070// Use vmovaps/vmovups for AVX-512 integer load/store.
1071// 512-bit load/store
1072def : Pat<(alignedloadv8i64 addr:$src),
1073 (VMOVAPSZrm addr:$src)>;
1074def : Pat<(loadv8i64 addr:$src),
1075 (VMOVUPSZrm addr:$src)>;
1076
1077def : Pat<(alignedstore512 (v8i64 VR512:$src), addr:$dst),
1078 (VMOVAPSZmr addr:$dst, VR512:$src)>;
1079def : Pat<(alignedstore512 (v16i32 VR512:$src), addr:$dst),
1080 (VMOVAPSZmr addr:$dst, VR512:$src)>;
1081
1082def : Pat<(store (v8i64 VR512:$src), addr:$dst),
1083 (VMOVUPDZmr addr:$dst, VR512:$src)>;
1084def : Pat<(store (v16i32 VR512:$src), addr:$dst),
1085 (VMOVUPSZmr addr:$dst, VR512:$src)>;
1086
1087let neverHasSideEffects = 1 in {
1088 def VMOVDQA32rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1089 (ins VR512:$src),
1090 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1091 EVEX, EVEX_V512;
1092 def VMOVDQA64rr : AVX512BI<0x6F, MRMSrcReg, (outs VR512:$dst),
1093 (ins VR512:$src),
1094 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1095 EVEX, EVEX_V512, VEX_W;
1096let mayStore = 1 in {
1097 def VMOVDQA32mr : AVX512BI<0x7F, MRMDestMem, (outs),
1098 (ins i512mem:$dst, VR512:$src),
1099 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1100 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1101 def VMOVDQA64mr : AVX512BI<0x7F, MRMDestMem, (outs),
1102 (ins i512mem:$dst, VR512:$src),
1103 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1104 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1105}
1106let mayLoad = 1 in {
1107def VMOVDQA32rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1108 (ins i512mem:$src),
1109 "vmovdqa32\t{$src, $dst|$dst, $src}", []>,
1110 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
1111def VMOVDQA64rm : AVX512BI<0x6F, MRMSrcMem, (outs VR512:$dst),
1112 (ins i512mem:$src),
1113 "vmovdqa64\t{$src, $dst|$dst, $src}", []>,
1114 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1115}
1116}
1117
1118multiclass avx512_mov_int<bits<8> opc, string asm, RegisterClass RC,
1119 RegisterClass KRC,
1120 PatFrag ld_frag, X86MemOperand x86memop> {
1121let neverHasSideEffects = 1 in
1122 def rr : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1123 !strconcat(asm, "\t{$src, $dst|$dst, $src}"), []>,
1124 EVEX;
1125let canFoldAsLoad = 1 in
1126 def rm : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1127 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1128 [(set RC:$dst, (ld_frag addr:$src))]>,
1129 EVEX;
1130let Constraints = "$src1 = $dst" in {
1131 def rrk : AVX512XSI<opc, MRMSrcReg, (outs RC:$dst),
1132 (ins RC:$src1, KRC:$mask, RC:$src2),
1133 !strconcat(asm,
1134 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), []>,
1135 EVEX, EVEX_K;
1136 def rmk : AVX512XSI<opc, MRMSrcMem, (outs RC:$dst),
1137 (ins RC:$src1, KRC:$mask, x86memop:$src2),
1138 !strconcat(asm,
1139 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
1140 []>, EVEX, EVEX_K;
1141}
1142}
1143
1144defm VMOVDQU32 : avx512_mov_int<0x6F, "vmovdqu32", VR512, VK16WM, memopv16i32, i512mem>,
1145 EVEX_V512, EVEX_CD8<32, CD8VF>;
1146defm VMOVDQU64 : avx512_mov_int<0x6F, "vmovdqu64", VR512, VK8WM, memopv8i64, i512mem>,
1147 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1148
1149let AddedComplexity = 20 in {
1150def : Pat<(v16f32 (vselect VK16WM:$mask, (v16f32 VR512:$src1),
1151 (v16f32 VR512:$src2))),
1152 (VMOVUPSZrrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1153def : Pat<(v8f64 (vselect VK8WM:$mask, (v8f64 VR512:$src1),
1154 (v8f64 VR512:$src2))),
1155 (VMOVUPDZrrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1156def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src1),
1157 (v16i32 VR512:$src2))),
1158 (VMOVDQU32rrk VR512:$src2, VK16WM:$mask, VR512:$src1)>;
1159def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src1),
1160 (v8i64 VR512:$src2))),
1161 (VMOVDQU64rrk VR512:$src2, VK8WM:$mask, VR512:$src1)>;
1162}
1163// Move Int Doubleword to Packed Double Int
1164//
1165def VMOVDI2PDIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
1166 "vmovd{z}\t{$src, $dst|$dst, $src}",
1167 [(set VR128X:$dst,
1168 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
1169 EVEX, VEX_LIG;
1170def VMOVDI2PDIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
1171 "vmovd{z}\t{$src, $dst|$dst, $src}",
1172 [(set VR128X:$dst,
1173 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
1174 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1175def VMOV64toPQIZrr : AVX512SI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
1176 "vmovq{z}\t{$src, $dst|$dst, $src}",
1177 [(set VR128X:$dst,
1178 (v2i64 (scalar_to_vector GR64:$src)))],
1179 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
1180def VMOV64toSDZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
1181 "vmovq{z}\t{$src, $dst|$dst, $src}",
1182 [(set FR64:$dst, (bitconvert GR64:$src))],
1183 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1184def VMOVSDto64Zrr : AVX512SI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
1185 "vmovq{z}\t{$src, $dst|$dst, $src}",
1186 [(set GR64:$dst, (bitconvert FR64:$src))],
1187 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
1188def VMOVSDto64Zmr : AVX512SI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
1189 "vmovq{z}\t{$src, $dst|$dst, $src}",
1190 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
1191 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
1192 EVEX_CD8<64, CD8VT1>;
1193
1194// Move Int Doubleword to Single Scalar
1195//
1196def VMOVDI2SSZrr : AVX512SI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
1197 "vmovd{z}\t{$src, $dst|$dst, $src}",
1198 [(set FR32X:$dst, (bitconvert GR32:$src))],
1199 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
1200
1201def VMOVDI2SSZrm : AVX512SI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
1202 "vmovd{z}\t{$src, $dst|$dst, $src}",
1203 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
1204 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1205
1206// Move Packed Doubleword Int to Packed Double Int
1207//
1208def VMOVPDI2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
1209 "vmovd{z}\t{$src, $dst|$dst, $src}",
1210 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
1211 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
1212 EVEX, VEX_LIG;
1213def VMOVPDI2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1214 (ins i32mem:$dst, VR128X:$src),
1215 "vmovd{z}\t{$src, $dst|$dst, $src}",
1216 [(store (i32 (vector_extract (v4i32 VR128X:$src),
1217 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
1218 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1219
1220// Move Packed Doubleword Int first element to Doubleword Int
1221//
1222def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
1223 "vmovq{z}\t{$src, $dst|$dst, $src}",
1224 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
1225 (iPTR 0)))],
1226 IIC_SSE_MOVD_ToGP>, TB, OpSize, EVEX, VEX_LIG, VEX_W,
1227 Requires<[HasAVX512, In64BitMode]>;
1228
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1229def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1230 (ins i64mem:$dst, VR128X:$src),
1231 "vmovq{z}\t{$src, $dst|$dst, $src}",
1232 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
1233 addr:$dst)], IIC_SSE_MOVDQ>,
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1234 EVEX, OpSize, VEX_LIG, VEX_W, TB, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1235 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
1236
1237// Move Scalar Single to Double Int
1238//
1239def VMOVSS2DIZrr : AVX512SI<0x7E, MRMDestReg, (outs GR32:$dst),
1240 (ins FR32X:$src),
1241 "vmovd{z}\t{$src, $dst|$dst, $src}",
1242 [(set GR32:$dst, (bitconvert FR32X:$src))],
1243 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
1244def VMOVSS2DIZmr : AVX512SI<0x7E, MRMDestMem, (outs),
1245 (ins i32mem:$dst, FR32X:$src),
1246 "vmovd{z}\t{$src, $dst|$dst, $src}",
1247 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
1248 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
1249
1250// Move Quadword Int to Packed Quadword Int
1251//
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]1252def VMOVQI2PQIZrm : AVX512SI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1253 (ins i64mem:$src),
1254 "vmovq{z}\t{$src, $dst|$dst, $src}",
1255 [(set VR128X:$dst,
1256 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
1257 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
1258
1259//===----------------------------------------------------------------------===//
1260// AVX-512 MOVSS, MOVSD
1261//===----------------------------------------------------------------------===//
1262
1263multiclass avx512_move_scalar <string asm, RegisterClass RC,
1264 SDNode OpNode, ValueType vt,
1265 X86MemOperand x86memop, PatFrag mem_pat> {
1266 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
1267 !strconcat(asm, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1268 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
1269 (scalar_to_vector RC:$src2))))],
1270 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
1271 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1272 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1273 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
1274 EVEX, VEX_LIG;
1275 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
1276 !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
1277 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
1278 EVEX, VEX_LIG;
1279}
1280
1281let ExeDomain = SSEPackedSingle in
1282defm VMOVSSZ : avx512_move_scalar<"movss{z}", FR32X, X86Movss, v4f32, f32mem,
1283 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
1284
1285let ExeDomain = SSEPackedDouble in
1286defm VMOVSDZ : avx512_move_scalar<"movsd{z}", FR64X, X86Movsd, v2f64, f64mem,
1287 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
1288
1289
1290// For the disassembler
1291let isCodeGenOnly = 1 in {
1292 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1293 (ins VR128X:$src1, FR32X:$src2),
1294 "movss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1295 IIC_SSE_MOV_S_RR>,
1296 XS, EVEX_4V, VEX_LIG;
1297 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
1298 (ins VR128X:$src1, FR64X:$src2),
1299 "movsd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
1300 IIC_SSE_MOV_S_RR>,
1301 XD, EVEX_4V, VEX_LIG, VEX_W;
1302}
1303
1304let Predicates = [HasAVX512] in {
1305 let AddedComplexity = 15 in {
1306 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
1307 // MOVS{S,D} to the lower bits.
1308 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
1309 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
1310 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
1311 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1312 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
1313 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
1314 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
1315 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
1316
1317 // Move low f32 and clear high bits.
1318 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
1319 (SUBREG_TO_REG (i32 0),
1320 (VMOVSSZrr (v4f32 (V_SET0)),
1321 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
1322 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
1323 (SUBREG_TO_REG (i32 0),
1324 (VMOVSSZrr (v4i32 (V_SET0)),
1325 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
1326 }
1327
1328 let AddedComplexity = 20 in {
1329 // MOVSSrm zeros the high parts of the register; represent this
1330 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1331 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
1332 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1333 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
1334 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1335 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
1336 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
1337
1338 // MOVSDrm zeros the high parts of the register; represent this
1339 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
1340 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
1341 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1342 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
1343 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1344 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
1345 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1346 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
1347 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1348 def : Pat<(v2f64 (X86vzload addr:$src)),
1349 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
1350
1351 // Represent the same patterns above but in the form they appear for
1352 // 256-bit types
1353 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1354 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1355 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1356 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1357 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
1358 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
1359 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1360 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
1361 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
1362 }
1363 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
1364 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
1365 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
1366 FR32X:$src)), sub_xmm)>;
1367 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
1368 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
1369 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
1370 FR64X:$src)), sub_xmm)>;
1371 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1372 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]1373 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1374
1375 // Move low f64 and clear high bits.
1376 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
1377 (SUBREG_TO_REG (i32 0),
1378 (VMOVSDZrr (v2f64 (V_SET0)),
1379 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
1380
1381 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
1382 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
1383 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
1384
1385 // Extract and store.
1386 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
1387 addr:$dst),
1388 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
1389 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
1390 addr:$dst),
1391 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
1392
1393 // Shuffle with VMOVSS
1394 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
1395 (VMOVSSZrr (v4i32 VR128X:$src1),
1396 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
1397 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
1398 (VMOVSSZrr (v4f32 VR128X:$src1),
1399 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
1400
1401 // 256-bit variants
1402 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
1403 (SUBREG_TO_REG (i32 0),
1404 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
1405 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
1406 sub_xmm)>;
1407 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
1408 (SUBREG_TO_REG (i32 0),
1409 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
1410 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
1411 sub_xmm)>;
1412
1413 // Shuffle with VMOVSD
1414 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1415 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1416 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
1417 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1418 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1419 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1420 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
1421 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1422
1423 // 256-bit variants
1424 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1425 (SUBREG_TO_REG (i32 0),
1426 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
1427 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
1428 sub_xmm)>;
1429 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
1430 (SUBREG_TO_REG (i32 0),
1431 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
1432 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
1433 sub_xmm)>;
1434
1435 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1436 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1437 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
1438 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1439 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1440 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1441 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
1442 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
1443}
1444
1445let AddedComplexity = 15 in
1446def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
1447 (ins VR128X:$src),
1448 "vmovq{z}\t{$src, $dst|$dst, $src}",
1449 [(set VR128X:$dst, (v2i64 (X86vzmovl
1450 (v2i64 VR128X:$src))))],
1451 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
1452
1453let AddedComplexity = 20 in
1454def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
1455 (ins i128mem:$src),
1456 "vmovq{z}\t{$src, $dst|$dst, $src}",
1457 [(set VR128X:$dst, (v2i64 (X86vzmovl
1458 (loadv2i64 addr:$src))))],
1459 IIC_SSE_MOVDQ>, EVEX, VEX_W,
1460 EVEX_CD8<8, CD8VT8>;
1461
1462let Predicates = [HasAVX512] in {
1463 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
1464 let AddedComplexity = 20 in {
1465 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
1466 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1467 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
1468 (VMOV64toPQIZrr GR64:$src)>;
1469 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
1470 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1471
1472 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
1473 (VMOVDI2PDIZrm addr:$src)>;
1474 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
1475 (VMOVDI2PDIZrm addr:$src)>;
1476 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
1477 (VMOVZPQILo2PQIZrm addr:$src)>;
1478 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
1479 (VMOVZPQILo2PQIZrr VR128X:$src)>;
1480 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]1481
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1482 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
1483 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
1484 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
1485 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
1486 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
1487 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
1488 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
1489}
1490
1491def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
1492 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1493
1494def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
1495 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1496
1497def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
1498 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
1499
1500def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
1501 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
1502
1503//===----------------------------------------------------------------------===//
1504// AVX-512 - Integer arithmetic
1505//
1506multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1507 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1508 X86MemOperand x86memop, PatFrag scalar_mfrag,
1509 X86MemOperand x86scalar_mop, string BrdcstStr,
1510 OpndItins itins, bit IsCommutable = 0> {
1511 let isCommutable = IsCommutable in
1512 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1513 (ins RC:$src1, RC:$src2),
1514 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1515 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1516 itins.rr>, EVEX_4V;
1517 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1518 (ins RC:$src1, x86memop:$src2),
1519 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1520 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
1521 itins.rm>, EVEX_4V;
1522 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1523 (ins RC:$src1, x86scalar_mop:$src2),
1524 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1525 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1526 [(set RC:$dst, (OpNode RC:$src1,
1527 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
1528 itins.rm>, EVEX_4V, EVEX_B;
1529}
1530multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr,
1531 ValueType DstVT, ValueType SrcVT, RegisterClass RC,
1532 PatFrag memop_frag, X86MemOperand x86memop,
1533 OpndItins itins,
1534 bit IsCommutable = 0> {
1535 let isCommutable = IsCommutable in
1536 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1537 (ins RC:$src1, RC:$src2),
1538 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1539 []>, EVEX_4V, VEX_W;
1540 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1541 (ins RC:$src1, x86memop:$src2),
1542 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1543 []>, EVEX_4V, VEX_W;
1544}
1545
1546defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VR512, memopv16i32,
1547 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1548 EVEX_V512, EVEX_CD8<32, CD8VF>;
1549
1550defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VR512, memopv16i32,
1551 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 0>,
1552 EVEX_V512, EVEX_CD8<32, CD8VF>;
1553
1554defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VR512, memopv16i32,
1555 i512mem, loadi32, i32mem, "{1to16}", SSE_INTALU_ITINS_P, 1>,
1556 T8, EVEX_V512, EVEX_CD8<32, CD8VF>;
1557
1558defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VR512, memopv8i64,
1559 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 1>,
1560 EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
1561
1562defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VR512, memopv8i64,
1563 i512mem, loadi64, i64mem, "{1to8}", SSE_INTALU_ITINS_P, 0>,
1564 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1565
1566defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32,
1567 VR512, memopv8i64, i512mem, SSE_INTALU_ITINS_P, 1>, T8,
1568 EVEX_V512, EVEX_CD8<64, CD8VF>;
1569
1570defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32,
1571 VR512, memopv8i64, i512mem, SSE_INTMUL_ITINS_P, 1>, EVEX_V512,
1572 EVEX_CD8<64, CD8VF>;
1573
1574def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
1575 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
1576
1577//===----------------------------------------------------------------------===//
1578// AVX-512 - Unpack Instructions
1579//===----------------------------------------------------------------------===//
1580
1581multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
1582 PatFrag mem_frag, RegisterClass RC,
1583 X86MemOperand x86memop, string asm,
1584 Domain d> {
1585 def rr : AVX512PI<opc, MRMSrcReg,
1586 (outs RC:$dst), (ins RC:$src1, RC:$src2),
1587 asm, [(set RC:$dst,
1588 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1589 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1590 def rm : AVX512PI<opc, MRMSrcMem,
1591 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1592 asm, [(set RC:$dst,
1593 (vt (OpNode RC:$src1,
1594 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1595 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1596}
1597
1598defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
1599 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1600 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1601defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
1602 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1603 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1604defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
1605 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1606 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1607defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
1608 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1609 SSEPackedDouble>, OpSize, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1610
1611multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
1612 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
1613 X86MemOperand x86memop> {
1614 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1615 (ins RC:$src1, RC:$src2),
1616 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1617 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
1618 IIC_SSE_UNPCK>, EVEX_4V;
1619 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1620 (ins RC:$src1, x86memop:$src2),
1621 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1622 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
1623 (bitconvert (memop_frag addr:$src2)))))],
1624 IIC_SSE_UNPCK>, EVEX_4V;
1625}
1626defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
1627 VR512, memopv16i32, i512mem>, EVEX_V512,
1628 EVEX_CD8<32, CD8VF>;
1629defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
1630 VR512, memopv8i64, i512mem>, EVEX_V512,
1631 VEX_W, EVEX_CD8<64, CD8VF>;
1632defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
1633 VR512, memopv16i32, i512mem>, EVEX_V512,
1634 EVEX_CD8<32, CD8VF>;
1635defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
1636 VR512, memopv8i64, i512mem>, EVEX_V512,
1637 VEX_W, EVEX_CD8<64, CD8VF>;
1638//===----------------------------------------------------------------------===//
1639// AVX-512 - PSHUFD
1640//
1641
1642multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
1643 SDNode OpNode, PatFrag mem_frag,
1644 X86MemOperand x86memop, ValueType OpVT> {
1645 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
1646 (ins RC:$src1, i8imm:$src2),
1647 !strconcat(OpcodeStr,
1648 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1649 [(set RC:$dst,
1650 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
1651 EVEX;
1652 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
1653 (ins x86memop:$src1, i8imm:$src2),
1654 !strconcat(OpcodeStr,
1655 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1656 [(set RC:$dst,
1657 (OpVT (OpNode (mem_frag addr:$src1),
1658 (i8 imm:$src2))))]>, EVEX;
1659}
1660
1661defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
1662 i512mem, v16i32>, OpSize, EVEX_V512, EVEX_CD8<32, CD8VF>;
1663
1664let ExeDomain = SSEPackedSingle in
1665defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilp,
1666 memopv16f32, i512mem, v16f32>, OpSize, TA, EVEX_V512,
1667 EVEX_CD8<32, CD8VF>;
1668let ExeDomain = SSEPackedDouble in
1669defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilp,
1670 memopv8f64, i512mem, v8f64>, OpSize, TA, EVEX_V512,
1671 VEX_W, EVEX_CD8<32, CD8VF>;
1672
1673def : Pat<(v16i32 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1674 (VPERMILPSZri VR512:$src1, imm:$imm)>;
1675def : Pat<(v8i64 (X86VPermilp VR512:$src1, (i8 imm:$imm))),
1676 (VPERMILPDZri VR512:$src1, imm:$imm)>;
1677
1678//===----------------------------------------------------------------------===//
1679// AVX-512 Logical Instructions
1680//===----------------------------------------------------------------------===//
1681
1682defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VR512, memopv16i32,
1683 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1684 EVEX_V512, EVEX_CD8<32, CD8VF>;
1685defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VR512, memopv8i64,
1686 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1687 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1688defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VR512, memopv16i32,
1689 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1690 EVEX_V512, EVEX_CD8<32, CD8VF>;
1691defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VR512, memopv8i64,
1692 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1693 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1694defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VR512, memopv16i32,
1695 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
1696 EVEX_V512, EVEX_CD8<32, CD8VF>;
1697defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VR512, memopv8i64,
1698 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
1699 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1700defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VR512,
1701 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
1702 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1703defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VR512, memopv8i64,
1704 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 0>,
1705 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
1706
1707//===----------------------------------------------------------------------===//
1708// AVX-512 FP arithmetic
1709//===----------------------------------------------------------------------===//
1710
1711multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
1712 SizeItins itins> {
1713 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss{z}"), OpNode, FR32X,
1714 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
1715 EVEX_CD8<32, CD8VT1>;
1716 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd{z}"), OpNode, FR64X,
1717 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
1718 EVEX_CD8<64, CD8VT1>;
1719}
1720
1721let isCommutable = 1 in {
1722defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
1723defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
1724defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
1725defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
1726}
1727let isCommutable = 0 in {
1728defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
1729defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
1730}
1731
1732multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1733 RegisterClass RC, ValueType vt,
1734 X86MemOperand x86memop, PatFrag mem_frag,
1735 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
1736 string BrdcstStr,
1737 Domain d, OpndItins itins, bit commutable> {
1738 let isCommutable = commutable in
1739 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
1740 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1741 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1742 EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1743 let mayLoad = 1 in {
1744 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
1745 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1746 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1747 itins.rm, d>, EVEX_4V, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1748 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
1749 (ins RC:$src1, x86scalar_mop:$src2),
1750 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
1751 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
1752 [(set RC:$dst, (OpNode RC:$src1,
1753 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]1754 itins.rm, d>, EVEX_4V, EVEX_B, TB;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1755 }
1756}
1757
1758defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VR512, v16f32, f512mem,
1759 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1760 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1761
1762defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VR512, v8f64, f512mem,
1763 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1764 SSE_ALU_ITINS_P.d, 1>,
1765 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1766
1767defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VR512, v16f32, f512mem,
1768 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1769 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1770defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VR512, v8f64, f512mem,
1771 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1772 SSE_ALU_ITINS_P.d, 1>,
1773 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1774
1775defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VR512, v16f32, f512mem,
1776 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1777 SSE_ALU_ITINS_P.s, 1>,
1778 EVEX_V512, EVEX_CD8<32, CD8VF>;
1779defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VR512, v16f32, f512mem,
1780 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1781 SSE_ALU_ITINS_P.s, 1>,
1782 EVEX_V512, EVEX_CD8<32, CD8VF>;
1783
1784defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VR512, v8f64, f512mem,
1785 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1786 SSE_ALU_ITINS_P.d, 1>,
1787 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1788defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VR512, v8f64, f512mem,
1789 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1790 SSE_ALU_ITINS_P.d, 1>,
1791 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1792
1793defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VR512, v16f32, f512mem,
1794 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1795 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1796defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VR512, v16f32, f512mem,
1797 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
1798 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
1799
1800defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VR512, v8f64, f512mem,
1801 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1802 SSE_ALU_ITINS_P.d, 0>,
1803 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1804defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VR512, v8f64, f512mem,
1805 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
1806 SSE_ALU_ITINS_P.d, 0>,
1807 EVEX_V512, OpSize, VEX_W, EVEX_CD8<64, CD8VF>;
1808
1809//===----------------------------------------------------------------------===//
1810// AVX-512 VPTESTM instructions
1811//===----------------------------------------------------------------------===//
1812
1813multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1814 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
1815 SDNode OpNode, ValueType vt> {
1816 def rr : AVX5128I<opc, MRMSrcReg,
1817 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
1818 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1819 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))]>, EVEX_4V;
1820 def rm : AVX5128I<opc, MRMSrcMem,
1821 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
1822 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1823 [(set KRC:$dst, (OpNode (vt RC:$src1),
1824 (bitconvert (memop_frag addr:$src2))))]>, EVEX_4V;
1825}
1826
1827defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
1828 memopv16i32, X86testm, v16i32>, EVEX_V512,
1829 EVEX_CD8<32, CD8VF>;
1830defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
1831 memopv8i64, X86testm, v8i64>, EVEX_V512, VEX_W,
1832 EVEX_CD8<64, CD8VF>;
1833
1834//===----------------------------------------------------------------------===//
1835// AVX-512 Shift instructions
1836//===----------------------------------------------------------------------===//
1837multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
1838 string OpcodeStr, SDNode OpNode, RegisterClass RC,
1839 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
1840 RegisterClass KRC> {
1841 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1842 (ins RC:$src1, i32i8imm:$src2),
1843 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1844 [(set RC:$dst, (vt (OpNode RC:$src1, (i32 imm:$src2))))],
1845 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1846 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
1847 (ins KRC:$mask, RC:$src1, i32i8imm:$src2),
1848 !strconcat(OpcodeStr,
1849 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1850 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1851 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1852 (ins x86memop:$src1, i32i8imm:$src2),
1853 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1854 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
1855 (i32 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1856 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
1857 (ins KRC:$mask, x86memop:$src1, i32i8imm:$src2),
1858 !strconcat(OpcodeStr,
1859 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1860 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1861}
1862
1863multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
1864 RegisterClass RC, ValueType vt, ValueType SrcVT,
1865 PatFrag bc_frag, RegisterClass KRC> {
1866 // src2 is always 128-bit
1867 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1868 (ins RC:$src1, VR128X:$src2),
1869 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1870 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
1871 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
1872 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
1873 (ins KRC:$mask, RC:$src1, VR128X:$src2),
1874 !strconcat(OpcodeStr,
1875 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1876 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
1877 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1878 (ins RC:$src1, i128mem:$src2),
1879 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1880 [(set RC:$dst, (vt (OpNode RC:$src1,
1881 (bc_frag (memopv2i64 addr:$src2)))))],
1882 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
1883 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
1884 (ins KRC:$mask, RC:$src1, i128mem:$src2),
1885 !strconcat(OpcodeStr,
1886 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
1887 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
1888}
1889
1890defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
1891 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1892 EVEX_V512, EVEX_CD8<32, CD8VF>;
1893defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
1894 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1895 EVEX_CD8<32, CD8VQ>;
1896
1897defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
1898 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1899 EVEX_CD8<64, CD8VF>, VEX_W;
1900defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
1901 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1902 EVEX_CD8<64, CD8VQ>, VEX_W;
1903
1904defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
1905 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
1906 EVEX_CD8<32, CD8VF>;
1907defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
1908 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1909 EVEX_CD8<32, CD8VQ>;
1910
1911defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
1912 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1913 EVEX_CD8<64, CD8VF>, VEX_W;
1914defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
1915 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1916 EVEX_CD8<64, CD8VQ>, VEX_W;
1917
1918defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
1919 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
1920 EVEX_V512, EVEX_CD8<32, CD8VF>;
1921defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
1922 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
1923 EVEX_CD8<32, CD8VQ>;
1924
1925defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
1926 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
1927 EVEX_CD8<64, CD8VF>, VEX_W;
1928defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
1929 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
1930 EVEX_CD8<64, CD8VQ>, VEX_W;
1931
1932//===-------------------------------------------------------------------===//
1933// Variable Bit Shifts
1934//===-------------------------------------------------------------------===//
1935multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
1936 RegisterClass RC, ValueType vt,
1937 X86MemOperand x86memop, PatFrag mem_frag> {
1938 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
1939 (ins RC:$src1, RC:$src2),
1940 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1941 [(set RC:$dst,
1942 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
1943 EVEX_4V;
1944 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
1945 (ins RC:$src1, x86memop:$src2),
1946 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1947 [(set RC:$dst,
1948 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
1949 EVEX_4V;
1950}
1951
1952defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
1953 i512mem, memopv16i32>, EVEX_V512,
1954 EVEX_CD8<32, CD8VF>;
1955defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
1956 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1957 EVEX_CD8<64, CD8VF>;
1958defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
1959 i512mem, memopv16i32>, EVEX_V512,
1960 EVEX_CD8<32, CD8VF>;
1961defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
1962 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1963 EVEX_CD8<64, CD8VF>;
1964defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
1965 i512mem, memopv16i32>, EVEX_V512,
1966 EVEX_CD8<32, CD8VF>;
1967defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
1968 i512mem, memopv8i64>, EVEX_V512, VEX_W,
1969 EVEX_CD8<64, CD8VF>;
1970
1971//===----------------------------------------------------------------------===//
1972// AVX-512 - MOVDDUP
1973//===----------------------------------------------------------------------===//
1974
1975multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
1976 X86MemOperand x86memop, PatFrag memop_frag> {
1977def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
1978 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1979 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
1980def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
1981 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1982 [(set RC:$dst,
1983 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
1984}
1985
1986defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
1987 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
1988def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
1989 (VMOVDDUPZrm addr:$src)>;
1990
1991def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
1992 (ins VR128X:$src1, VR128X:$src2),
1993 "vmovlhps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1994 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
1995 IIC_SSE_MOV_LH>, EVEX_4V;
1996def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
1997 (ins VR128X:$src1, VR128X:$src2),
1998 "vmovhlps{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1999 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
2000 IIC_SSE_MOV_LH>, EVEX_4V;
2001
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2002let Predicates = [HasAVX512] in {
2003 // MOVLHPS patterns
2004 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2005 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
2006 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
2007 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2008
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]2009 // MOVHLPS patterns
2010 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
2011 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
2012}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2013
2014//===----------------------------------------------------------------------===//
2015// FMA - Fused Multiply Operations
2016//
2017let Constraints = "$src1 = $dst" in {
2018multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr,
2019 RegisterClass RC, X86MemOperand x86memop,
2020 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2021 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2022 def r: AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2023 (ins RC:$src1, RC:$src2, RC:$src3),
2024 !strconcat(OpcodeStr,"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2025 [(set RC:$dst, (OpVT(OpNode RC:$src1, RC:$src2, RC:$src3)))]>;
2026
2027 let mayLoad = 1 in
2028 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2029 (ins RC:$src1, RC:$src2, x86memop:$src3),
2030 !strconcat(OpcodeStr, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2031 [(set RC:$dst, (OpVT (OpNode RC:$src1, RC:$src2,
2032 (mem_frag addr:$src3))))]>;
2033 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2034 (ins RC:$src1, RC:$src2, x86scalar_mop:$src3),
2035 !strconcat(OpcodeStr, "\t{${src3}", BrdcstStr,
2036 ", $src2, $dst|$dst, $src2, ${src3}", BrdcstStr, "}"),
2037 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
2038 (OpVT (X86VBroadcast (scalar_mfrag addr:$src3)))))]>, EVEX_B;
2039}
2040} // Constraints = "$src1 = $dst"
2041
2042let ExeDomain = SSEPackedSingle in {
2043 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", VR512, f512mem,
2044 memopv16f32, f32mem, loadf32, "{1to16}",
2045 X86Fmadd, v16f32>, EVEX_V512,
2046 EVEX_CD8<32, CD8VF>;
2047 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", VR512, f512mem,
2048 memopv16f32, f32mem, loadf32, "{1to16}",
2049 X86Fmsub, v16f32>, EVEX_V512,
2050 EVEX_CD8<32, CD8VF>;
2051 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", VR512, f512mem,
2052 memopv16f32, f32mem, loadf32, "{1to16}",
2053 X86Fmaddsub, v16f32>,
2054 EVEX_V512, EVEX_CD8<32, CD8VF>;
2055 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", VR512, f512mem,
2056 memopv16f32, f32mem, loadf32, "{1to16}",
2057 X86Fmsubadd, v16f32>,
2058 EVEX_V512, EVEX_CD8<32, CD8VF>;
2059 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", VR512, f512mem,
2060 memopv16f32, f32mem, loadf32, "{1to16}",
2061 X86Fnmadd, v16f32>, EVEX_V512,
2062 EVEX_CD8<32, CD8VF>;
2063 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", VR512, f512mem,
2064 memopv16f32, f32mem, loadf32, "{1to16}",
2065 X86Fnmsub, v16f32>, EVEX_V512,
2066 EVEX_CD8<32, CD8VF>;
2067}
2068let ExeDomain = SSEPackedDouble in {
2069 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", VR512, f512mem,
2070 memopv8f64, f64mem, loadf64, "{1to8}",
2071 X86Fmadd, v8f64>, EVEX_V512,
2072 VEX_W, EVEX_CD8<64, CD8VF>;
2073 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", VR512, f512mem,
2074 memopv8f64, f64mem, loadf64, "{1to8}",
2075 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2076 EVEX_CD8<64, CD8VF>;
2077 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", VR512, f512mem,
2078 memopv8f64, f64mem, loadf64, "{1to8}",
2079 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2080 EVEX_CD8<64, CD8VF>;
2081 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", VR512, f512mem,
2082 memopv8f64, f64mem, loadf64, "{1to8}",
2083 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2084 EVEX_CD8<64, CD8VF>;
2085 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", VR512, f512mem,
2086 memopv8f64, f64mem, loadf64, "{1to8}",
2087 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2088 EVEX_CD8<64, CD8VF>;
2089 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", VR512, f512mem,
2090 memopv8f64, f64mem, loadf64, "{1to8}",
2091 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2092 EVEX_CD8<64, CD8VF>;
2093}
2094
2095let Constraints = "$src1 = $dst" in {
2096multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr,
2097 RegisterClass RC, X86MemOperand x86memop,
2098 PatFrag mem_frag, X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2099 string BrdcstStr, SDNode OpNode, ValueType OpVT> {
2100 let mayLoad = 1 in
2101 def m: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2102 (ins RC:$src1, RC:$src3, x86memop:$src2),
2103 !strconcat(OpcodeStr, "\t{$src2, $src3, $dst|$dst, $src3, $src2}"),
2104 [(set RC:$dst, (OpVT (OpNode RC:$src1, (mem_frag addr:$src2), RC:$src3)))]>;
2105 def mb: AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2106 (ins RC:$src1, RC:$src3, x86scalar_mop:$src2),
2107 !strconcat(OpcodeStr, "\t{${src2}", BrdcstStr,
2108 ", $src3, $dst|$dst, $src3, ${src2}", BrdcstStr, "}"),
2109 [(set RC:$dst, (OpNode RC:$src1,
2110 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2))), RC:$src3))]>, EVEX_B;
2111}
2112} // Constraints = "$src1 = $dst"
2113
2114
2115let ExeDomain = SSEPackedSingle in {
2116 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", VR512, f512mem,
2117 memopv16f32, f32mem, loadf32, "{1to16}",
2118 X86Fmadd, v16f32>, EVEX_V512,
2119 EVEX_CD8<32, CD8VF>;
2120 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", VR512, f512mem,
2121 memopv16f32, f32mem, loadf32, "{1to16}",
2122 X86Fmsub, v16f32>, EVEX_V512,
2123 EVEX_CD8<32, CD8VF>;
2124 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", VR512, f512mem,
2125 memopv16f32, f32mem, loadf32, "{1to16}",
2126 X86Fmaddsub, v16f32>,
2127 EVEX_V512, EVEX_CD8<32, CD8VF>;
2128 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", VR512, f512mem,
2129 memopv16f32, f32mem, loadf32, "{1to16}",
2130 X86Fmsubadd, v16f32>,
2131 EVEX_V512, EVEX_CD8<32, CD8VF>;
2132 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", VR512, f512mem,
2133 memopv16f32, f32mem, loadf32, "{1to16}",
2134 X86Fnmadd, v16f32>, EVEX_V512,
2135 EVEX_CD8<32, CD8VF>;
2136 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", VR512, f512mem,
2137 memopv16f32, f32mem, loadf32, "{1to16}",
2138 X86Fnmsub, v16f32>, EVEX_V512,
2139 EVEX_CD8<32, CD8VF>;
2140}
2141let ExeDomain = SSEPackedDouble in {
2142 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", VR512, f512mem,
2143 memopv8f64, f64mem, loadf64, "{1to8}",
2144 X86Fmadd, v8f64>, EVEX_V512,
2145 VEX_W, EVEX_CD8<64, CD8VF>;
2146 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", VR512, f512mem,
2147 memopv8f64, f64mem, loadf64, "{1to8}",
2148 X86Fmsub, v8f64>, EVEX_V512, VEX_W,
2149 EVEX_CD8<64, CD8VF>;
2150 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", VR512, f512mem,
2151 memopv8f64, f64mem, loadf64, "{1to8}",
2152 X86Fmaddsub, v8f64>, EVEX_V512, VEX_W,
2153 EVEX_CD8<64, CD8VF>;
2154 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", VR512, f512mem,
2155 memopv8f64, f64mem, loadf64, "{1to8}",
2156 X86Fmsubadd, v8f64>, EVEX_V512, VEX_W,
2157 EVEX_CD8<64, CD8VF>;
2158 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", VR512, f512mem,
2159 memopv8f64, f64mem, loadf64, "{1to8}",
2160 X86Fnmadd, v8f64>, EVEX_V512, VEX_W,
2161 EVEX_CD8<64, CD8VF>;
2162 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", VR512, f512mem,
2163 memopv8f64, f64mem, loadf64, "{1to8}",
2164 X86Fnmsub, v8f64>, EVEX_V512, VEX_W,
2165 EVEX_CD8<64, CD8VF>;
2166}
2167
2168// Scalar FMA
2169let Constraints = "$src1 = $dst" in {
2170multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
2171 RegisterClass RC, ValueType OpVT,
2172 X86MemOperand x86memop, Operand memop,
2173 PatFrag mem_frag> {
2174 let isCommutable = 1 in
2175 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
2176 (ins RC:$src1, RC:$src2, RC:$src3),
2177 !strconcat(OpcodeStr,
2178 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2179 [(set RC:$dst,
2180 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
2181 let mayLoad = 1 in
2182 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
2183 (ins RC:$src1, RC:$src2, f128mem:$src3),
2184 !strconcat(OpcodeStr,
2185 "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
2186 [(set RC:$dst,
2187 (OpVT (OpNode RC:$src2, RC:$src1,
2188 (mem_frag addr:$src3))))]>;
2189}
2190
2191} // Constraints = "$src1 = $dst"
2192
2193defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss{z}", X86Fmadd, FR32X,
2194 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2195defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd{z}", X86Fmadd, FR64X,
2196 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2197defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss{z}", X86Fmsub, FR32X,
2198 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2199defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd{z}", X86Fmsub, FR64X,
2200 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2201defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss{z}", X86Fnmadd, FR32X,
2202 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2203defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd{z}", X86Fnmadd, FR64X,
2204 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2205defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss{z}", X86Fnmsub, FR32X,
2206 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
2207defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd{z}", X86Fnmsub, FR64X,
2208 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
2209
2210//===----------------------------------------------------------------------===//
2211// AVX-512 Scalar convert from sign integer to float/double
2212//===----------------------------------------------------------------------===//
2213
2214multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2215 X86MemOperand x86memop, string asm> {
2216let neverHasSideEffects = 1 in {
2217 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame^]2218 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2219 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2220 let mayLoad = 1 in
2221 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
2222 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame^]2223 !strconcat(asm,"\t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
2224 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2225} // neverHasSideEffects = 1
2226}
2227
2228defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}{z}">,
2229 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame^]2230defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2231 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2232defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}{z}">,
2233 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame^]2234defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}{z}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2235 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2236
2237def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
2238 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2239def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame^]2240 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2241def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
2242 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2243def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame^]2244 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2245
2246def : Pat<(f32 (sint_to_fp GR32:$src)),
2247 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2248def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame^]2249 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2250def : Pat<(f64 (sint_to_fp GR32:$src)),
2251 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2252def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame^]2253 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
2254
2255defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}{z}">,
2256 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2257defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}{z}">,
2258 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2259defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}{z}">,
2260 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2261defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}{z}">,
2262 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
2263
2264def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
2265 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2266def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
2267 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
2268def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
2269 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2270def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
2271 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
2272
2273def : Pat<(f32 (uint_to_fp GR32:$src)),
2274 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
2275def : Pat<(f32 (uint_to_fp GR64:$src)),
2276 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
2277def : Pat<(f64 (uint_to_fp GR32:$src)),
2278 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
2279def : Pat<(f64 (uint_to_fp GR64:$src)),
2280 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2281
2282
2283//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame^]2284// AVX-512 Scalar convert from float/double to integer
2285//===----------------------------------------------------------------------===//
2286multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2287 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
2288 string asm> {
2289let neverHasSideEffects = 1 in {
2290 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2291 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2292 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG;
2293 let mayLoad = 1 in
2294 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
2295 !strconcat(asm,"\t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG;
2296} // neverHasSideEffects = 1
2297}
2298let Predicates = [HasAVX512] in {
2299// Convert float/double to signed/unsigned int 32/64
2300defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
2301 ssmem, sse_load_f32, "cvtss2si{z}">,
2302 XS, EVEX_CD8<32, CD8VT1>;
2303defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
2304 ssmem, sse_load_f32, "cvtss2si{z}">,
2305 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
2306defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
2307 ssmem, sse_load_f32, "cvtss2usi{z}">,
2308 XS, EVEX_CD8<32, CD8VT1>;
2309defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2310 int_x86_avx512_cvtss2usi64, ssmem,
2311 sse_load_f32, "cvtss2usi{z}">, XS, VEX_W,
2312 EVEX_CD8<32, CD8VT1>;
2313defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
2314 sdmem, sse_load_f64, "cvtsd2si{z}">,
2315 XD, EVEX_CD8<64, CD8VT1>;
2316defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
2317 sdmem, sse_load_f64, "cvtsd2si{z}">,
2318 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2319defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
2320 sdmem, sse_load_f64, "cvtsd2usi{z}">,
2321 XD, EVEX_CD8<64, CD8VT1>;
2322defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
2323 int_x86_avx512_cvtsd2usi64, sdmem,
2324 sse_load_f64, "cvtsd2usi{z}">, XD, VEX_W,
2325 EVEX_CD8<64, CD8VT1>;
2326
2327defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2328 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}{z}",
2329 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2330defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2331 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}{z}",
2332 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2333defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2334 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}{z}",
2335 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2336defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2337 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}{z}",
2338 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2339
2340defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2341 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}{z}",
2342 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
2343defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2344 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}{z}",
2345 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
2346defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
2347 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}{z}",
2348 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
2349defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
2350 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}{z}",
2351 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
2352
2353// Convert float/double to signed/unsigned int 32/64 with truncation
2354defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
2355 ssmem, sse_load_f32, "cvttss2si{z}">,
2356 XS, EVEX_CD8<32, CD8VT1>;
2357defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2358 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
2359 "cvttss2si{z}">, XS, VEX_W,
2360 EVEX_CD8<32, CD8VT1>;
2361defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
2362 sdmem, sse_load_f64, "cvttsd2si{z}">, XD,
2363 EVEX_CD8<64, CD8VT1>;
2364defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
2365 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
2366 "cvttsd2si{z}">, XD, VEX_W,
2367 EVEX_CD8<64, CD8VT1>;
2368defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2369 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
2370 "cvttss2si{z}">, XS, EVEX_CD8<32, CD8VT1>;
2371defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2372 int_x86_avx512_cvttss2usi64, ssmem,
2373 sse_load_f32, "cvttss2usi{z}">, XS, VEX_W,
2374 EVEX_CD8<32, CD8VT1>;
2375defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
2376 int_x86_avx512_cvttsd2usi,
2377 sdmem, sse_load_f64, "cvttsd2usi{z}">, XD,
2378 EVEX_CD8<64, CD8VT1>;
2379defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
2380 int_x86_avx512_cvttsd2usi64, sdmem,
2381 sse_load_f64, "cvttsd2usi{z}">, XD, VEX_W,
2382 EVEX_CD8<64, CD8VT1>;
2383}
2384
2385multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
2386 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
2387 string asm> {
2388 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2389 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2390 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
2391 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2392 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2393 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
2394}
2395
2396defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
2397 loadf32, "cvttss2si{z}">, XS,
2398 EVEX_CD8<32, CD8VT1>;
2399defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
2400 loadf32, "cvttss2usi{z}">, XS,
2401 EVEX_CD8<32, CD8VT1>;
2402defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
2403 loadf32, "cvttss2si{z}">, XS, VEX_W,
2404 EVEX_CD8<32, CD8VT1>;
2405defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
2406 loadf32, "cvttss2usi{z}">, XS, VEX_W,
2407 EVEX_CD8<32, CD8VT1>;
2408defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
2409 loadf64, "cvttsd2si{z}">, XD,
2410 EVEX_CD8<64, CD8VT1>;
2411defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
2412 loadf64, "cvttsd2usi{z}">, XD,
2413 EVEX_CD8<64, CD8VT1>;
2414defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
2415 loadf64, "cvttsd2si{z}">, XD, VEX_W,
2416 EVEX_CD8<64, CD8VT1>;
2417defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
2418 loadf64, "cvttsd2usi{z}">, XD, VEX_W,
2419 EVEX_CD8<64, CD8VT1>;
2420//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2421// AVX-512 Convert form float to double and back
2422//===----------------------------------------------------------------------===//
2423let neverHasSideEffects = 1 in {
2424def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
2425 (ins FR32X:$src1, FR32X:$src2),
2426 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2427 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
2428let mayLoad = 1 in
2429def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
2430 (ins FR32X:$src1, f32mem:$src2),
2431 "vcvtss2sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2432 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
2433 EVEX_CD8<32, CD8VT1>;
2434
2435// Convert scalar double to scalar single
2436def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
2437 (ins FR64X:$src1, FR64X:$src2),
2438 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2439 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
2440let mayLoad = 1 in
2441def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
2442 (ins FR64X:$src1, f64mem:$src2),
2443 "vcvtsd2ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
2444 []>, EVEX_4V, VEX_LIG, VEX_W,
2445 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
2446}
2447
2448def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
2449 Requires<[HasAVX512]>;
2450def : Pat<(fextend (loadf32 addr:$src)),
2451 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
2452
2453def : Pat<(extloadf32 addr:$src),
2454 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
2455 Requires<[HasAVX512, OptForSize]>;
2456
2457def : Pat<(extloadf32 addr:$src),
2458 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
2459 Requires<[HasAVX512, OptForSpeed]>;
2460
2461def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
2462 Requires<[HasAVX512]>;
2463
2464multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
2465 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
2466 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
2467 Domain d> {
2468let neverHasSideEffects = 1 in {
2469 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
2470 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2471 [(set DstRC:$dst,
2472 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
2473 let mayLoad = 1 in
2474 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
2475 !strconcat(asm,"\t{$src, $dst|$dst, $src}"),
2476 [(set DstRC:$dst,
2477 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
2478} // neverHasSideEffects = 1
2479}
2480
2481defm VCVTPD2PSZ : avx512_vcvt_fp<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
2482 memopv8f64, f512mem, v8f32, v8f64,
2483 SSEPackedSingle>, EVEX_V512, VEX_W, OpSize,
2484 EVEX_CD8<64, CD8VF>;
2485
2486defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
2487 memopv4f64, f256mem, v8f64, v8f32,
2488 SSEPackedDouble>, EVEX_V512, EVEX_CD8<32, CD8VH>;
2489def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2490 (VCVTPS2PDZrm addr:$src)>;
2491
2492//===----------------------------------------------------------------------===//
2493// AVX-512 Vector convert from sign integer to float/double
2494//===----------------------------------------------------------------------===//
2495
2496defm VCVTDQ2PSZ : avx512_vcvt_fp<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
2497 memopv8i64, i512mem, v16f32, v16i32,
2498 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
2499
2500defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
2501 memopv4i64, i256mem, v8f64, v8i32,
2502 SSEPackedDouble>, EVEX_V512, XS,
2503 EVEX_CD8<32, CD8VH>;
2504
2505defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
2506 memopv16f32, f512mem, v16i32, v16f32,
2507 SSEPackedSingle>, EVEX_V512, XS,
2508 EVEX_CD8<32, CD8VF>;
2509
2510defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
2511 memopv8f64, f512mem, v8i32, v8f64,
2512 SSEPackedDouble>, EVEX_V512, OpSize, VEX_W,
2513 EVEX_CD8<64, CD8VF>;
2514
2515defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
2516 memopv16f32, f512mem, v16i32, v16f32,
2517 SSEPackedSingle>, EVEX_V512,
2518 EVEX_CD8<32, CD8VF>;
2519
2520defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
2521 memopv8f64, f512mem, v8i32, v8f64,
2522 SSEPackedDouble>, EVEX_V512, VEX_W,
2523 EVEX_CD8<64, CD8VF>;
2524
2525defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
2526 memopv4i64, f256mem, v8f64, v8i32,
2527 SSEPackedDouble>, EVEX_V512, XS,
2528 EVEX_CD8<32, CD8VH>;
2529
2530defm VCVTUDQ2PSZ : avx512_vcvt_fp<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
2531 memopv16i32, f512mem, v16f32, v16i32,
2532 SSEPackedSingle>, EVEX_V512, XD,
2533 EVEX_CD8<32, CD8VF>;
2534
2535def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
2536 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
2537 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
2538
2539
2540def : Pat<(int_x86_avx512_cvtdq2_ps_512 VR512:$src),
2541 (VCVTDQ2PSZrr VR512:$src)>;
2542def : Pat<(int_x86_avx512_cvtdq2_ps_512 (bitconvert (memopv8i64 addr:$src))),
2543 (VCVTDQ2PSZrm addr:$src)>;
2544
2545def VCVTPS2DQZrr : AVX512BI<0x5B, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2546 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2547 [(set VR512:$dst,
2548 (int_x86_avx512_cvt_ps2dq_512 VR512:$src))],
2549 IIC_SSE_CVT_PS_RR>, EVEX, EVEX_V512;
2550def VCVTPS2DQZrm : AVX512BI<0x5B, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2551 "vcvtps2dq\t{$src, $dst|$dst, $src}",
2552 [(set VR512:$dst,
2553 (int_x86_avx512_cvt_ps2dq_512 (memopv16f32 addr:$src)))],
2554 IIC_SSE_CVT_PS_RM>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2555
2556
2557let Predicates = [HasAVX512] in {
2558 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
2559 (VCVTPD2PSZrm addr:$src)>;
2560 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
2561 (VCVTPS2PDZrm addr:$src)>;
2562}
2563
2564let Defs = [EFLAGS], Predicates = [HasAVX512] in {
2565 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
2566 "ucomiss{z}">, TB, EVEX, VEX_LIG,
2567 EVEX_CD8<32, CD8VT1>;
2568 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
2569 "ucomisd{z}">, TB, OpSize, EVEX,
2570 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2571 let Pattern = []<dag> in {
2572 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
2573 "comiss{z}">, TB, EVEX, VEX_LIG,
2574 EVEX_CD8<32, CD8VT1>;
2575 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
2576 "comisd{z}">, TB, OpSize, EVEX,
2577 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2578 }
2579 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
2580 load, "ucomiss">, TB, EVEX, VEX_LIG,
2581 EVEX_CD8<32, CD8VT1>;
2582 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
2583 load, "ucomisd">, TB, OpSize, EVEX,
2584 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2585
2586 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
2587 load, "comiss">, TB, EVEX, VEX_LIG,
2588 EVEX_CD8<32, CD8VT1>;
2589 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
2590 load, "comisd">, TB, OpSize, EVEX,
2591 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2592}
2593
2594/// avx512_unop_p - AVX-512 unops in packed form.
2595multiclass avx512_fp_unop_p<bits<8> opc, string OpcodeStr, SDNode OpNode> {
2596 def PSZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2597 !strconcat(OpcodeStr,
2598 "ps\t{$src, $dst|$dst, $src}"),
2599 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))]>,
2600 EVEX, EVEX_V512;
2601 def PSZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f256mem:$src),
2602 !strconcat(OpcodeStr,
2603 "ps\t{$src, $dst|$dst, $src}"),
2604 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2605 EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2606 def PDZr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2607 !strconcat(OpcodeStr,
2608 "pd\t{$src, $dst|$dst, $src}"),
2609 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))]>,
2610 EVEX, EVEX_V512, VEX_W;
2611 def PDZm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2612 !strconcat(OpcodeStr,
2613 "pd\t{$src, $dst|$dst, $src}"),
2614 [(set VR512:$dst, (OpNode (memopv16f32 addr:$src)))]>,
2615 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2616}
2617
2618/// avx512_fp_unop_p_int - AVX-512 intrinsics unops in packed forms.
2619multiclass avx512_fp_unop_p_int<bits<8> opc, string OpcodeStr,
2620 Intrinsic V16F32Int, Intrinsic V8F64Int> {
2621 def PSZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2622 !strconcat(OpcodeStr,
2623 "ps\t{$src, $dst|$dst, $src}"),
2624 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2625 EVEX, EVEX_V512;
2626 def PSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2627 !strconcat(OpcodeStr,
2628 "ps\t{$src, $dst|$dst, $src}"),
2629 [(set VR512:$dst,
2630 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2631 EVEX_V512, EVEX_CD8<32, CD8VF>;
2632 def PDZr_Int : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2633 !strconcat(OpcodeStr,
2634 "pd\t{$src, $dst|$dst, $src}"),
2635 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2636 EVEX, EVEX_V512, VEX_W;
2637 def PDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2638 !strconcat(OpcodeStr,
2639 "pd\t{$src, $dst|$dst, $src}"),
2640 [(set VR512:$dst,
2641 (V8F64Int (memopv8f64 addr:$src)))]>,
2642 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2643}
2644
2645/// avx512_fp_unop_s - AVX-512 unops in scalar form.
2646multiclass avx512_fp_unop_s<bits<8> opc, string OpcodeStr,
2647 Intrinsic F32Int, Intrinsic F64Int> {
2648 let hasSideEffects = 0 in {
2649 def SSZr : AVX5128I<opc, MRMSrcReg, (outs FR32X:$dst),
2650 (ins FR32X:$src1, FR32X:$src2),
2651 !strconcat(OpcodeStr,
2652 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2653 []>, EVEX_4V;
2654 let mayLoad = 1 in {
2655 def SSZm : AVX5128I<opc, MRMSrcMem, (outs FR32X:$dst),
2656 (ins FR32X:$src1, f32mem:$src2),
2657 !strconcat(OpcodeStr,
2658 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2659 []>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2660 def SSZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2661 (ins VR128X:$src1, ssmem:$src2),
2662 !strconcat(OpcodeStr,
2663 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2664 [(set VR128X:$dst, (F32Int VR128X:$src1, sse_load_f32:$src2))]>,
2665 EVEX_4V, EVEX_CD8<32, CD8VT1>;
2666 }
2667 def SDZr : AVX5128I<opc, MRMSrcReg, (outs FR64X:$dst),
2668 (ins FR64X:$src1, FR64X:$src2),
2669 !strconcat(OpcodeStr,
2670 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2671 EVEX_4V, VEX_W;
2672 let mayLoad = 1 in {
2673 def SDZm : AVX5128I<opc, MRMSrcMem, (outs FR64X:$dst),
2674 (ins FR64X:$src1, f64mem:$src2),
2675 !strconcat(OpcodeStr,
2676 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2677 EVEX_4V, VEX_W, EVEX_CD8<32, CD8VT1>;
2678 def SDZm_Int : AVX5128I<opc, MRMSrcMem, (outs VR128X:$dst),
2679 (ins VR128X:$src1, sdmem:$src2),
2680 !strconcat(OpcodeStr,
2681 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2682 [(set VR128X:$dst, (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2683 EVEX_4V, VEX_W, EVEX_CD8<32, CD8VT1>;
2684 }
2685}
2686}
2687
2688defm VRCP14 : avx512_fp_unop_s<0x4D, "vrcp14", int_x86_avx512_rcp14_ss,
2689 int_x86_avx512_rcp14_sd>,
2690 avx512_fp_unop_p<0x4C, "vrcp14", X86frcp>,
2691 avx512_fp_unop_p_int<0x4C, "vrcp14",
2692 int_x86_avx512_rcp14_ps_512, int_x86_avx512_rcp14_pd_512>;
2693
2694defm VRSQRT14 : avx512_fp_unop_s<0x4F, "vrsqrt14", int_x86_avx512_rsqrt14_ss,
2695 int_x86_avx512_rsqrt14_sd>,
2696 avx512_fp_unop_p<0x4E, "vrsqrt14", X86frsqrt>,
2697 avx512_fp_unop_p_int<0x4E, "vrsqrt14",
2698 int_x86_avx512_rsqrt14_ps_512, int_x86_avx512_rsqrt14_pd_512>;
2699
2700multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
2701 Intrinsic V16F32Int, Intrinsic V8F64Int,
2702 OpndItins itins_s, OpndItins itins_d> {
2703 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2704 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2705 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
2706 EVEX, EVEX_V512;
2707
2708 let mayLoad = 1 in
2709 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2710 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2711 [(set VR512:$dst,
2712 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
2713 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
2714
2715 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2716 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2717 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
2718 EVEX, EVEX_V512;
2719
2720 let mayLoad = 1 in
2721 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2722 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2723 [(set VR512:$dst, (OpNode
2724 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
2725 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
2726
2727 def PSZr_Int : AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2728 !strconcat(OpcodeStr,
2729 "ps\t{$src, $dst|$dst, $src}"),
2730 [(set VR512:$dst, (V16F32Int VR512:$src))]>,
2731 EVEX, EVEX_V512;
2732 def PSZm_Int : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2733 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
2734 [(set VR512:$dst,
2735 (V16F32Int (memopv16f32 addr:$src)))]>, EVEX,
2736 EVEX_V512, EVEX_CD8<32, CD8VF>;
2737 def PDZr_Int : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
2738 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
2739 [(set VR512:$dst, (V8F64Int VR512:$src))]>,
2740 EVEX, EVEX_V512, VEX_W;
2741 def PDZm_Int : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
2742 !strconcat(OpcodeStr,
2743 "pd\t{$src, $dst|$dst, $src}"),
2744 [(set VR512:$dst, (V8F64Int (memopv8f64 addr:$src)))]>,
2745 EVEX, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
2746}
2747
2748multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
2749 Intrinsic F32Int, Intrinsic F64Int,
2750 OpndItins itins_s, OpndItins itins_d> {
2751 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
2752 (ins FR32X:$src1, FR32X:$src2),
2753 !strconcat(OpcodeStr,
2754 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2755 [], itins_s.rr>, XS, EVEX_4V;
2756 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2757 (ins VR128X:$src1, VR128X:$src2),
2758 !strconcat(OpcodeStr,
2759 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2760 [(set VR128X:$dst,
2761 (F32Int VR128X:$src1, VR128X:$src2))],
2762 itins_s.rr>, XS, EVEX_4V;
2763 let mayLoad = 1 in {
2764 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
2765 (ins FR32X:$src1, f32mem:$src2),
2766 !strconcat(OpcodeStr,
2767 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2768 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2769 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2770 (ins VR128X:$src1, ssmem:$src2),
2771 !strconcat(OpcodeStr,
2772 "ss{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2773 [(set VR128X:$dst,
2774 (F32Int VR128X:$src1, sse_load_f32:$src2))],
2775 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
2776 }
2777 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
2778 (ins FR64X:$src1, FR64X:$src2),
2779 !strconcat(OpcodeStr,
2780 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2781 XD, EVEX_4V, VEX_W;
2782 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
2783 (ins VR128X:$src1, VR128X:$src2),
2784 !strconcat(OpcodeStr,
2785 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2786 [(set VR128X:$dst,
2787 (F64Int VR128X:$src1, VR128X:$src2))],
2788 itins_s.rr>, XD, EVEX_4V, VEX_W;
2789 let mayLoad = 1 in {
2790 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
2791 (ins FR64X:$src1, f64mem:$src2),
2792 !strconcat(OpcodeStr,
2793 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
2794 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2795 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
2796 (ins VR128X:$src1, sdmem:$src2),
2797 !strconcat(OpcodeStr,
2798 "sd{z}\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2799 [(set VR128X:$dst,
2800 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
2801 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
2802 }
2803}
2804
2805
2806defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
2807 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
2808 SSE_SQRTSS, SSE_SQRTSD>,
2809 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
2810 int_x86_avx512_sqrt_ps_512, int_x86_avx512_sqrt_pd_512,
2811 SSE_SQRTPS, SSE_SQRTPD>;
2812
2813def : Pat<(f32 (fsqrt FR32X:$src)),
2814 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2815def : Pat<(f32 (fsqrt (load addr:$src))),
2816 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2817 Requires<[OptForSize]>;
2818def : Pat<(f64 (fsqrt FR64X:$src)),
2819 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
2820def : Pat<(f64 (fsqrt (load addr:$src))),
2821 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
2822 Requires<[OptForSize]>;
2823
2824def : Pat<(f32 (X86frsqrt FR32X:$src)),
2825 (VRSQRT14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2826def : Pat<(f32 (X86frsqrt (load addr:$src))),
2827 (VRSQRT14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2828 Requires<[OptForSize]>;
2829
2830def : Pat<(f32 (X86frcp FR32X:$src)),
2831 (VRCP14SSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
2832def : Pat<(f32 (X86frcp (load addr:$src))),
2833 (VRCP14SSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
2834 Requires<[OptForSize]>;
2835
2836multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
2837 X86MemOperand x86memop, RegisterClass RC,
2838 PatFrag mem_frag32, PatFrag mem_frag64,
2839 Intrinsic V4F32Int, Intrinsic V2F64Int,
2840 CD8VForm VForm> {
2841let ExeDomain = SSEPackedSingle in {
2842 // Intrinsic operation, reg.
2843 // Vector intrinsic operation, reg
2844 def PSr : AVX512AIi8<opcps, MRMSrcReg,
2845 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2846 !strconcat(OpcodeStr,
2847 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2848 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
2849
2850 // Vector intrinsic operation, mem
2851 def PSm : AVX512AIi8<opcps, MRMSrcMem,
2852 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2853 !strconcat(OpcodeStr,
2854 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2855 [(set RC:$dst,
2856 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
2857 EVEX_CD8<32, VForm>;
2858} // ExeDomain = SSEPackedSingle
2859
2860let ExeDomain = SSEPackedDouble in {
2861 // Vector intrinsic operation, reg
2862 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
2863 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
2864 !strconcat(OpcodeStr,
2865 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2866 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
2867
2868 // Vector intrinsic operation, mem
2869 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
2870 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
2871 !strconcat(OpcodeStr,
2872 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2873 [(set RC:$dst,
2874 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
2875 EVEX_CD8<64, VForm>;
2876} // ExeDomain = SSEPackedDouble
2877}
2878
2879multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
2880 string OpcodeStr,
2881 Intrinsic F32Int,
2882 Intrinsic F64Int> {
2883let ExeDomain = GenericDomain in {
2884 // Operation, reg.
2885 let hasSideEffects = 0 in
2886 def SSr : AVX512AIi8<opcss, MRMSrcReg,
2887 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
2888 !strconcat(OpcodeStr,
2889 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2890 []>;
2891
2892 // Intrinsic operation, reg.
2893 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
2894 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2895 !strconcat(OpcodeStr,
2896 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2897 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
2898
2899 // Intrinsic operation, mem.
2900 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
2901 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
2902 !strconcat(OpcodeStr,
2903 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2904 [(set VR128X:$dst, (F32Int VR128X:$src1,
2905 sse_load_f32:$src2, imm:$src3))]>,
2906 EVEX_CD8<32, CD8VT1>;
2907
2908 // Operation, reg.
2909 let hasSideEffects = 0 in
2910 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
2911 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
2912 !strconcat(OpcodeStr,
2913 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2914 []>, VEX_W;
2915
2916 // Intrinsic operation, reg.
2917 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
2918 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
2919 !strconcat(OpcodeStr,
2920 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2921 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
2922 VEX_W;
2923
2924 // Intrinsic operation, mem.
2925 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
2926 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
2927 !strconcat(OpcodeStr,
2928 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
2929 [(set VR128X:$dst,
2930 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
2931 VEX_W, EVEX_CD8<64, CD8VT1>;
2932} // ExeDomain = GenericDomain
2933}
2934
2935let Predicates = [HasAVX512] in {
2936 defm VRNDSCALE : avx512_fp_binop_rm<0x0A, 0x0B, "vrndscale",
2937 int_x86_avx512_rndscale_ss,
2938 int_x86_avx512_rndscale_sd>, EVEX_4V;
2939
2940 defm VRNDSCALEZ : avx512_fp_unop_rm<0x08, 0x09, "vrndscale", f256mem, VR512,
2941 memopv16f32, memopv8f64,
2942 int_x86_avx512_rndscale_ps_512,
2943 int_x86_avx512_rndscale_pd_512, CD8VF>,
2944 EVEX, EVEX_V512;
2945}
2946
2947def : Pat<(ffloor FR32X:$src),
2948 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
2949def : Pat<(f64 (ffloor FR64X:$src)),
2950 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
2951def : Pat<(f32 (fnearbyint FR32X:$src)),
2952 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
2953def : Pat<(f64 (fnearbyint FR64X:$src)),
2954 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
2955def : Pat<(f32 (fceil FR32X:$src)),
2956 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
2957def : Pat<(f64 (fceil FR64X:$src)),
2958 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
2959def : Pat<(f32 (frint FR32X:$src)),
2960 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
2961def : Pat<(f64 (frint FR64X:$src)),
2962 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
2963def : Pat<(f32 (ftrunc FR32X:$src)),
2964 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
2965def : Pat<(f64 (ftrunc FR64X:$src)),
2966 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
2967
2968def : Pat<(v16f32 (ffloor VR512:$src)),
2969 (VRNDSCALEZPSr VR512:$src, (i32 0x1))>;
2970def : Pat<(v16f32 (fnearbyint VR512:$src)),
2971 (VRNDSCALEZPSr VR512:$src, (i32 0xC))>;
2972def : Pat<(v16f32 (fceil VR512:$src)),
2973 (VRNDSCALEZPSr VR512:$src, (i32 0x2))>;
2974def : Pat<(v16f32 (frint VR512:$src)),
2975 (VRNDSCALEZPSr VR512:$src, (i32 0x4))>;
2976def : Pat<(v16f32 (ftrunc VR512:$src)),
2977 (VRNDSCALEZPSr VR512:$src, (i32 0x3))>;
2978
2979def : Pat<(v8f64 (ffloor VR512:$src)),
2980 (VRNDSCALEZPDr VR512:$src, (i32 0x1))>;
2981def : Pat<(v8f64 (fnearbyint VR512:$src)),
2982 (VRNDSCALEZPDr VR512:$src, (i32 0xC))>;
2983def : Pat<(v8f64 (fceil VR512:$src)),
2984 (VRNDSCALEZPDr VR512:$src, (i32 0x2))>;
2985def : Pat<(v8f64 (frint VR512:$src)),
2986 (VRNDSCALEZPDr VR512:$src, (i32 0x4))>;
2987def : Pat<(v8f64 (ftrunc VR512:$src)),
2988 (VRNDSCALEZPDr VR512:$src, (i32 0x3))>;
2989
2990//-------------------------------------------------
2991// Integer truncate and extend operations
2992//-------------------------------------------------
2993
2994multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
2995 RegisterClass dstRC, RegisterClass srcRC,
2996 RegisterClass KRC, X86MemOperand x86memop> {
2997 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
2998 (ins srcRC:$src),
2999 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3000 []>, EVEX;
3001
3002 def krr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
3003 (ins KRC:$mask, srcRC:$src),
3004 !strconcat(OpcodeStr,
3005 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
3006 []>, EVEX, EVEX_KZ;
3007
3008 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
3009 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3010 []>, EVEX;
3011}
3012defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
3013 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3014defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
3015 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3016defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
3017 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
3018defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
3019 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3020defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
3021 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3022defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
3023 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
3024defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
3025 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3026defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
3027 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3028defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
3029 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
3030defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
3031 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3032defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
3033 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3034defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
3035 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
3036defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
3037 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3038defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
3039 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3040defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
3041 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
3042
3043def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
3044def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
3045def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
3046def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
3047def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
3048
3049def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3050 (VPMOVDBkrr VK16WM:$mask, VR512:$src)>;
3051def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
3052 (VPMOVDWkrr VK16WM:$mask, VR512:$src)>;
3053def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3054 (VPMOVQWkrr VK8WM:$mask, VR512:$src)>;
3055def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
3056 (VPMOVQDkrr VK8WM:$mask, VR512:$src)>;
3057
3058
3059multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass DstRC,
3060 RegisterClass SrcRC, SDNode OpNode, PatFrag mem_frag,
3061 X86MemOperand x86memop, ValueType OpVT, ValueType InVT> {
3062
3063 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
3064 (ins SrcRC:$src),
3065 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
3066 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
3067 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
3068 (ins x86memop:$src),
3069 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),
3070 [(set DstRC:$dst,
3071 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
3072 EVEX;
3073}
3074
3075defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VR512, VR128X, X86vzext,
3076 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3077 EVEX_CD8<8, CD8VQ>;
3078defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VR512, VR128X, X86vzext,
3079 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3080 EVEX_CD8<8, CD8VO>;
3081defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VR512, VR256X, X86vzext,
3082 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3083 EVEX_CD8<16, CD8VH>;
3084defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VR512, VR128X, X86vzext,
3085 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3086 EVEX_CD8<16, CD8VQ>;
3087defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VR512, VR256X, X86vzext,
3088 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3089 EVEX_CD8<32, CD8VH>;
3090
3091defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VR512, VR128X, X86vsext,
3092 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
3093 EVEX_CD8<8, CD8VQ>;
3094defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VR512, VR128X, X86vsext,
3095 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
3096 EVEX_CD8<8, CD8VO>;
3097defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VR512, VR256X, X86vsext,
3098 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
3099 EVEX_CD8<16, CD8VH>;
3100defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VR512, VR128X, X86vsext,
3101 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
3102 EVEX_CD8<16, CD8VQ>;
3103defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VR512, VR256X, X86vsext,
3104 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
3105 EVEX_CD8<32, CD8VH>;
3106
3107//===----------------------------------------------------------------------===//
3108// GATHER - SCATTER Operations
3109
3110multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3111 RegisterClass RC, X86MemOperand memop> {
3112let mayLoad = 1,
3113 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
3114 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
3115 (ins RC:$src1, KRC:$mask, memop:$src2),
3116 !strconcat(OpcodeStr,
3117 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3118 []>, EVEX, EVEX_K;
3119}
3120defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
3121 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3122defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
3123 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3124
3125defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
3126 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3127defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
3128 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3129
3130defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
3131 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3132defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
3133 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3134
3135defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
3136 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3137defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
3138 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3139
3140multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3141 RegisterClass RC, X86MemOperand memop> {
3142let mayStore = 1, Constraints = "$mask = $mask_wb" in
3143 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
3144 (ins memop:$dst, KRC:$mask, RC:$src2),
3145 !strconcat(OpcodeStr,
3146 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
3147 []>, EVEX, EVEX_K;
3148}
3149
3150defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
3151 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3152defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
3153 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3154
3155defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
3156 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3157defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
3158 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3159
3160defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
3161 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3162defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
3163 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3164
3165defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
3166 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
3167defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
3168 EVEX_V512, EVEX_CD8<32, CD8VT1>;
3169
3170//===----------------------------------------------------------------------===//
3171// VSHUFPS - VSHUFPD Operations
3172
3173multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
3174 ValueType vt, string OpcodeStr, PatFrag mem_frag,
3175 Domain d> {
3176 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
3177 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3178 !strconcat(OpcodeStr,
3179 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3180 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
3181 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3182 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3183 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
3184 (ins RC:$src1, RC:$src2, i8imm:$src3),
3185 !strconcat(OpcodeStr,
3186 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3187 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
3188 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]3189 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3190}
3191
3192defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
3193 SSEPackedSingle>, EVEX_V512, EVEX_CD8<32, CD8VF>;
3194defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
3195 SSEPackedDouble>, OpSize, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3196
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]3197def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3198 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3199def : Pat<(v16i32 (X86Shufp VR512:$src1,
3200 (memopv16i32 addr:$src2), (i8 imm:$imm))),
3201 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
3202
3203def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3204 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
3205def : Pat<(v8i64 (X86Shufp VR512:$src1,
3206 (memopv8i64 addr:$src2), (i8 imm:$imm))),
3207 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3208
3209multiclass avx512_alignr<string OpcodeStr, RegisterClass RC,
3210 X86MemOperand x86memop> {
3211 def rri : AVX512AIi8<0x03, MRMSrcReg, (outs RC:$dst),
3212 (ins RC:$src1, RC:$src2, i8imm:$src3),
3213 !strconcat(OpcodeStr,
3214 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3215 []>, EVEX_4V;
3216 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs RC:$dst),
3217 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
3218 !strconcat(OpcodeStr,
3219 "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
3220 []>, EVEX_4V;
3221}
3222defm VALIGND : avx512_alignr<"valignd", VR512, i512mem>,
3223 EVEX_V512, EVEX_CD8<32, CD8VF>;
3224defm VALIGNQ : avx512_alignr<"valignq", VR512, i512mem>,
3225 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3226
3227def : Pat<(v16f32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3228 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3229def : Pat<(v8f64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3230 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3231def : Pat<(v16i32 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3232 (VALIGNDrri VR512:$src2, VR512:$src1, imm:$imm)>;
3233def : Pat<(v8i64 (X86PAlignr VR512:$src1, VR512:$src2, (i8 imm:$imm))),
3234 (VALIGNQrri VR512:$src2, VR512:$src1, imm:$imm)>;
3235
3236multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, RegisterClass RC,
3237 X86MemOperand x86memop> {
3238 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3239 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3240 EVEX;
3241 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
3242 (ins x86memop:$src),
3243 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), []>,
3244 EVEX;
3245}
3246
3247defm VPABSD : avx512_vpabs<0x1E, "vpabsd", VR512, i512mem>, EVEX_V512,
3248 EVEX_CD8<32, CD8VF>;
3249defm VPABSQ : avx512_vpabs<0x1F, "vpabsq", VR512, i512mem>, EVEX_V512, VEX_W,
3250 EVEX_CD8<64, CD8VF>;
3251