| Vasileios Kalintiris | 2ed214f | 2015-01-26 12:04:40 +0000 | [diff] [blame^] | 1 | ; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ |
| 2 | ; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 |
| 3 | ; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ |
| 4 | ; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 |
| 5 | ; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \ |
| 6 | ; RUN: -check-prefix=R2 -check-prefix=R2-R6 -check-prefix=NOT-R6 |
| 7 | ; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ |
| 8 | ; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6 |
| 9 | ; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ |
| 10 | ; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 |
| 11 | ; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ |
| 12 | ; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 |
| 13 | ; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ |
| 14 | ; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 |
| 15 | ; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ |
| 16 | ; RUN: -check-prefix=R2 -check-prefix=R2-R6 \ |
| 17 | ; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 |
| 18 | ; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ |
| 19 | ; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6 |
| 20 | |
| 21 | define signext i1 @urem_i1(i1 signext %a, i1 signext %b) { |
| 22 | entry: |
| 23 | ; ALL-LABEL: urem_i1: |
| 24 | |
| 25 | ; NOT-R6: andi $[[T0:[0-9]+]], $5, 1 |
| 26 | ; NOT-R6: andi $[[T1:[0-9]+]], $4, 1 |
| 27 | ; NOT-R6: divu $zero, $[[T1]], $[[T0]] |
| 28 | ; NOT-R6: teq $[[T0]], $zero, 7 |
| 29 | ; NOT-R6: mfhi $[[T2:[0-9]+]] |
| 30 | ; NOT-R6: sll $[[T3:[0-9]+]], $[[T2]], 31 |
| 31 | ; NOT-R6: sra $2, $[[T3]], 31 |
| 32 | |
| 33 | ; R6: andi $[[T0:[0-9]+]], $5, 1 |
| 34 | ; R6: andi $[[T1:[0-9]+]], $4, 1 |
| 35 | ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] |
| 36 | ; R6: teq $[[T0]], $zero, 7 |
| 37 | ; R6: sll $[[T3:[0-9]+]], $[[T2]], 31 |
| 38 | ; R6: sra $2, $[[T3]], 31 |
| 39 | |
| 40 | %r = urem i1 %a, %b |
| 41 | ret i1 %r |
| 42 | } |
| 43 | |
| 44 | define signext i8 @urem_i8(i8 signext %a, i8 signext %b) { |
| 45 | entry: |
| 46 | ; ALL-LABEL: urem_i8: |
| 47 | |
| 48 | ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255 |
| 49 | ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 255 |
| 50 | ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]] |
| 51 | ; NOT-R2-R6: teq $[[T0]], $zero, 7 |
| 52 | ; NOT-R2-R6: mfhi $[[T2:[0-9]+]] |
| 53 | ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 24 |
| 54 | ; NOT-R2-R6: sra $2, $[[T3]], 24 |
| 55 | |
| 56 | ; R2: andi $[[T0:[0-9]+]], $5, 255 |
| 57 | ; R2: andi $[[T1:[0-9]+]], $4, 255 |
| 58 | ; R2: divu $zero, $[[T1]], $[[T0]] |
| 59 | ; R2: teq $[[T0]], $zero, 7 |
| 60 | ; R2: mfhi $[[T2:[0-9]+]] |
| 61 | ; R2: seb $2, $[[T2]] |
| 62 | |
| 63 | ; R6: andi $[[T0:[0-9]+]], $5, 255 |
| 64 | ; R6: andi $[[T1:[0-9]+]], $4, 255 |
| 65 | ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] |
| 66 | ; R6: teq $[[T0]], $zero, 7 |
| 67 | ; R6: seb $2, $[[T2]] |
| 68 | |
| 69 | %r = urem i8 %a, %b |
| 70 | ret i8 %r |
| 71 | } |
| 72 | |
| 73 | define signext i16 @urem_i16(i16 signext %a, i16 signext %b) { |
| 74 | entry: |
| 75 | ; ALL-LABEL: urem_i16: |
| 76 | |
| 77 | ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535 |
| 78 | ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 65535 |
| 79 | ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]] |
| 80 | ; NOT-R2-R6: teq $[[T0]], $zero, 7 |
| 81 | ; NOT-R2-R6: mfhi $[[T2:[0-9]+]] |
| 82 | ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 16 |
| 83 | ; NOT-R2-R6: sra $2, $[[T3]], 16 |
| 84 | |
| 85 | ; R2: andi $[[T0:[0-9]+]], $5, 65535 |
| 86 | ; R2: andi $[[T1:[0-9]+]], $4, 65535 |
| 87 | ; R2: divu $zero, $[[T1]], $[[T0]] |
| 88 | ; R2: teq $[[T0]], $zero, 7 |
| 89 | ; R2: mfhi $[[T3:[0-9]+]] |
| 90 | ; R2: seh $2, $[[T2]] |
| 91 | |
| 92 | ; R6: andi $[[T0:[0-9]+]], $5, 65535 |
| 93 | ; R6: andi $[[T1:[0-9]+]], $4, 65535 |
| 94 | ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] |
| 95 | ; R6: teq $[[T0]], $zero, 7 |
| 96 | ; R6: seh $2, $[[T2]] |
| 97 | |
| 98 | %r = urem i16 %a, %b |
| 99 | ret i16 %r |
| 100 | } |
| 101 | |
| 102 | define signext i32 @urem_i32(i32 signext %a, i32 signext %b) { |
| 103 | entry: |
| 104 | ; ALL-LABEL: urem_i32: |
| 105 | |
| 106 | ; NOT-R6: divu $zero, $4, $5 |
| 107 | ; NOT-R6: teq $5, $zero, 7 |
| 108 | ; NOT-R6: mfhi $2 |
| 109 | |
| 110 | ; R6: modu $2, $4, $5 |
| 111 | ; R6: teq $5, $zero, 7 |
| 112 | |
| 113 | %r = urem i32 %a, %b |
| 114 | ret i32 %r |
| 115 | } |
| 116 | |
| 117 | define signext i64 @urem_i64(i64 signext %a, i64 signext %b) { |
| 118 | entry: |
| 119 | ; ALL-LABEL: urem_i64: |
| 120 | |
| 121 | ; GP32: lw $25, %call16(__umoddi3)($gp) |
| 122 | |
| 123 | ; GP64-NOT-R6: ddivu $zero, $4, $5 |
| 124 | ; GP64-NOT-R6: teq $5, $zero, 7 |
| 125 | ; GP64-NOT-R6: mfhi $2 |
| 126 | |
| 127 | ; 64R6: dmodu $2, $4, $5 |
| 128 | ; 64R6: teq $5, $zero, 7 |
| 129 | |
| 130 | %r = urem i64 %a, %b |
| 131 | ret i64 %r |
| 132 | } |