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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===- AMDGPUMCInstLower.cpp - Lower AMDGPU MachineInstr to an MCInst -----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Code to lower AMDGPU MachineInstrs to their corresponding MCInst.
12//
13//===----------------------------------------------------------------------===//
14//
15
16#include "AMDGPUMCInstLower.h"
17#include "AMDGPUAsmPrinter.h"
Tom Stellarded699252013-10-12 05:02:51 +000018#include "InstPrinter/AMDGPUInstPrinter.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000019#include "R600InstrInfo.h"
20#include "llvm/CodeGen/MachineBasicBlock.h"
21#include "llvm/CodeGen/MachineInstr.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +000022#include "llvm/IR/Constants.h"
Tom Stellarded699252013-10-12 05:02:51 +000023#include "llvm/MC/MCCodeEmitter.h"
Chandler Carruthbe810232013-01-02 10:22:59 +000024#include "llvm/MC/MCExpr.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000025#include "llvm/MC/MCInst.h"
Tom Stellarded699252013-10-12 05:02:51 +000026#include "llvm/MC/MCObjectStreamer.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000027#include "llvm/MC/MCStreamer.h"
28#include "llvm/Support/ErrorHandling.h"
Tom Stellarded699252013-10-12 05:02:51 +000029#include "llvm/Support/Format.h"
30#include <algorithm>
Tom Stellard75aadc22012-12-11 21:25:42 +000031
32using namespace llvm;
33
Tom Stellard9e90b582012-12-17 15:14:54 +000034AMDGPUMCInstLower::AMDGPUMCInstLower(MCContext &ctx):
35 Ctx(ctx)
36{ }
Tom Stellard75aadc22012-12-11 21:25:42 +000037
38void AMDGPUMCInstLower::lower(const MachineInstr *MI, MCInst &OutMI) const {
39 OutMI.setOpcode(MI->getOpcode());
40
David Blaikie2f771122014-04-05 22:42:04 +000041 for (const MachineOperand &MO : MI->explicit_operands()) {
Tom Stellard75aadc22012-12-11 21:25:42 +000042 MCOperand MCOp;
43 switch (MO.getType()) {
44 default:
45 llvm_unreachable("unknown operand type");
46 case MachineOperand::MO_FPImmediate: {
47 const APFloat &FloatValue = MO.getFPImm()->getValueAPF();
48 assert(&FloatValue.getSemantics() == &APFloat::IEEEsingle &&
49 "Only floating point immediates are supported at the moment.");
50 MCOp = MCOperand::CreateFPImm(FloatValue.convertToFloat());
51 break;
52 }
53 case MachineOperand::MO_Immediate:
54 MCOp = MCOperand::CreateImm(MO.getImm());
55 break;
56 case MachineOperand::MO_Register:
57 MCOp = MCOperand::CreateReg(MO.getReg());
58 break;
Tom Stellard9e90b582012-12-17 15:14:54 +000059 case MachineOperand::MO_MachineBasicBlock:
60 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
61 MO.getMBB()->getSymbol(), Ctx));
Tom Stellard75aadc22012-12-11 21:25:42 +000062 }
63 OutMI.addOperand(MCOp);
64 }
65}
66
67void AMDGPUAsmPrinter::EmitInstruction(const MachineInstr *MI) {
Tom Stellard9e90b582012-12-17 15:14:54 +000068 AMDGPUMCInstLower MCInstLowering(OutContext);
Tom Stellard75aadc22012-12-11 21:25:42 +000069
Tom Stellard9b9e9262014-02-28 21:36:41 +000070#ifdef _DEBUG
71 StringRef Err;
72 if (!TM.getInstrInfo()->verifyInstruction(MI, Err)) {
73 errs() << "Warning: Illegal instruction detected: " << Err << "\n";
74 MI->dump();
75 }
76#endif
Tom Stellard75aadc22012-12-11 21:25:42 +000077 if (MI->isBundle()) {
78 const MachineBasicBlock *MBB = MI->getParent();
79 MachineBasicBlock::const_instr_iterator I = MI;
80 ++I;
81 while (I != MBB->end() && I->isInsideBundle()) {
Tom Stellarded699252013-10-12 05:02:51 +000082 EmitInstruction(I);
Tom Stellard75aadc22012-12-11 21:25:42 +000083 ++I;
84 }
85 } else {
86 MCInst TmpInst;
87 MCInstLowering.lower(MI, TmpInst);
David Woodhousee6c13e42014-01-28 23:12:42 +000088 EmitToStreamer(OutStreamer, TmpInst);
Tom Stellarded699252013-10-12 05:02:51 +000089
90 if (DisasmEnabled) {
91 // Disassemble instruction/operands to text.
92 DisasmLines.resize(DisasmLines.size() + 1);
93 std::string &DisasmLine = DisasmLines.back();
94 raw_string_ostream DisasmStream(DisasmLine);
95
96 AMDGPUInstPrinter InstPrinter(*TM.getMCAsmInfo(), *TM.getInstrInfo(),
97 *TM.getRegisterInfo());
98 InstPrinter.printInst(&TmpInst, DisasmStream, StringRef());
99
100 // Disassemble instruction/operands to hex representation.
101 SmallVector<MCFixup, 4> Fixups;
102 SmallVector<char, 16> CodeBytes;
103 raw_svector_ostream CodeStream(CodeBytes);
104
105 MCObjectStreamer &ObjStreamer = (MCObjectStreamer &)OutStreamer;
106 MCCodeEmitter &InstEmitter = ObjStreamer.getAssembler().getEmitter();
David Woodhouse9784cef2014-01-28 23:13:07 +0000107 InstEmitter.EncodeInstruction(TmpInst, CodeStream, Fixups,
108 TM.getSubtarget<MCSubtargetInfo>());
Tom Stellarded699252013-10-12 05:02:51 +0000109 CodeStream.flush();
110
111 HexLines.resize(HexLines.size() + 1);
112 std::string &HexLine = HexLines.back();
113 raw_string_ostream HexStream(HexLine);
114
115 for (size_t i = 0; i < CodeBytes.size(); i += 4) {
116 unsigned int CodeDWord = *(unsigned int *)&CodeBytes[i];
117 HexStream << format("%s%08X", (i > 0 ? " " : ""), CodeDWord);
118 }
119
120 DisasmStream.flush();
121 DisasmLineMaxLen = std::max(DisasmLineMaxLen, DisasmLine.size());
122 }
Tom Stellard75aadc22012-12-11 21:25:42 +0000123 }
124}