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gerrit-public.fairphone.software / toolchain / llvm-project / 2fc5a786beaba1fbac1de65d78889d72b667f2d3 / . / llvm / test / CodeGen / AArch64 / vecreduce-and-legalization.ll
blob: 78032521a85e864ba312c71850aa84dbc9567ed5 [file] [log] [blame]
Nikita Popovaa7cfa72019-03-11 20:22:13 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
3
4declare i1 @llvm.experimental.vector.reduce.and.i1.v1i1(<1 x i1> %a)
5declare i8 @llvm.experimental.vector.reduce.and.i8.v1i8(<1 x i8> %a)
6declare i16 @llvm.experimental.vector.reduce.and.i16.v1i16(<1 x i16> %a)
7declare i24 @llvm.experimental.vector.reduce.and.i24.v1i24(<1 x i24> %a)
8declare i32 @llvm.experimental.vector.reduce.and.i32.v1i32(<1 x i32> %a)
9declare i64 @llvm.experimental.vector.reduce.and.i64.v1i64(<1 x i64> %a)
10declare i128 @llvm.experimental.vector.reduce.and.i128.v1i128(<1 x i128> %a)
11
12declare i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a)
13declare i8 @llvm.experimental.vector.reduce.and.i8.v9i8(<9 x i8> %a)
14declare i32 @llvm.experimental.vector.reduce.and.i32.v3i32(<3 x i32> %a)
15declare i1 @llvm.experimental.vector.reduce.and.i1.v4i1(<4 x i1> %a)
16declare i24 @llvm.experimental.vector.reduce.and.i24.v4i24(<4 x i24> %a)
17declare i128 @llvm.experimental.vector.reduce.and.i128.v2i128(<2 x i128> %a)
18declare i32 @llvm.experimental.vector.reduce.and.i32.v16i32(<16 x i32> %a)
19
20define i1 @test_v1i1(<1 x i1> %a) nounwind {
21; CHECK-LABEL: test_v1i1:
22; CHECK: // %bb.0:
23; CHECK-NEXT: and w0, w0, #0x1
24; CHECK-NEXT: ret
25 %b = call i1 @llvm.experimental.vector.reduce.and.i1.v1i1(<1 x i1> %a)
26 ret i1 %b
27}
28
29define i8 @test_v1i8(<1 x i8> %a) nounwind {
30; CHECK-LABEL: test_v1i8:
31; CHECK: // %bb.0:
32; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
33; CHECK-NEXT: umov w0, v0.b[0]
34; CHECK-NEXT: ret
35 %b = call i8 @llvm.experimental.vector.reduce.and.i8.v1i8(<1 x i8> %a)
36 ret i8 %b
37}
38
39define i16 @test_v1i16(<1 x i16> %a) nounwind {
40; CHECK-LABEL: test_v1i16:
41; CHECK: // %bb.0:
42; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
43; CHECK-NEXT: umov w0, v0.h[0]
44; CHECK-NEXT: ret
45 %b = call i16 @llvm.experimental.vector.reduce.and.i16.v1i16(<1 x i16> %a)
46 ret i16 %b
47}
48
49define i24 @test_v1i24(<1 x i24> %a) nounwind {
50; CHECK-LABEL: test_v1i24:
51; CHECK: // %bb.0:
52; CHECK-NEXT: ret
53 %b = call i24 @llvm.experimental.vector.reduce.and.i24.v1i24(<1 x i24> %a)
54 ret i24 %b
55}
56
57define i32 @test_v1i32(<1 x i32> %a) nounwind {
58; CHECK-LABEL: test_v1i32:
59; CHECK: // %bb.0:
60; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
61; CHECK-NEXT: fmov w0, s0
62; CHECK-NEXT: ret
63 %b = call i32 @llvm.experimental.vector.reduce.and.i32.v1i32(<1 x i32> %a)
64 ret i32 %b
65}
66
67define i64 @test_v1i64(<1 x i64> %a) nounwind {
68; CHECK-LABEL: test_v1i64:
69; CHECK: // %bb.0:
70; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
71; CHECK-NEXT: fmov x0, d0
72; CHECK-NEXT: ret
73 %b = call i64 @llvm.experimental.vector.reduce.and.i64.v1i64(<1 x i64> %a)
74 ret i64 %b
75}
76
77define i128 @test_v1i128(<1 x i128> %a) nounwind {
78; CHECK-LABEL: test_v1i128:
79; CHECK: // %bb.0:
80; CHECK-NEXT: ret
81 %b = call i128 @llvm.experimental.vector.reduce.and.i128.v1i128(<1 x i128> %a)
82 ret i128 %b
83}
84
85define i8 @test_v3i8(<3 x i8> %a) nounwind {
86; CHECK-LABEL: test_v3i8:
87; CHECK: // %bb.0:
88; CHECK-NEXT: and w8, w0, w1
89; CHECK-NEXT: and w8, w8, w2
90; CHECK-NEXT: and w0, w8, #0xff
91; CHECK-NEXT: ret
92 %b = call i8 @llvm.experimental.vector.reduce.and.i8.v3i8(<3 x i8> %a)
93 ret i8 %b
94}
95
96define i8 @test_v9i8(<9 x i8> %a) nounwind {
97; CHECK-LABEL: test_v9i8:
98; CHECK: // %bb.0:
99; CHECK-NEXT: mov w8, #-1
100; CHECK-NEXT: mov v0.b[9], w8
101; CHECK-NEXT: mov v0.b[10], w8
102; CHECK-NEXT: mov v0.b[11], w8
103; CHECK-NEXT: mov v0.b[12], w8
104; CHECK-NEXT: mov v0.b[13], w8
105; CHECK-NEXT: mov v0.b[14], w8
106; CHECK-NEXT: mov v0.b[15], w8
107; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
108; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
109; CHECK-NEXT: umov w8, v0.b[1]
110; CHECK-NEXT: umov w9, v0.b[0]
111; CHECK-NEXT: and w8, w9, w8
112; CHECK-NEXT: umov w9, v0.b[2]
113; CHECK-NEXT: and w8, w8, w9
114; CHECK-NEXT: umov w9, v0.b[3]
115; CHECK-NEXT: and w8, w8, w9
116; CHECK-NEXT: umov w9, v0.b[4]
117; CHECK-NEXT: and w8, w8, w9
118; CHECK-NEXT: umov w9, v0.b[5]
119; CHECK-NEXT: and w8, w8, w9
120; CHECK-NEXT: umov w9, v0.b[6]
121; CHECK-NEXT: and w8, w8, w9
122; CHECK-NEXT: umov w9, v0.b[7]
123; CHECK-NEXT: and w0, w8, w9
124; CHECK-NEXT: ret
125 %b = call i8 @llvm.experimental.vector.reduce.and.i8.v9i8(<9 x i8> %a)
126 ret i8 %b
127}
128
129define i32 @test_v3i32(<3 x i32> %a) nounwind {
130; CHECK-LABEL: test_v3i32:
131; CHECK: // %bb.0:
132; CHECK-NEXT: mov w8, #-1
133; CHECK-NEXT: mov v0.s[3], w8
134; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
135; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
136; CHECK-NEXT: mov w8, v0.s[1]
137; CHECK-NEXT: fmov w9, s0
138; CHECK-NEXT: and w0, w9, w8
139; CHECK-NEXT: ret
140 %b = call i32 @llvm.experimental.vector.reduce.and.i32.v3i32(<3 x i32> %a)
141 ret i32 %b
142}
143
144define i1 @test_v4i1(<4 x i1> %a) nounwind {
145; CHECK-LABEL: test_v4i1:
146; CHECK: // %bb.0:
147; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
148; CHECK-NEXT: umov w10, v0.h[1]
149; CHECK-NEXT: umov w11, v0.h[0]
150; CHECK-NEXT: umov w9, v0.h[2]
151; CHECK-NEXT: and w10, w11, w10
152; CHECK-NEXT: umov w8, v0.h[3]
153; CHECK-NEXT: and w9, w10, w9
154; CHECK-NEXT: and w8, w9, w8
155; CHECK-NEXT: and w0, w8, #0x1
156; CHECK-NEXT: ret
157 %b = call i1 @llvm.experimental.vector.reduce.and.i1.v4i1(<4 x i1> %a)
158 ret i1 %b
159}
160
161define i24 @test_v4i24(<4 x i24> %a) nounwind {
162; CHECK-LABEL: test_v4i24:
163; CHECK: // %bb.0:
164; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
165; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
166; CHECK-NEXT: mov w8, v0.s[1]
167; CHECK-NEXT: fmov w9, s0
168; CHECK-NEXT: and w0, w9, w8
169; CHECK-NEXT: ret
170 %b = call i24 @llvm.experimental.vector.reduce.and.i24.v4i24(<4 x i24> %a)
171 ret i24 %b
172}
173
174define i128 @test_v2i128(<2 x i128> %a) nounwind {
175; CHECK-LABEL: test_v2i128:
176; CHECK: // %bb.0:
177; CHECK-NEXT: and x0, x0, x2
178; CHECK-NEXT: and x1, x1, x3
179; CHECK-NEXT: ret
180 %b = call i128 @llvm.experimental.vector.reduce.and.i128.v2i128(<2 x i128> %a)
181 ret i128 %b
182}
183
184define i32 @test_v16i32(<16 x i32> %a) nounwind {
185; CHECK-LABEL: test_v16i32:
186; CHECK: // %bb.0:
187; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
188; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
189; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
190; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
191; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
192; CHECK-NEXT: mov w8, v0.s[1]
193; CHECK-NEXT: fmov w9, s0
194; CHECK-NEXT: and w0, w9, w8
195; CHECK-NEXT: ret
196 %b = call i32 @llvm.experimental.vector.reduce.and.i32.v16i32(<16 x i32> %a)
197 ret i32 %b
198}