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gerrit-public.fairphone.software / toolchain / llvm-project / 2fc5a786beaba1fbac1de65d78889d72b667f2d3 / . / llvm / test / CodeGen / AArch64 / vecreduce-fadd.ll
blob: b4576e7aa6552f0d82e49a5a49cb07c5613007a0 [file] [log] [blame]
Sander de Smalen72fc7b82019-03-13 15:18:27 +0000[diff] [blame]1; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=generic -asm-verbose=0 -mattr=+fullfp16 | FileCheck %s
2; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=generic -asm-verbose=0 | FileCheck %s --check-prefix=CHECKNOFP16
3
4define float @add_HalfS(<2 x float> %bin.rdx) {
5; CHECK-LABEL: add_HalfS:
6; CHECK: faddp s0, v0.2s
7; CHECK-NEXT: ret
8 %r = call fast float @llvm.experimental.vector.reduce.fadd.f32.v2f32(<2 x float> undef, <2 x float> %bin.rdx)
9 ret float %r
10}
11
12define half @add_HalfH(<4 x half> %bin.rdx) {
13; CHECK-LABEL: add_HalfH:
14; CHECK: mov h3, v0.h[1]
15; CHECK-NEXT: mov h1, v0.h[3]
16; CHECK-NEXT: mov h2, v0.h[2]
17; CHECK-NEXT: fadd h0, h0, h3
18; CHECK-NEXT: fadd h0, h0, h2
19; CHECK-NEXT: fadd h0, h0, h1
20; CHECK-NEXT: ret
21; CHECKNOFP16-LABEL: add_HalfH:
22; CHECKNOFP16-NOT: faddp
23; CHECKNOFP16-NOT: fadd h{{[0-9]+}}
24; CHECKNOFP16-NOT: fadd v{{[0-9]+}}.{{[0-9]}}h
25; CHECKNOFP16: ret
26 %r = call fast half @llvm.experimental.vector.reduce.fadd.f16.v4f16(<4 x half> undef, <4 x half> %bin.rdx)
27 ret half %r
28}
29
30
31define half @add_H(<8 x half> %bin.rdx) {
32; CHECK-LABEL: add_H:
33; CHECK: ext v1.16b, v0.16b, v0.16b, #8
34; CHECK-NEXT: fadd v0.4h, v0.4h, v1.4h
35; CHECK-NEXT: mov h1, v0.h[1]
36; CHECK-NEXT: mov h2, v0.h[2]
37; CHECK-NEXT: fadd h1, h0, h1
38; CHECK-NEXT: fadd h1, h1, h2
39; CHECK-NEXT: mov h0, v0.h[3]
40; CHECK-NEXT: fadd h0, h1, h0
41; CHECK-NEXT: ret
42
43; CHECKNOFP16-LABEL: add_H:
44; CHECKNOFP16-NOT: faddp
45; CHECKNOFP16-NOT: fadd h{{[0-9]+}}
46; CHECKNOFP16-NOT: fadd v{{[0-9]+}}.{{[0-9]}}h
47; CHECKNOFP16: ret
48 %r = call fast half @llvm.experimental.vector.reduce.fadd.f16.v8f16(<8 x half> undef, <8 x half> %bin.rdx)
49 ret half %r
50}
51
52define float @add_S(<4 x float> %bin.rdx) {
53; CHECK-LABEL: add_S:
54; CHECK: ext v1.16b, v0.16b, v0.16b, #8
55; CHECK-NEXT: fadd v0.2s, v0.2s, v1.2s
56; CHECK-NEXT: faddp s0, v0.2s
57; CHECK-NEXT: ret
58 %r = call fast float @llvm.experimental.vector.reduce.fadd.f32.v4f32(<4 x float> undef, <4 x float> %bin.rdx)
59 ret float %r
60}
61
62define double @add_D(<2 x double> %bin.rdx) {
63; CHECK-LABEL: add_D:
64; CHECK: faddp d0, v0.2d
65; CHECK-NEXT: ret
66 %r = call fast double @llvm.experimental.vector.reduce.fadd.f64.v2f64(<2 x double> undef, <2 x double> %bin.rdx)
67 ret double %r
68}
69
70define half @add_2H(<16 x half> %bin.rdx) {
71; CHECK-LABEL: add_2H:
72; CHECK: fadd v0.8h, v0.8h, v1.8h
73; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
74; CHECK-NEXT: fadd v0.4h, v0.4h, v1.4h
75; CHECK-NEXT: mov h1, v0.h[1]
76; CHECK-NEXT: mov h2, v0.h[2]
77; CHECK-NEXT: fadd h1, h0, h1
78; CHECK-NEXT: fadd h1, h1, h2
79; CHECK-NEXT: mov h0, v0.h[3]
80; CHECK-NEXT: fadd h0, h1, h0
81; CHECK-NEXT: ret
82; CHECKNOFP16-LABEL: add_2H:
83; CHECKNOFP16-NOT: faddp
84; CHECKNOFP16-NOT: fadd h{{[0-9]+}}
85; CHECKNOFP16-NOT: fadd v{{[0-9]+}}.{{[0-9]}}h
86; CHECKNOFP16: ret
87 %r = call fast half @llvm.experimental.vector.reduce.fadd.f16.v16f16(<16 x half> undef, <16 x half> %bin.rdx)
88 ret half %r
89}
90
91define float @add_2S(<8 x float> %bin.rdx) {
92; CHECK-LABEL: add_2S:
93; CHECK: fadd v0.4s, v0.4s, v1.4s
94; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
95; CHECK-NEXT: fadd v0.2s, v0.2s, v1.2s
96; CHECK-NEXT: faddp s0, v0.2s
97; CHECK-NEXT: ret
98 %r = call fast float @llvm.experimental.vector.reduce.fadd.f32.v8f32(<8 x float> undef, <8 x float> %bin.rdx)
99 ret float %r
100}
101
102define double @add_2D(<4 x double> %bin.rdx) {
103; CHECK-LABEL: add_2D:
104; CHECK: fadd v0.2d, v0.2d, v1.2d
105; CHECK-NEXT: faddp d0, v0.2d
106; CHECK-NEXT: ret
107 %r = call fast double @llvm.experimental.vector.reduce.fadd.f64.v4f64(<4 x double> undef, <4 x double> %bin.rdx)
108 ret double %r
109}
110
111; Function Attrs: nounwind readnone
112declare half @llvm.experimental.vector.reduce.fadd.f16.v4f16(<4 x half>, <4 x half>)
113declare half @llvm.experimental.vector.reduce.fadd.f16.v8f16(<8 x half>, <8 x half>)
114declare half @llvm.experimental.vector.reduce.fadd.f16.v16f16(<16 x half>, <16 x half>)
115declare float @llvm.experimental.vector.reduce.fadd.f32.v2f32(<2 x float>, <2 x float>)
116declare float @llvm.experimental.vector.reduce.fadd.f32.v4f32(<4 x float>, <4 x float>)
117declare float @llvm.experimental.vector.reduce.fadd.f32.v8f32(<8 x float>, <8 x float>)
118declare double @llvm.experimental.vector.reduce.fadd.f64.v2f64(<2 x double>, <2 x double>)
119declare double @llvm.experimental.vector.reduce.fadd.f64.v4f64(<4 x double>, <4 x double>)