| Krzysztof Parzyszek | 8f174dd | 2017-10-11 15:51:44 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=hexagon < %s | FileCheck %s |
| 2 | |
| 3 | ; Test that the instruction ordering code in the pipeliner fixes up dependences |
| 4 | ; between post-increment register definitions and uses so that the register |
| 5 | ; allocator does not allocate an additional register. The following test case |
| 6 | ; should generate a single packet. |
| 7 | |
| 8 | ; CHECK: loop0(.LBB0_[[LOOP:.]], |
| 9 | ; CHECK: .LBB0_[[LOOP]]: |
| 10 | ; CHECK: { |
| 11 | ; CHECK-NOT: { |
| 12 | ; CHECK: :endloop0 |
| 13 | |
| 14 | define void @test(i64* nocapture %v1, i64 %v2, i32 %len) local_unnamed_addr #0 { |
| 15 | entry: |
| 16 | %cmp7 = icmp sgt i32 %len, 0 |
| 17 | br i1 %cmp7, label %for.body, label %for.end |
| 18 | |
| 19 | for.body: |
| 20 | %arrayidx.phi = phi i64* [ %arrayidx.inc, %for.body ], [ %v1, %entry ] |
| 21 | %i.08 = phi i32 [ %inc, %for.body ], [ 0, %entry ] |
| 22 | %0 = load i64, i64* %arrayidx.phi, align 8 |
| 23 | %1 = tail call i64 @llvm.hexagon.M2.mmpyul.rs1(i64 %0, i64 %v2) |
| 24 | store i64 %1, i64* %arrayidx.phi, align 8 |
| 25 | %inc = add nuw nsw i32 %i.08, 1 |
| 26 | %exitcond = icmp eq i32 %inc, %len |
| 27 | %arrayidx.inc = getelementptr i64, i64* %arrayidx.phi, i32 1 |
| 28 | br i1 %exitcond, label %for.end, label %for.body |
| 29 | |
| 30 | for.end: |
| 31 | ret void |
| 32 | } |
| 33 | |
| 34 | declare i64 @llvm.hexagon.M2.mmpyul.rs1(i64, i64) #1 |
| 35 | |
| 36 | attributes #0 = { nounwind "target-cpu"="hexagonv60" } |
| 37 | attributes #1 = { nounwind readnone } |