Krzysztof Parzyszek | 046090d | 2018-03-12 14:01:28 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=hexagon < %s |
| 2 | ; REQUIRES: asserts |
| 3 | |
| 4 | ; Test that the pipeliner doesn't assert when renaming a phi |
| 5 | ; that looks like: a = PHI b, a |
| 6 | |
| 7 | %s.0 = type { i32, i32*, [0 x i32], [0 x i32], [1 x i32] } |
| 8 | %s.1 = type { %s.2, %s.4, %s.5 } |
| 9 | %s.2 = type { %s.3 } |
| 10 | %s.3 = type { i32 } |
| 11 | %s.4 = type { i32 } |
| 12 | %s.5 = type { [0 x i32], [0 x i32 (i32*, i32*, i32*, i32*, i32*, i32, i32*)*] } |
| 13 | |
| 14 | @g0 = external global i32, align 4 |
| 15 | @g1 = external global %s.0, align 4 |
| 16 | @g2 = external global i32, align 4 |
| 17 | @g3 = external global i32, align 4 |
| 18 | @g4 = external global i32*, align 4 |
| 19 | |
| 20 | define void @f0(%s.1* nocapture readonly %a0) #0 { |
| 21 | b0: |
| 22 | %v0 = alloca [0 x i32], align 4 |
| 23 | %v1 = load i32, i32* @g0, align 4 |
| 24 | %v2 = load i32, i32* undef, align 4 |
| 25 | %v3 = load i32*, i32** getelementptr inbounds (%s.0, %s.0* @g1, i32 0, i32 1), align 4 |
| 26 | %v4 = load i32, i32* @g2, align 4 |
| 27 | %v5 = sub i32 0, %v4 |
| 28 | %v6 = getelementptr inbounds i32, i32* %v3, i32 %v5 |
| 29 | %v7 = load i32, i32* undef, align 4 |
| 30 | switch i32 %v7, label %b15 [ |
| 31 | i32 0, label %b1 |
| 32 | i32 1, label %b2 |
| 33 | ] |
| 34 | |
| 35 | b1: ; preds = %b0 |
| 36 | store i32 0, i32* @g3, align 4 |
| 37 | br label %b2 |
| 38 | |
| 39 | b2: ; preds = %b1, %b0 |
| 40 | %v8 = icmp eq i32 %v1, 0 |
| 41 | %v9 = icmp sgt i32 %v2, 0 |
| 42 | %v10 = getelementptr inbounds [0 x i32], [0 x i32]* %v0, i32 0, i32 0 |
| 43 | %v11 = sdiv i32 %v2, 2 |
| 44 | %v12 = add i32 %v11, -1 |
| 45 | %v13 = getelementptr inbounds [0 x i32], [0 x i32]* %v0, i32 0, i32 1 |
| 46 | %v14 = getelementptr inbounds %s.1, %s.1* %a0, i32 0, i32 2, i32 1, i32 %v1 |
| 47 | %v15 = sub i32 1, %v4 |
| 48 | %v16 = getelementptr inbounds i32, i32* %v3, i32 %v15 |
| 49 | %v17 = sdiv i32 %v2, 4 |
| 50 | %v18 = icmp slt i32 %v2, -3 |
| 51 | %v19 = add i32 %v2, -1 |
| 52 | %v20 = lshr i32 %v19, 2 |
| 53 | %v21 = mul i32 %v20, 4 |
| 54 | %v22 = add i32 %v21, 4 |
| 55 | %v23 = add i32 %v11, -2 |
| 56 | %v24 = add i32 %v17, 1 |
| 57 | %v25 = select i1 %v18, i32 1, i32 %v24 |
| 58 | br label %b4 |
| 59 | |
| 60 | b3: ; preds = %b14 |
| 61 | store i32 %v25, i32* @g3, align 4 |
| 62 | br label %b4 |
| 63 | |
| 64 | b4: ; preds = %b13, %b3, %b2 |
| 65 | %v26 = phi i32 [ undef, %b2 ], [ %v42, %b3 ], [ %v42, %b13 ] |
| 66 | %v27 = phi i32 [ undef, %b2 ], [ 0, %b3 ], [ 0, %b13 ] |
| 67 | %v28 = phi i32 [ undef, %b2 ], [ %v30, %b3 ], [ %v30, %b13 ] |
| 68 | %v29 = phi i32 [ undef, %b2 ], [ %v43, %b3 ], [ %v43, %b13 ] |
| 69 | %v30 = phi i32 [ undef, %b2 ], [ undef, %b3 ], [ 0, %b13 ] |
| 70 | br i1 %v8, label %b6, label %b5 |
| 71 | |
| 72 | b5: ; preds = %b5, %b4 |
| 73 | br label %b5 |
| 74 | |
| 75 | b6: ; preds = %b4 |
| 76 | br i1 %v9, label %b8, label %b7 |
| 77 | |
| 78 | b7: ; preds = %b6 |
| 79 | store i32 0, i32* @g3, align 4 |
| 80 | br label %b11 |
| 81 | |
| 82 | b8: ; preds = %b6 |
| 83 | br i1 undef, label %b9, label %b11 |
| 84 | |
| 85 | b9: ; preds = %b8 |
| 86 | %v31 = load i32*, i32** @g4, align 4 |
| 87 | br label %b10 |
| 88 | |
| 89 | b10: ; preds = %b10, %b9 |
| 90 | %v32 = phi i32 [ %v22, %b9 ], [ %v39, %b10 ] |
| 91 | %v33 = phi i32 [ %v29, %b9 ], [ %v38, %b10 ] |
| 92 | %v34 = add nsw i32 %v32, %v28 |
| 93 | %v35 = shl i32 %v34, 1 |
| 94 | %v36 = getelementptr inbounds i32, i32* %v31, i32 %v35 |
| 95 | %v37 = load i32, i32* %v36, align 4 |
| 96 | %v38 = select i1 false, i32 0, i32 %v33 |
| 97 | %v39 = add nsw i32 %v32, 1 |
| 98 | store i32 %v39, i32* @g3, align 4 |
| 99 | %v40 = icmp slt i32 %v39, 0 |
| 100 | br i1 %v40, label %b10, label %b11 |
| 101 | |
| 102 | b11: ; preds = %b10, %b8, %b7 |
| 103 | %v41 = phi i32 [ %v29, %b8 ], [ %v29, %b7 ], [ %v38, %b10 ] |
| 104 | br i1 false, label %b12, label %b13 |
| 105 | |
| 106 | b12: ; preds = %b11 |
| 107 | br label %b13 |
| 108 | |
| 109 | b13: ; preds = %b12, %b11 |
| 110 | %v42 = load i32, i32* %v10, align 4 |
| 111 | %v43 = select i1 false, i32 %v41, i32 1 |
| 112 | br i1 %v18, label %b4, label %b14 |
| 113 | |
| 114 | b14: ; preds = %b14, %b13 |
| 115 | br i1 false, label %b14, label %b3 |
| 116 | |
| 117 | b15: ; preds = %b0 |
| 118 | ret void |
| 119 | } |
| 120 | |
| 121 | attributes #0 = { nounwind "target-cpu"="hexagonv55" } |